#ifndef __OCTEON_WNPA3850_SHARED_H__
#define __OCTEON_WNPA3850_SHARED_H__

/* Board delay in picoseconds */
#define DDR_BOARD_DELAY		3500 /* ~2500 - ~4500 work so use 3500 */

#define DDR_WNPA3850_REG_LMC_DELAY_CLK		4
#define DDR_WNPA3850_REG_LMC_DELAY_CMD		0
#define DDR_WNPA3850_REG_LMC_DELAY_DQ		4

#define DDR_WNPA3850_UNBUF_LMC_DELAY_CLK	4
#define DDR_WNPA3850_UNBUF_LMC_DELAY_CMD	0
#define DDR_WNPA3850_UNBUF_LMC_DELAY_DQ		4

#define OCTEON_WNPA3850_DRAM_SOCKET_CONFIGURATION0 \
	{{0x50, 0x54}, {NULL, NULL}}

#define OCTEON_WNPA3850_BOARD_EEPROM_TWSI_ADDR 0x52

/* Construct a static initializer for the ddr_configuration_t variable that holds
** (almost) all of the information required for DDR initialization.
*/
#define OCTEON_WNPA3850_DDR_CONFIGURATION   \
/* Interface 0 */   \
{   \
    .dimm_config_table = {OCTEON_WNPA3850_DRAM_SOCKET_CONFIGURATION0, DIMM_CONFIG_TERMINATOR},   \
    .unbuffered = {   \
        .ddr_board_delay = DDR_BOARD_DELAY,   \
        .lmc_delay_clk = DDR_WNPA3850_UNBUF_LMC_DELAY_CLK,   \
        .lmc_delay_cmd = DDR_WNPA3850_UNBUF_LMC_DELAY_CMD,   \
        .lmc_delay_dq = DDR_WNPA3850_UNBUF_LMC_DELAY_DQ,   \
        },    \
    .registered = {   \
        .ddr_board_delay = DDR_BOARD_DELAY,   \
        .lmc_delay_clk = DDR_WNPA3850_REG_LMC_DELAY_CLK,   \
        .lmc_delay_cmd = DDR_WNPA3850_REG_LMC_DELAY_CMD,   \
        .lmc_delay_dq = DDR_WNPA3850_REG_LMC_DELAY_DQ,   \
        },   \
    .odt_1rank_config = {   \
        CN38XX_DRAM_ODT_1RANK_CONFIGURATION,   \
        },   \
    .odt_2rank_config = {   \
        CN38XX_DRAM_ODT_2RANK_CONFIGURATION,   \
        },   \
}

#endif   /* __OCTEON_WNPA3850_SHARED_H__ */

