/**     npa_56x4_eth_tests.h
 **
 ** Author: Ted Schmitz
 ** Date of original creation July 31, 2009
 **
 **     This file contains all the symbols and definitions to support the Ethernet 
 ** tests for the TNPA-5651x AMC board.
 **
 **
 **/
extern void octeon_eth_test(void);

extern void BIST_PingHandler(uchar * pkt, unsigned dest, unsigned src, 
                             unsigned len);

/**    The following symbols define the options that acn be used to call 
 ** function "get_phy_mode()" followed by the values that can be returned 
 ** by this function.
 **/
#define ETH_PORT_0 0            /* select front panel port 0 */
#define ETH_PORT_1 1            /* select front panel port 1 */

#define ROUT_AMC_CONN 0    /* seltd port is 10G routed out the AMC connector */
#define ROUT_1G_FRONT 1    /* seltd port is 1G routed out the front panel */
#define ROUT_10G_FRONT 10  /* seltd port is 10G routed out the front panel */

#define MAX_WAIT_FOR_LINK_LOOP 20 /* max loops to wait for link "up" status */

/**   The following symbol is define to enable the normal network messages
 ** when the PING function is called.  Make sure to "undefine" this symbol 
 ** for normal operation of the BIST tests
 **/
#define ENABLE_NET_DEBUG_MSGS /* enable normal network debug nessages */

/**  The following default IP address is used if the environment variable
 ** "ipaddr" is not yet set when the Ethernet tests are executed.  The "0"
 ** in the address is supposed to be replace with the Ethernet port number
 ** such as: eth0 = 0, eth1 = 1, etc.
 **/
#define DEFAULT_IP_ADRS "192.168.0.100"

/**  The following symbols define the official system device names 
 ** defined in Uboot for the various Ethernet ports on this board.
 **/
#define QLM1_ETH_NAME      "octeth0"     /* front port 0/fabric ports 8-11 */
#define QLM3_ETH_NAME      "octeth1"     /* front port 1/fabric ports 12-20 */
#define QLM2_GE_PORT0      "e1000#0"     /* port 0 on 82571/base port 0 */
#define QLM2_GE_PORT1      "e1000#1"     /* port 1 on 82571/base port 1 */

#define PCS_VEND_SPEC_LB    0x0020       /* bit in PCSvendor specific reg
                                            to enable loopback data override mode
                                            on PHY in 10 GB mode */
#define PMA_CORE_CNT2_REG_LB 0x0040      /* bit in PMA/PMD core control reg 2
                                            that enables loop back mode on PHY
                                            in 1 BG mode */
#define PMA_VEND_SPEC1_LB    0x8000      /* bit in PMA/PMD vendor specific 1 reg
                                            to enable loopback data override mode
                                            on PHY in 10 GB mode */
#define PCS_CNT1_LB          0x4000       /* bit in PCS control register 1
                                            to enable loop back mode on PHY in 
                                            10 GB mode */

