

#define OCTEON_EBH5610_EEPROM_TWSI_ADDR        (0x56)
/* SPD EEPROM addresses on EBH5610 board */
#define EBH5610_DIMM_0_SPD_TWSI_ADDR    0x50
#define EBH5610_DIMM_1_SPD_TWSI_ADDR    0x51
#define EBH5610_INTERFACE1_DIMM_0_SPD_TWSI_ADDR    0x52
#define EBH5610_INTERFACE1_DIMM_1_SPD_TWSI_ADDR    0x53

/* EBH5610 has two DRAM interfaces each with two DIMM sockets. DIMM 0
** must be populated on at least one interface. Each interface used
** must have at least DIMM 0 populated.
*/
#define OCTEON_EBH5610_DRAM_SOCKET_CONFIGURATION \
    {EBH5610_DIMM_0_SPD_TWSI_ADDR, 0}, \
    {EBH5610_DIMM_1_SPD_TWSI_ADDR, 0}

#define OCTEON_EBH5610_DRAM_SOCKET_CONFIGURATION_INTERFACE1 \
    {EBH5610_INTERFACE1_DIMM_0_SPD_TWSI_ADDR, 0}, \
    {EBH5610_INTERFACE1_DIMM_1_SPD_TWSI_ADDR, 0}

/*
** CN56xx Registered configuration
*/
#define OCTEON_CN56XX_EBH5610_DDR_BOARD_DELAY		4200
#define OCTEON_CN56XX_EBH5610_LMC_DELAY_CLK		7
#define OCTEON_CN56XX_EBH5610_LMC_DELAY_CMD		0
#define OCTEON_CN56XX_EBH5610_LMC_DELAY_DQ		6

/*
** CN56xx Unbuffered configuration
*/
#define OCTEON_CN56XX_EBH5610_UNB_DDR_BOARD_DELAY	4600
#define OCTEON_CN56XX_EBH5610_UNB_LMC_DELAY_CLK		13
#define OCTEON_CN56XX_EBH5610_UNB_LMC_DELAY_CMD  	0
#define OCTEON_CN56XX_EBH5610_UNB_LMC_DELAY_DQ		8

