/*
Copyright (C) 2008, 2009  GE Intelligent Platforms, Inc
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
*/

/* redHawkReg.c - redHawk register definitions */

/*
DESCRIPTION:
    This file provides redHawk register definitions

INCLUDES:

*/

#include <common.h>
#include <config.h>
#include <command.h>

#ifndef CONFIG_OCTEON_AT5810
#include "systypes.h"
#endif

#include "rhRegif.h"
#include "rhAsicReg.h"

/*
 * redHawk ASIC register set.
 *
 *  { regid,
 *    name,
 *    offset, hiBit, loBit, properties,
 *    instances offset, maximum instances, default value,
 *    mdio DA, mdio MA }
 */

reginfo_t redHawkRegs[redHawk_REG_MAX+1] = {
    { StsRegCoDevice,
      "StsRegCoDevice",
      AD_StsRegCoDevice, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRedHawkID,
      "CfgRegCoRedHawkID",
      AD_CfgRegCoRedHawkID, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { VarRegCoGlobalSoftReset,
      "VarRegCoGlobalSoftReset",
      AD_VarRegCoGlobalSoftReset, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0,
      "VarRegCoFunctionActivate0",
      AD_VarRegCoFunctionActivate0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarLedEnP1,
      "VarRegCoFunctionActivate0__VarLedEnP1",
      AD_VarRegCoFunctionActivate0, 31, 31, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarShadowRegsEnP1,
      "VarRegCoFunctionActivate0__VarShadowRegsEnP1",
      AD_VarRegCoFunctionActivate0, 30, 30, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarTxXauiXmacEnP1,
      "VarRegCoFunctionActivate0__VarTxXauiXmacEnP1",
      AD_VarRegCoFunctionActivate0, 29, 29, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxXauiXmacEnP1,
      "VarRegCoFunctionActivate0__VarRxXauiXmacEnP1",
      AD_VarRegCoFunctionActivate0, 28, 28, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxMacActivateP1,
      "VarRegCoFunctionActivate0__VarRxMacActivateP1",
      AD_VarRegCoFunctionActivate0, 27, 27, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxDropControlEnP1,
      "VarRegCoFunctionActivate0__VarRxDropControlEnP1",
      AD_VarRegCoFunctionActivate0, 26, 26, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxEnqueuerEnP1,
      "VarRegCoFunctionActivate0__VarRxEnqueuerEnP1",
      AD_VarRegCoFunctionActivate0, 25, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxQueueManagerEnP1,
      "VarRegCoFunctionActivate0__VarRxQueueManagerEnP1",
      AD_VarRegCoFunctionActivate0, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxMemReqEnP1,
      "VarRegCoFunctionActivate0__VarRxMemReqEnP1",
      AD_VarRegCoFunctionActivate0, 23, 23, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxFCRAMEnP1,
      "VarRegCoFunctionActivate0__VarRxFCRAMEnP1",
      AD_VarRegCoFunctionActivate0, 22, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxDequeuerEnP1,
      "VarRegCoFunctionActivate0__VarRxDequeuerEnP1",
      AD_VarRegCoFunctionActivate0, 21, 21, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarTxVlanCtrlEnP1,
      "VarRegCoFunctionActivate0__VarTxVlanCtrlEnP1",
      AD_VarRegCoFunctionActivate0, 20, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarTxMacActivateP1,
      "VarRegCoFunctionActivate0__VarTxMacActivateP1",
      AD_VarRegCoFunctionActivate0, 19, 19, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarLedEnP0,
      "VarRegCoFunctionActivate0__VarLedEnP0",
      AD_VarRegCoFunctionActivate0, 18, 18, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarShadowRegsEnP0,
      "VarRegCoFunctionActivate0__VarShadowRegsEnP0",
      AD_VarRegCoFunctionActivate0, 17, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarTxXauiXmacEnP0,
      "VarRegCoFunctionActivate0__VarTxXauiXmacEnP0",
      AD_VarRegCoFunctionActivate0, 16, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxXauiXmacEnP0,
      "VarRegCoFunctionActivate0__VarRxXauiXmacEnP0",
      AD_VarRegCoFunctionActivate0, 15, 15, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxMacActivateP0,
      "VarRegCoFunctionActivate0__VarRxMacActivateP0",
      AD_VarRegCoFunctionActivate0, 14, 14, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxDropControlEnP0,
      "VarRegCoFunctionActivate0__VarRxDropControlEnP0",
      AD_VarRegCoFunctionActivate0, 13, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxEnqueuerEnP0,
      "VarRegCoFunctionActivate0__VarRxEnqueuerEnP0",
      AD_VarRegCoFunctionActivate0, 12, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxQueueManagerEnP0,
      "VarRegCoFunctionActivate0__VarRxQueueManagerEnP0",
      AD_VarRegCoFunctionActivate0, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxMemReqEnP0,
      "VarRegCoFunctionActivate0__VarRxMemReqEnP0",
      AD_VarRegCoFunctionActivate0, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxFCRAMEnP0,
      "VarRegCoFunctionActivate0__VarRxFCRAMEnP0",
      AD_VarRegCoFunctionActivate0, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxDequeuerEnP0,
      "VarRegCoFunctionActivate0__VarRxDequeuerEnP0",
      AD_VarRegCoFunctionActivate0, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarTxVlanCtrlEnP0,
      "VarRegCoFunctionActivate0__VarTxVlanCtrlEnP0",
      AD_VarRegCoFunctionActivate0, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarTxMacActivateP0,
      "VarRegCoFunctionActivate0__VarTxMacActivateP0",
      AD_VarRegCoFunctionActivate0, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarTxSSpiEn,
      "VarRegCoFunctionActivate0__VarTxSSpiEn",
      AD_VarRegCoFunctionActivate0, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarTxPSpiEn,
      "VarRegCoFunctionActivate0__VarTxPSpiEn",
      AD_VarRegCoFunctionActivate0, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxSSpiEn,
      "VarRegCoFunctionActivate0__VarRxSSpiEn",
      AD_VarRegCoFunctionActivate0, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarRxPSpiEn,
      "VarRegCoFunctionActivate0__VarRxPSpiEn",
      AD_VarRegCoFunctionActivate0, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarTempSensorEn,
      "VarRegCoFunctionActivate0__VarTempSensorEn",
      AD_VarRegCoFunctionActivate0, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate0__VarMDIOActivate,
      "VarRegCoFunctionActivate0__VarMDIOActivate",
      AD_VarRegCoFunctionActivate0, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1,
      "VarRegCoFunctionActivate1",
      AD_VarRegCoFunctionActivate1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarCpuToLineEn,
      "VarRegCoFunctionActivate1__VarCpuToLineEn",
      AD_VarRegCoFunctionActivate1, 16, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarTxMemMgrEn1,
      "VarRegCoFunctionActivate1__VarTxMemMgrEn1",
      AD_VarRegCoFunctionActivate1, 15, 15, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarTxMemMgrEn0,
      "VarRegCoFunctionActivate1__VarTxMemMgrEn0",
      AD_VarRegCoFunctionActivate1, 14, 14, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarTxPortIntfEnP1,
      "VarRegCoFunctionActivate1__VarTxPortIntfEnP1",
      AD_VarRegCoFunctionActivate1, 13, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarRxPortIntfEnP1,
      "VarRegCoFunctionActivate1__VarRxPortIntfEnP1",
      AD_VarRegCoFunctionActivate1, 12, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarTxPortIntfEnP0,
      "VarRegCoFunctionActivate1__VarTxPortIntfEnP0",
      AD_VarRegCoFunctionActivate1, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarRxPortIntfEnP0,
      "VarRegCoFunctionActivate1__VarRxPortIntfEnP0",
      AD_VarRegCoFunctionActivate1, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarBERTEnP1,
      "VarRegCoFunctionActivate1__VarBERTEnP1",
      AD_VarRegCoFunctionActivate1, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarBERTEnP0,
      "VarRegCoFunctionActivate1__VarBERTEnP0",
      AD_VarRegCoFunctionActivate1, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarXFICoreVCOEnP1,
      "VarRegCoFunctionActivate1__VarXFICoreVCOEnP1",
      AD_VarRegCoFunctionActivate1, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarXFICoreTxEnP1,
      "VarRegCoFunctionActivate1__VarXFICoreTxEnP1",
      AD_VarRegCoFunctionActivate1, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarXFICoreRxEnP1,
      "VarRegCoFunctionActivate1__VarXFICoreRxEnP1",
      AD_VarRegCoFunctionActivate1, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarXFICoreVCOEnP0,
      "VarRegCoFunctionActivate1__VarXFICoreVCOEnP0",
      AD_VarRegCoFunctionActivate1, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarXFICoreTxEnP0,
      "VarRegCoFunctionActivate1__VarXFICoreTxEnP0",
      AD_VarRegCoFunctionActivate1, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarXFICoreRxEnP0,
      "VarRegCoFunctionActivate1__VarXFICoreRxEnP0",
      AD_VarRegCoFunctionActivate1, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarRxFCRAMHmEnP1,
      "VarRegCoFunctionActivate1__VarRxFCRAMHmEnP1",
      AD_VarRegCoFunctionActivate1, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegCoFunctionActivate1__VarRxFCRAMHmEnP0,
      "VarRegCoFunctionActivate1__VarRxFCRAMHmEnP0",
      AD_VarRegCoFunctionActivate1, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoCPUMode,
      "CfgRegCoCPUMode",
      AD_CfgRegCoCPUMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoCPUMode__TestMode,
      "CfgRegCoCPUMode__TestMode",
      AD_CfgRegCoCPUMode, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoCPUMode__AddrDataMuxMode,
      "CfgRegCoCPUMode__AddrDataMuxMode",
      AD_CfgRegCoCPUMode, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClockDiv0,
      "CfgRegCoClockDiv0",
      AD_CfgRegCoClockDiv0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClockDiv0__I2CClk1,
      "CfgRegCoClockDiv0__I2CClk1",
      AD_CfgRegCoClockDiv0, 31, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClockDiv0__I2CClk0,
      "CfgRegCoClockDiv0__I2CClk0",
      AD_CfgRegCoClockDiv0, 23, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClockDiv0__Reserved,
      "CfgRegCoClockDiv0__Reserved",
      AD_CfgRegCoClockDiv0, 15, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClockDiv0__MDIOClk,
      "CfgRegCoClockDiv0__MDIOClk",
      AD_CfgRegCoClockDiv0, 7, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClockDiv1,
      "CfgRegCoClockDiv1",
      AD_CfgRegCoClockDiv1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClockDiv1__TEMPClk,
      "CfgRegCoClockDiv1__TEMPClk",
      AD_CfgRegCoClockDiv1, 23, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClockDiv1__LEDClk1,
      "CfgRegCoClockDiv1__LEDClk1",
      AD_CfgRegCoClockDiv1, 15, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClockDiv1__LEDClk0,
      "CfgRegCoClockDiv1__LEDClk0",
      AD_CfgRegCoClockDiv1, 7, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLoopbackMode,
      "CfgRegCoLoopbackMode",
      AD_CfgRegCoLoopbackMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLoopbackMode__XauiRx2TxLpbkP1,
      "CfgRegCoLoopbackMode__XauiRx2TxLpbkP1",
      AD_CfgRegCoLoopbackMode, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLoopbackMode__XauiRx2TxLpbkP0,
      "CfgRegCoLoopbackMode__XauiRx2TxLpbkP0",
      AD_CfgRegCoLoopbackMode, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLoopbackMode__SSpiRx2TxLpbk,
      "CfgRegCoLoopbackMode__SSpiRx2TxLpbk",
      AD_CfgRegCoLoopbackMode, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLoopbackMode__PSpiRx2TxLpbk,
      "CfgRegCoLoopbackMode__PSpiRx2TxLpbk",
      AD_CfgRegCoLoopbackMode, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLoopbackMode__SSpiTx2RxLpbk,
      "CfgRegCoLoopbackMode__SSpiTx2RxLpbk",
      AD_CfgRegCoLoopbackMode, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLoopbackMode__PSpiTx2RxLpbk,
      "CfgRegCoLoopbackMode__PSpiTx2RxLpbk",
      AD_CfgRegCoLoopbackMode, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLoopbackMode__XGMIIRx2TxLpbkP1,
      "CfgRegCoLoopbackMode__XGMIIRx2TxLpbkP1",
      AD_CfgRegCoLoopbackMode, 3, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLoopbackMode__XGMIIRx2TxLpbkP0,
      "CfgRegCoLoopbackMode__XGMIIRx2TxLpbkP0",
      AD_CfgRegCoLoopbackMode, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMemoryMode,
      "CfgRegCoMemoryMode",
      AD_CfgRegCoMemoryMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMemoryMode__CfgMemModeP1,
      "CfgRegCoMemoryMode__CfgMemModeP1",
      AD_CfgRegCoMemoryMode, 5, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMemoryMode__CfgMemModeP0,
      "CfgRegCoMemoryMode__CfgMemModeP0",
      AD_CfgRegCoMemoryMode, 2, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSystemInterfaceMode,
      "CfgRegCoSystemInterfaceMode",
      AD_CfgRegCoSystemInterfaceMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSystemInterfaceMode__XAUIInterfaceP1,
      "CfgRegCoSystemInterfaceMode__XAUIInterfaceP1",
      AD_CfgRegCoSystemInterfaceMode, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSystemInterfaceMode__SPIInterfaceP1,
      "CfgRegCoSystemInterfaceMode__SPIInterfaceP1",
      AD_CfgRegCoSystemInterfaceMode, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSystemInterfaceMode__XAUIInterfaceP0,
      "CfgRegCoSystemInterfaceMode__XAUIInterfaceP0",
      AD_CfgRegCoSystemInterfaceMode, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSystemInterfaceMode__SPIInterfaceP0,
      "CfgRegCoSystemInterfaceMode__SPIInterfaceP0",
      AD_CfgRegCoSystemInterfaceMode, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLineInterfaceMode,
      "CfgRegCoLineInterfaceMode",
      AD_CfgRegCoLineInterfaceMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLineInterfaceMode__XAUIInterfaceP1,
      "CfgRegCoLineInterfaceMode__XAUIInterfaceP1",
      AD_CfgRegCoLineInterfaceMode, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLineInterfaceMode__XFIInterfaceP1,
      "CfgRegCoLineInterfaceMode__XFIInterfaceP1",
      AD_CfgRegCoLineInterfaceMode, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLineInterfaceMode__XAUIInterfaceP0,
      "CfgRegCoLineInterfaceMode__XAUIInterfaceP0",
      AD_CfgRegCoLineInterfaceMode, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLineInterfaceMode__XFIInterfaceP0,
      "CfgRegCoLineInterfaceMode__XFIInterfaceP0",
      AD_CfgRegCoLineInterfaceMode, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoOversubscriptionMode,
      "CfgRegCoOversubscriptionMode",
      AD_CfgRegCoOversubscriptionMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoOversubscriptionMode__Mode4_1,
      "CfgRegCoOversubscriptionMode__Mode4_1",
      AD_CfgRegCoOversubscriptionMode, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoOversubscriptionMode__Mode2_1,
      "CfgRegCoOversubscriptionMode__Mode2_1",
      AD_CfgRegCoOversubscriptionMode, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoOversubscriptionMode__Mode1_1,
      "CfgRegCoOversubscriptionMode__Mode1_1",
      AD_CfgRegCoOversubscriptionMode, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoCascadeHarrierMode,
      "CfgRegCoCascadeHarrierMode",
      AD_CfgRegCoCascadeHarrierMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoAPSMode,
      "CfgRegCoAPSMode",
      AD_CfgRegCoAPSMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoAPSMode__SwitchPort,
      "CfgRegCoAPSMode__SwitchPort",
      AD_CfgRegCoAPSMode, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoAPSMode__Standby,
      "CfgRegCoAPSMode__Standby",
      AD_CfgRegCoAPSMode, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoAPSMode__ActiveDuplicate,
      "CfgRegCoAPSMode__ActiveDuplicate",
      AD_CfgRegCoAPSMode, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoCutThruMode,
      "CfgRegCoCutThruMode",
      AD_CfgRegCoCutThruMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoCutThruMode__CfgEgressCutThruModeEnP1,
      "CfgRegCoCutThruMode__CfgEgressCutThruModeEnP1",
      AD_CfgRegCoCutThruMode, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoCutThruMode__CfgEgressCutThruModeEnP0,
      "CfgRegCoCutThruMode__CfgEgressCutThruModeEnP0",
      AD_CfgRegCoCutThruMode, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoCutThruMode__CfgIngressCutThruModeEnP1,
      "CfgRegCoCutThruMode__CfgIngressCutThruModeEnP1",
      AD_CfgRegCoCutThruMode, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoCutThruMode__CfgIngressCutThruModeEnP0,
      "CfgRegCoCutThruMode__CfgIngressCutThruModeEnP0",
      AD_CfgRegCoCutThruMode, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode,
      "CfgRegCoMDIOMode",
      AD_CfgRegCoMDIOMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode__CfgRegMDIOIntMasterExtSlaveP1,
      "CfgRegCoMDIOMode__CfgRegMDIOIntMasterExtSlaveP1",
      AD_CfgRegCoMDIOMode, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode__CfgRegMDIOIntMasterExtSlaveP0,
      "CfgRegCoMDIOMode__CfgRegMDIOIntMasterExtSlaveP0",
      AD_CfgRegCoMDIOMode, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode__CfgRegMDIOIntMasterXFIP1,
      "CfgRegCoMDIOMode__CfgRegMDIOIntMasterXFIP1",
      AD_CfgRegCoMDIOMode, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode__CfgRegMDIOIntMasterXFIP0,
      "CfgRegCoMDIOMode__CfgRegMDIOIntMasterXFIP0",
      AD_CfgRegCoMDIOMode, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode__CfgRegMDIOExtMasterXFIP1,
      "CfgRegCoMDIOMode__CfgRegMDIOExtMasterXFIP1",
      AD_CfgRegCoMDIOMode, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode__CfgRegMDIOExtMasterXFIP0,
      "CfgRegCoMDIOMode__CfgRegMDIOExtMasterXFIP0",
      AD_CfgRegCoMDIOMode, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode__CfgRegMDIOIntMasterXAUIP1,
      "CfgRegCoMDIOMode__CfgRegMDIOIntMasterXAUIP1",
      AD_CfgRegCoMDIOMode, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode__CfgRegMDIOIntMasterXAUIP0,
      "CfgRegCoMDIOMode__CfgRegMDIOIntMasterXAUIP0",
      AD_CfgRegCoMDIOMode, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode__CfgRegMDIOExtMasterXAUIP1,
      "CfgRegCoMDIOMode__CfgRegMDIOExtMasterXAUIP1",
      AD_CfgRegCoMDIOMode, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOMode__CfgRegMDIOExtMasterXAUIP0,
      "CfgRegCoMDIOMode__CfgRegMDIOExtMasterXAUIP0",
      AD_CfgRegCoMDIOMode, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOSlaveSetup,
      "CfgRegCoMDIOSlaveSetup",
      AD_CfgRegCoMDIOSlaveSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOSlaveSetup__CfgRegMDIOIntSlavePortAddrP1,
      "CfgRegCoMDIOSlaveSetup__CfgRegMDIOIntSlavePortAddrP1",
      AD_CfgRegCoMDIOSlaveSetup, 9, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMDIOSlaveSetup__CfgRegMDIOIntSlavePortAddrP0,
      "CfgRegCoMDIOSlaveSetup__CfgRegMDIOIntSlavePortAddrP0",
      AD_CfgRegCoMDIOSlaveSetup, 4, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoDiagSel,
      "CfgRegCoDiagSel",
      AD_CfgRegCoDiagSel, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoDiagExtBitSel,
      "CfgRegCoDiagExtBitSel",
      AD_CfgRegCoDiagExtBitSel, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCoDiagData,
      "StsRegCoDiagData",
      AD_StsRegCoDiagData, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCoClkMon,
      "StsRegCoClkMon",
      AD_StsRegCoClkMon, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCoClkMonInterrupt,
      "StsRegCoClkMonInterrupt",
      AD_StsRegCoClkMonInterrupt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCoClkMonInterruptMask,
      "StsRegCoClkMonInterruptMask",
      AD_StsRegCoClkMonInterruptMask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkSelect,
      "CfgRegCoClkSelect",
      AD_CfgRegCoClkSelect, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkSelect__SRSPIUseHardMacroClk,
      "CfgRegCoClkSelect__SRSPIUseHardMacroClk",
      AD_CfgRegCoClkSelect, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkSelect__PRSPIUseHardMacroClk,
      "CfgRegCoClkSelect__PRSPIUseHardMacroClk",
      AD_CfgRegCoClkSelect, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkSelect__SPIPLLBypassSelectP1,
      "CfgRegCoClkSelect__SPIPLLBypassSelectP1",
      AD_CfgRegCoClkSelect, 7, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkSelect__SPIPLLBypassSelectP0,
      "CfgRegCoClkSelect__SPIPLLBypassSelectP0",
      AD_CfgRegCoClkSelect, 5, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkSelect__XGClkSelectP1,
      "CfgRegCoClkSelect__XGClkSelectP1",
      AD_CfgRegCoClkSelect, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkSelect__XGClkSelectP0,
      "CfgRegCoClkSelect__XGClkSelectP0",
      AD_CfgRegCoClkSelect, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkSelect__SysClkSelect,
      "CfgRegCoClkSelect__SysClkSelect",
      AD_CfgRegCoClkSelect, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkPowerDown,
      "CfgRegCoClkPowerDown",
      AD_CfgRegCoClkPowerDown, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkPowerDown__XmacClkDownP1,
      "CfgRegCoClkPowerDown__XmacClkDownP1",
      AD_CfgRegCoClkPowerDown, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoClkPowerDown__XmacClkDownP0,
      "CfgRegCoClkPowerDown__XmacClkDownP0",
      AD_CfgRegCoClkPowerDown, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup,
      "CfgRegCoSpiSetup",
      AD_CfgRegCoSpiSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__SSpiStatusSpeed125,
      "CfgRegCoSpiSetup__SSpiStatusSpeed125",
      AD_CfgRegCoSpiSetup, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__PSpiStatusSpeed125,
      "CfgRegCoSpiSetup__PSpiStatusSpeed125",
      AD_CfgRegCoSpiSetup, 23, 23, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__UseDivRefclk,
      "CfgRegCoSpiSetup__UseDivRefclk",
      AD_CfgRegCoSpiSetup, 22, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__SSpiStatusSpeed,
      "CfgRegCoSpiSetup__SSpiStatusSpeed",
      AD_CfgRegCoSpiSetup, 21, 21, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__PSpiStatusSpeed,
      "CfgRegCoSpiSetup__PSpiStatusSpeed",
      AD_CfgRegCoSpiSetup, 20, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__CfgPriTSClkFlip,
      "CfgRegCoSpiSetup__CfgPriTSClkFlip",
      AD_CfgRegCoSpiSetup, 19, 19, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__CfgSecTSClkFlip,
      "CfgRegCoSpiSetup__CfgSecTSClkFlip",
      AD_CfgRegCoSpiSetup, 18, 18, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__Reserved3,
      "CfgRegCoSpiSetup__Reserved3",
      AD_CfgRegCoSpiSetup, 17, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__VarNPSIEn1,
      "CfgRegCoSpiSetup__VarNPSIEn1",
      AD_CfgRegCoSpiSetup, 16, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__Cfgsparein_spi0,
      "CfgRegCoSpiSetup__Cfgsparein_spi0",
      AD_CfgRegCoSpiSetup, 15, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__VarNPSIEn0,
      "CfgRegCoSpiSetup__VarNPSIEn0",
      AD_CfgRegCoSpiSetup, 12, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__STSpiPowerDn,
      "CfgRegCoSpiSetup__STSpiPowerDn",
      AD_CfgRegCoSpiSetup, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__STSpiPllEn,
      "CfgRegCoSpiSetup__STSpiPllEn",
      AD_CfgRegCoSpiSetup, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__SRSpiPowerDn,
      "CfgRegCoSpiSetup__SRSpiPowerDn",
      AD_CfgRegCoSpiSetup, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__SRSpiPllEn,
      "CfgRegCoSpiSetup__SRSpiPllEn",
      AD_CfgRegCoSpiSetup, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__PTSpiPowerDn,
      "CfgRegCoSpiSetup__PTSpiPowerDn",
      AD_CfgRegCoSpiSetup, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__PTSpiPllEn,
      "CfgRegCoSpiSetup__PTSpiPllEn",
      AD_CfgRegCoSpiSetup, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__PRSpiPowerDn,
      "CfgRegCoSpiSetup__PRSpiPowerDn",
      AD_CfgRegCoSpiSetup, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__PRSpiPllEn,
      "CfgRegCoSpiSetup__PRSpiPllEn",
      AD_CfgRegCoSpiSetup, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__SSpiHalfSpeed,
      "CfgRegCoSpiSetup__SSpiHalfSpeed",
      AD_CfgRegCoSpiSetup, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__PSpiHalfSpeed,
      "CfgRegCoSpiSetup__PSpiHalfSpeed",
      AD_CfgRegCoSpiSetup, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__SSpiQuarterSpeed,
      "CfgRegCoSpiSetup__SSpiQuarterSpeed",
      AD_CfgRegCoSpiSetup, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSpiSetup__PSpiQuarterSpeed,
      "CfgRegCoSpiSetup__PSpiQuarterSpeed",
      AD_CfgRegCoSpiSetup, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRxpSpiHMPLLReg,
      "CfgRegCoRxpSpiHMPLLReg",
      AD_CfgRegCoRxpSpiHMPLLReg, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRxpSpiHMPLLReg__rxpll_byp,
      "CfgRegCoRxpSpiHMPLLReg__rxpll_byp",
      AD_CfgRegCoRxpSpiHMPLLReg, 21, 21, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRxpSpiHMPLLReg__rx_refclk_sel,
      "CfgRegCoRxpSpiHMPLLReg__rx_refclk_sel",
      AD_CfgRegCoRxpSpiHMPLLReg, 20, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRxpSpiHMPLLReg__rx_fbclk_sel,
      "CfgRegCoRxpSpiHMPLLReg__rx_fbclk_sel",
      AD_CfgRegCoRxpSpiHMPLLReg, 19, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRxpSpiHMPLLReg__RSPI_PLL,
      "CfgRegCoRxpSpiHMPLLReg__RSPI_PLL",
      AD_CfgRegCoRxpSpiHMPLLReg, 16, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRxsSpiHMPLLReg,
      "CfgRegCoRxsSpiHMPLLReg",
      AD_CfgRegCoRxsSpiHMPLLReg, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRxsSpiHMPLLReg__rxpll_byp,
      "CfgRegCoRxsSpiHMPLLReg__rxpll_byp",
      AD_CfgRegCoRxsSpiHMPLLReg, 21, 21, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRxsSpiHMPLLReg__rx_refclk_sel,
      "CfgRegCoRxsSpiHMPLLReg__rx_refclk_sel",
      AD_CfgRegCoRxsSpiHMPLLReg, 20, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRxsSpiHMPLLReg__rx_fbclk_sel,
      "CfgRegCoRxsSpiHMPLLReg__rx_fbclk_sel",
      AD_CfgRegCoRxsSpiHMPLLReg, 19, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoRxsSpiHMPLLReg__RSPI_PLL,
      "CfgRegCoRxsSpiHMPLLReg__RSPI_PLL",
      AD_CfgRegCoRxsSpiHMPLLReg, 16, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoTxPSpiHMPLLReg,
      "CfgRegCoTxPSpiHMPLLReg",
      AD_CfgRegCoTxPSpiHMPLLReg, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoTxPSpiHMPLLReg__refclk_sel,
      "CfgRegCoTxPSpiHMPLLReg__refclk_sel",
      AD_CfgRegCoTxPSpiHMPLLReg, 20, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoTxPSpiHMPLLReg__fbclk_sel,
      "CfgRegCoTxPSpiHMPLLReg__fbclk_sel",
      AD_CfgRegCoTxPSpiHMPLLReg, 19, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoTxPSpiHMPLLReg__TSPI_PLL,
      "CfgRegCoTxPSpiHMPLLReg__TSPI_PLL",
      AD_CfgRegCoTxPSpiHMPLLReg, 16, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoTxSSpiHMPLLReg,
      "CfgRegCoTxSSpiHMPLLReg",
      AD_CfgRegCoTxSSpiHMPLLReg, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoTxSSpiHMPLLReg__refclk_sel,
      "CfgRegCoTxSSpiHMPLLReg__refclk_sel",
      AD_CfgRegCoTxSSpiHMPLLReg, 20, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoTxSSpiHMPLLReg__fbclk_sel,
      "CfgRegCoTxSSpiHMPLLReg__fbclk_sel",
      AD_CfgRegCoTxSSpiHMPLLReg, 19, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoTxSSpiHMPLLReg__TSPI_PLL,
      "CfgRegCoTxSSpiHMPLLReg__TSPI_PLL",
      AD_CfgRegCoTxSSpiHMPLLReg, 16, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { StsRegCoInterruptSource0,
      "StsRegCoInterruptSource0",
      AD_StsRegCoInterruptSource0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCoInterruptSource1,
      "StsRegCoInterruptSource1",
      AD_StsRegCoInterruptSource1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCoTempSensorOut,
      "StsRegCoTempSensorOut",
      AD_StsRegCoTempSensorOut, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFISetup,
      "CfgRegCoXFISetup",
      AD_CfgRegCoXFISetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFISetup__Cfgsparein_xfi1,
      "CfgRegCoXFISetup__Cfgsparein_xfi1",
      AD_CfgRegCoXFISetup, 13, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFISetup__Cfgsparein_xfi0,
      "CfgRegCoXFISetup__Cfgsparein_xfi0",
      AD_CfgRegCoXFISetup, 9, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFISetup__Cfgrxlockref_xfi1,
      "CfgRegCoXFISetup__Cfgrxlockref_xfi1",
      AD_CfgRegCoXFISetup, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFISetup__Cfgrxlockref_xfi0,
      "CfgRegCoXFISetup__Cfgrxlockref_xfi0",
      AD_CfgRegCoXFISetup, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFISetup__MuxExtBERTAlignP1,
      "CfgRegCoXFISetup__MuxExtBERTAlignP1",
      AD_CfgRegCoXFISetup, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFISetup__MuxExtBERTAlignP0,
      "CfgRegCoXFISetup__MuxExtBERTAlignP0",
      AD_CfgRegCoXFISetup, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFISetup__CfgBERTMux,
      "CfgRegCoXFISetup__CfgBERTMux",
      AD_CfgRegCoXFISetup, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFISetup__NOTUSED,
      "CfgRegCoXFISetup__NOTUSED",
      AD_CfgRegCoXFISetup, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0,
      "CfgRegCoXAUISetup0",
      AD_CfgRegCoXAUISetup0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgAHBMDIOSelectP1,
      "CfgRegCoXAUISetup0__CfgAHBMDIOSelectP1",
      AD_CfgRegCoXAUISetup0, 27, 27, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgAHBMDIOSelectP0,
      "CfgRegCoXAUISetup0__CfgAHBMDIOSelectP0",
      AD_CfgRegCoXAUISetup0, 26, 26, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgTERM1_xaui1,
      "CfgRegCoXAUISetup0__CfgTERM1_xaui1",
      AD_CfgRegCoXAUISetup0, 25, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgTERM0_xaui1,
      "CfgRegCoXAUISetup0__CfgTERM0_xaui1",
      AD_CfgRegCoXAUISetup0, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgTERM1_xaui0,
      "CfgRegCoXAUISetup0__CfgTERM1_xaui0",
      AD_CfgRegCoXAUISetup0, 23, 23, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgTERM0_xaui0,
      "CfgRegCoXAUISetup0__CfgTERM0_xaui0",
      AD_CfgRegCoXAUISetup0, 22, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgXAUIPortAddressP1,
      "CfgRegCoXAUISetup0__CfgXAUIPortAddressP1",
      AD_CfgRegCoXAUISetup0, 21, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgXAUIPortAddressP0,
      "CfgRegCoXAUISetup0__CfgXAUIPortAddressP0",
      AD_CfgRegCoXAUISetup0, 16, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgXAUIDevAddressP1,
      "CfgRegCoXAUISetup0__CfgXAUIDevAddressP1",
      AD_CfgRegCoXAUISetup0, 11, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgXAUIDevAddressP0,
      "CfgRegCoXAUISetup0__CfgXAUIDevAddressP0",
      AD_CfgRegCoXAUISetup0, 9, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgXAUIModeP1,
      "CfgRegCoXAUISetup0__CfgXAUIModeP1",
      AD_CfgRegCoXAUISetup0, 7, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup0__CfgXAUIModeP0,
      "CfgRegCoXAUISetup0__CfgXAUIModeP0",
      AD_CfgRegCoXAUISetup0, 3, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1,
      "CfgRegCoXAUISetup1",
      AD_CfgRegCoXAUISetup1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgensyncdet_D_xaui1,
      "CfgRegCoXAUISetup1__Cfgensyncdet_D_xaui1",
      AD_CfgRegCoXAUISetup1, 31, 31, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgensyncdet_C_xaui1,
      "CfgRegCoXAUISetup1__Cfgensyncdet_C_xaui1",
      AD_CfgRegCoXAUISetup1, 30, 30, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgensyncdet_B_xaui1,
      "CfgRegCoXAUISetup1__Cfgensyncdet_B_xaui1",
      AD_CfgRegCoXAUISetup1, 29, 29, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgensyncdet_A_xaui1,
      "CfgRegCoXAUISetup1__Cfgensyncdet_A_xaui1",
      AD_CfgRegCoXAUISetup1, 28, 28, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__CfgsigDet_D_xaui1,
      "CfgRegCoXAUISetup1__CfgsigDet_D_xaui1",
      AD_CfgRegCoXAUISetup1, 27, 27, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__CfgsigDet_C_xaui1,
      "CfgRegCoXAUISetup1__CfgsigDet_C_xaui1",
      AD_CfgRegCoXAUISetup1, 26, 26, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__CfgsigDet_B_xaui1,
      "CfgRegCoXAUISetup1__CfgsigDet_B_xaui1",
      AD_CfgRegCoXAUISetup1, 25, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__CfgsigDet_A_xaui1,
      "CfgRegCoXAUISetup1__CfgsigDet_A_xaui1",
      AD_CfgRegCoXAUISetup1, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgseltxcd_xaui1,
      "CfgRegCoXAUISetup1__Cfgseltxcd_xaui1",
      AD_CfgRegCoXAUISetup1, 23, 23, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgseltxab_xaui1,
      "CfgRegCoXAUISetup1__Cfgseltxab_xaui1",
      AD_CfgRegCoXAUISetup1, 22, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgselrxcd_xaui1,
      "CfgRegCoXAUISetup1__Cfgselrxcd_xaui1",
      AD_CfgRegCoXAUISetup1, 21, 21, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgselrxab_xaui1,
      "CfgRegCoXAUISetup1__Cfgselrxab_xaui1",
      AD_CfgRegCoXAUISetup1, 20, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfglpen_D_xaui1,
      "CfgRegCoXAUISetup1__Cfglpen_D_xaui1",
      AD_CfgRegCoXAUISetup1, 19, 19, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfglpen_C_xaui1,
      "CfgRegCoXAUISetup1__Cfglpen_C_xaui1",
      AD_CfgRegCoXAUISetup1, 18, 18, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfglpen_B_xaui1,
      "CfgRegCoXAUISetup1__Cfglpen_B_xaui1",
      AD_CfgRegCoXAUISetup1, 17, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfglpen_A_xaui1,
      "CfgRegCoXAUISetup1__Cfglpen_A_xaui1",
      AD_CfgRegCoXAUISetup1, 16, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgensyncdet_D_xaui0,
      "CfgRegCoXAUISetup1__Cfgensyncdet_D_xaui0",
      AD_CfgRegCoXAUISetup1, 15, 15, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgensyncdet_C_xaui0,
      "CfgRegCoXAUISetup1__Cfgensyncdet_C_xaui0",
      AD_CfgRegCoXAUISetup1, 14, 14, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgensyncdet_B_xaui0,
      "CfgRegCoXAUISetup1__Cfgensyncdet_B_xaui0",
      AD_CfgRegCoXAUISetup1, 13, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgensyncdet_A_xaui0,
      "CfgRegCoXAUISetup1__Cfgensyncdet_A_xaui0",
      AD_CfgRegCoXAUISetup1, 12, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__CfgsigDet_D_xaui0,
      "CfgRegCoXAUISetup1__CfgsigDet_D_xaui0",
      AD_CfgRegCoXAUISetup1, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__CfgsigDet_C_xaui0,
      "CfgRegCoXAUISetup1__CfgsigDet_C_xaui0",
      AD_CfgRegCoXAUISetup1, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__CfgsigDet_B_xaui0,
      "CfgRegCoXAUISetup1__CfgsigDet_B_xaui0",
      AD_CfgRegCoXAUISetup1, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__CfgsigDet_A_xaui0,
      "CfgRegCoXAUISetup1__CfgsigDet_A_xaui0",
      AD_CfgRegCoXAUISetup1, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgseltxcd_xaui0,
      "CfgRegCoXAUISetup1__Cfgseltxcd_xaui0",
      AD_CfgRegCoXAUISetup1, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgseltxab_xaui0,
      "CfgRegCoXAUISetup1__Cfgseltxab_xaui0",
      AD_CfgRegCoXAUISetup1, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgselrxcd_xaui0,
      "CfgRegCoXAUISetup1__Cfgselrxcd_xaui0",
      AD_CfgRegCoXAUISetup1, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfgselrxab_xaui0,
      "CfgRegCoXAUISetup1__Cfgselrxab_xaui0",
      AD_CfgRegCoXAUISetup1, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfglpen_D_xaui0,
      "CfgRegCoXAUISetup1__Cfglpen_D_xaui0",
      AD_CfgRegCoXAUISetup1, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfglpen_C_xaui0,
      "CfgRegCoXAUISetup1__Cfglpen_C_xaui0",
      AD_CfgRegCoXAUISetup1, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfglpen_B_xaui0,
      "CfgRegCoXAUISetup1__Cfglpen_B_xaui0",
      AD_CfgRegCoXAUISetup1, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup1__Cfglpen_A_xaui0,
      "CfgRegCoXAUISetup1__Cfglpen_A_xaui0",
      AD_CfgRegCoXAUISetup1, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2,
      "CfgRegCoXAUISetup2",
      AD_CfgRegCoXAUISetup2, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2__CfgrxdetP1,
      "CfgRegCoXAUISetup2__CfgrxdetP1",
      AD_CfgRegCoXAUISetup2, 17, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2__CfgrxdetP0,
      "CfgRegCoXAUISetup2__CfgrxdetP0",
      AD_CfgRegCoXAUISetup2, 16, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2__CfgtdenfifoP1,
      "CfgRegCoXAUISetup2__CfgtdenfifoP1",
      AD_CfgRegCoXAUISetup2, 15, 15, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2__CfgtdenfifoP0,
      "CfgRegCoXAUISetup2__CfgtdenfifoP0",
      AD_CfgRegCoXAUISetup2, 14, 14, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2__CfgenstretchP1,
      "CfgRegCoXAUISetup2__CfgenstretchP1",
      AD_CfgRegCoXAUISetup2, 13, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2__CfgenstretchP0,
      "CfgRegCoXAUISetup2__CfgenstretchP0",
      AD_CfgRegCoXAUISetup2, 12, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2__CfgemphInP1,
      "CfgRegCoXAUISetup2__CfgemphInP1",
      AD_CfgRegCoXAUISetup2, 11, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2__CfgemphInP0,
      "CfgRegCoXAUISetup2__CfgemphInP0",
      AD_CfgRegCoXAUISetup2, 8, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2__CfgtfbdivP1,
      "CfgRegCoXAUISetup2__CfgtfbdivP1",
      AD_CfgRegCoXAUISetup2, 5, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUISetup2__CfgtfbdivP0,
      "CfgRegCoXAUISetup2__CfgtfbdivP0",
      AD_CfgRegCoXAUISetup2, 2, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoLSIPortSelect,
      "CfgRegCoLSIPortSelect",
      AD_CfgRegCoLSIPortSelect, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig,
      "CfgRegCoXAUIIOConfig",
      AD_CfgRegCoXAUIIOConfig, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__XAUI1_TXON,
      "CfgRegCoXAUIIOConfig__XAUI1_TXON",
      AD_CfgRegCoXAUIIOConfig, 15, 15, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__XAUI1_RefPd,
      "CfgRegCoXAUIIOConfig__XAUI1_RefPd",
      AD_CfgRegCoXAUIIOConfig, 14, 14, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__XAUI1_Hiterm,
      "CfgRegCoXAUIIOConfig__XAUI1_Hiterm",
      AD_CfgRegCoXAUIIOConfig, 13, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__XAUI1_Ref50,
      "CfgRegCoXAUIIOConfig__XAUI1_Ref50",
      AD_CfgRegCoXAUIIOConfig, 12, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__CPUXAUI1_Termr1_FromTrimSel,
      "CfgRegCoXAUIIOConfig__CPUXAUI1_Termr1_FromTrimSel",
      AD_CfgRegCoXAUIIOConfig, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__CPUXAUI1_Termr1_FromTrimIn,
      "CfgRegCoXAUIIOConfig__CPUXAUI1_Termr1_FromTrimIn",
      AD_CfgRegCoXAUIIOConfig, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__CPUXAUI1_Termr0_FromTrimSel,
      "CfgRegCoXAUIIOConfig__CPUXAUI1_Termr0_FromTrimSel",
      AD_CfgRegCoXAUIIOConfig, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__CPUXAUI1_Termr0_FromTrimIn,
      "CfgRegCoXAUIIOConfig__CPUXAUI1_Termr0_FromTrimIn",
      AD_CfgRegCoXAUIIOConfig, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__XAUI0_TXON,
      "CfgRegCoXAUIIOConfig__XAUI0_TXON",
      AD_CfgRegCoXAUIIOConfig, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__XAUI0_RefPd,
      "CfgRegCoXAUIIOConfig__XAUI0_RefPd",
      AD_CfgRegCoXAUIIOConfig, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__XAUI0_Hiterm,
      "CfgRegCoXAUIIOConfig__XAUI0_Hiterm",
      AD_CfgRegCoXAUIIOConfig, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__XAUI0_Ref50,
      "CfgRegCoXAUIIOConfig__XAUI0_Ref50",
      AD_CfgRegCoXAUIIOConfig, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__CPUXAUI0_Termr1_FromTrimSel,
      "CfgRegCoXAUIIOConfig__CPUXAUI0_Termr1_FromTrimSel",
      AD_CfgRegCoXAUIIOConfig, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__CPUXAUI0_Termr1_FromTrimIn,
      "CfgRegCoXAUIIOConfig__CPUXAUI0_Termr1_FromTrimIn",
      AD_CfgRegCoXAUIIOConfig, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__CPUXAUI0_Termr0_FromTrimSel,
      "CfgRegCoXAUIIOConfig__CPUXAUI0_Termr0_FromTrimSel",
      AD_CfgRegCoXAUIIOConfig, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXAUIIOConfig__CPUXAUI0_Termr0_FromTrimIn,
      "CfgRegCoXAUIIOConfig__CPUXAUI0_Termr0_FromTrimIn",
      AD_CfgRegCoXAUIIOConfig, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { StsRegCoXAUIIO,
      "StsRegCoXAUIIO",
      AD_StsRegCoXAUIIO, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCoXAUIInterrupt,
      "StsRegCoXAUIInterrupt",
      AD_StsRegCoXAUIInterrupt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCoXAUIInterruptMask,
      "StsRegCoXAUIInterruptMask",
      AD_StsRegCoXAUIInterruptMask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFIIOConfig,
      "CfgRegCoXFIIOConfig",
      AD_CfgRegCoXFIIOConfig, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFIIOConfig__XFI1_CLKOUTPowerDownN,
      "CfgRegCoXFIIOConfig__XFI1_CLKOUTPowerDownN",
      AD_CfgRegCoXFIIOConfig, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFIIOConfig__XFI0_CLKOUTPowerDownN,
      "CfgRegCoXFIIOConfig__XFI0_CLKOUTPowerDownN",
      AD_CfgRegCoXFIIOConfig, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFIIOConfig__XFI_REFCLK66PowerDownN,
      "CfgRegCoXFIIOConfig__XFI_REFCLK66PowerDownN",
      AD_CfgRegCoXFIIOConfig, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFIIOConfig__XFI1_POWER_DOWN,
      "CfgRegCoXFIIOConfig__XFI1_POWER_DOWN",
      AD_CfgRegCoXFIIOConfig, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFIIOConfig__XFI1_MOD_DESEL,
      "CfgRegCoXFIIOConfig__XFI1_MOD_DESEL",
      AD_CfgRegCoXFIIOConfig, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFIIOConfig__XFI1_TX_DIS,
      "CfgRegCoXFIIOConfig__XFI1_TX_DIS",
      AD_CfgRegCoXFIIOConfig, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFIIOConfig__XFI0_POWER_DOWN,
      "CfgRegCoXFIIOConfig__XFI0_POWER_DOWN",
      AD_CfgRegCoXFIIOConfig, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFIIOConfig__XFI0_MOD_DESEL,
      "CfgRegCoXFIIOConfig__XFI0_MOD_DESEL",
      AD_CfgRegCoXFIIOConfig, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoXFIIOConfig__XFI0_TX_DIS,
      "CfgRegCoXFIIOConfig__XFI0_TX_DIS",
      AD_CfgRegCoXFIIOConfig, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { StsRegCoXFIIO,
      "StsRegCoXFIIO",
      AD_StsRegCoXFIIO, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCoXFIInterrupt,
      "StsRegCoXFIInterrupt",
      AD_StsRegCoXFIInterrupt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCoXFIInterruptMask,
      "StsRegCoXFIInterruptMask",
      AD_StsRegCoXFIInterruptMask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCPLLConfig,
      "CfgRegCoFCPLLConfig",
      AD_CfgRegCoFCPLLConfig, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCPLLConfig__FC_PLL_LOCK_Bypass,
      "CfgRegCoFCPLLConfig__FC_PLL_LOCK_Bypass",
      AD_CfgRegCoFCPLLConfig, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCPLLConfig__FC_UpdateInterval,
      "CfgRegCoFCPLLConfig__FC_UpdateInterval",
      AD_CfgRegCoFCPLLConfig, 10, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCPLLConfig__FC_StabilizeInterval,
      "CfgRegCoFCPLLConfig__FC_StabilizeInterval",
      AD_CfgRegCoFCPLLConfig, 6, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCPLLConfig__FC_PLL_LockResetN,
      "CfgRegCoFCPLLConfig__FC_PLL_LockResetN",
      AD_CfgRegCoFCPLLConfig, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCPLLConfig__FC_PLL_Bypass,
      "CfgRegCoFCPLLConfig__FC_PLL_Bypass",
      AD_CfgRegCoFCPLLConfig, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCPLLConfig__FC_PLL_En,
      "CfgRegCoFCPLLConfig__FC_PLL_En",
      AD_CfgRegCoFCPLLConfig, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig,
      "CfgRegCoFCRAMIOConfig",
      AD_CfgRegCoFCRAMIOConfig, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC1_PowerDownN,
      "CfgRegCoFCRAMIOConfig__FC1_PowerDownN",
      AD_CfgRegCoFCRAMIOConfig, 29, 29, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC1_ImpSel45,
      "CfgRegCoFCRAMIOConfig__FC1_ImpSel45",
      AD_CfgRegCoFCRAMIOConfig, 28, 28, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC1_Mode18,
      "CfgRegCoFCRAMIOConfig__FC1_Mode18",
      AD_CfgRegCoFCRAMIOConfig, 27, 27, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC1_ForceEN,
      "CfgRegCoFCRAMIOConfig__FC1_ForceEN",
      AD_CfgRegCoFCRAMIOConfig, 26, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC1_ForceEP,
      "CfgRegCoFCRAMIOConfig__FC1_ForceEP",
      AD_CfgRegCoFCRAMIOConfig, 21, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC1_ForceENEP,
      "CfgRegCoFCRAMIOConfig__FC1_ForceENEP",
      AD_CfgRegCoFCRAMIOConfig, 16, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC1_BZCntlrResetN,
      "CfgRegCoFCRAMIOConfig__FC1_BZCntlrResetN",
      AD_CfgRegCoFCRAMIOConfig, 15, 15, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC0_PowerDownN,
      "CfgRegCoFCRAMIOConfig__FC0_PowerDownN",
      AD_CfgRegCoFCRAMIOConfig, 14, 14, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC0_ImpSel45,
      "CfgRegCoFCRAMIOConfig__FC0_ImpSel45",
      AD_CfgRegCoFCRAMIOConfig, 13, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC0_Mode18,
      "CfgRegCoFCRAMIOConfig__FC0_Mode18",
      AD_CfgRegCoFCRAMIOConfig, 12, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC0_ForceEN,
      "CfgRegCoFCRAMIOConfig__FC0_ForceEN",
      AD_CfgRegCoFCRAMIOConfig, 11, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC0_ForceEP,
      "CfgRegCoFCRAMIOConfig__FC0_ForceEP",
      AD_CfgRegCoFCRAMIOConfig, 6, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC0_ForceENEP,
      "CfgRegCoFCRAMIOConfig__FC0_ForceENEP",
      AD_CfgRegCoFCRAMIOConfig, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMIOConfig__FC0_BZCntlrResetN,
      "CfgRegCoFCRAMIOConfig__FC0_BZCntlrResetN",
      AD_CfgRegCoFCRAMIOConfig, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig,
      "CfgRegCoFCRAMHardMacroConfig",
      AD_CfgRegCoFCRAMHardMacroConfig, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC1_RESERVED,
      "CfgRegCoFCRAMHardMacroConfig__FC1_RESERVED",
      AD_CfgRegCoFCRAMHardMacroConfig, 31, 31, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC1_Clk2XDKDly,
      "CfgRegCoFCRAMHardMacroConfig__FC1_Clk2XDKDly",
      AD_CfgRegCoFCRAMHardMacroConfig, 30, 29, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC1_Clk2XCkDly,
      "CfgRegCoFCRAMHardMacroConfig__FC1_Clk2XCkDly",
      AD_CfgRegCoFCRAMHardMacroConfig, 28, 27, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC1_ForceNegDlyOffset,
      "CfgRegCoFCRAMHardMacroConfig__FC1_ForceNegDlyOffset",
      AD_CfgRegCoFCRAMHardMacroConfig, 26, 26, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC1_ForcePosDlyOffset,
      "CfgRegCoFCRAMHardMacroConfig__FC1_ForcePosDlyOffset",
      AD_CfgRegCoFCRAMHardMacroConfig, 25, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC1_ForceNomDly,
      "CfgRegCoFCRAMHardMacroConfig__FC1_ForceNomDly",
      AD_CfgRegCoFCRAMHardMacroConfig, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC1_ForceValue,
      "CfgRegCoFCRAMHardMacroConfig__FC1_ForceValue",
      AD_CfgRegCoFCRAMHardMacroConfig, 23, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC0_RESERVED,
      "CfgRegCoFCRAMHardMacroConfig__FC0_RESERVED",
      AD_CfgRegCoFCRAMHardMacroConfig, 15, 15, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC0_Clk2XDKDly,
      "CfgRegCoFCRAMHardMacroConfig__FC0_Clk2XDKDly",
      AD_CfgRegCoFCRAMHardMacroConfig, 14, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC0_Clk2XCkDly,
      "CfgRegCoFCRAMHardMacroConfig__FC0_Clk2XCkDly",
      AD_CfgRegCoFCRAMHardMacroConfig, 12, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC0_ForceNegDlyOffset,
      "CfgRegCoFCRAMHardMacroConfig__FC0_ForceNegDlyOffset",
      AD_CfgRegCoFCRAMHardMacroConfig, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC0_ForcePosDlyOffset,
      "CfgRegCoFCRAMHardMacroConfig__FC0_ForcePosDlyOffset",
      AD_CfgRegCoFCRAMHardMacroConfig, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC0_ForceNomDly,
      "CfgRegCoFCRAMHardMacroConfig__FC0_ForceNomDly",
      AD_CfgRegCoFCRAMHardMacroConfig, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoFCRAMHardMacroConfig__FC0_ForceValue,
      "CfgRegCoFCRAMHardMacroConfig__FC0_ForceValue",
      AD_CfgRegCoFCRAMHardMacroConfig, 7, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig,
      "CfgRegCoSPIIOConfig",
      AD_CfgRegCoSPIIOConfig, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI1_NotUsed,
      "CfgRegCoSPIIOConfig__SPI1_NotUsed",
      AD_CfgRegCoSPIIOConfig, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI1_Bias_VSw,
      "CfgRegCoSPIIOConfig__SPI1_Bias_VSw",
      AD_CfgRegCoSPIIOConfig, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI1_Bias_Term,
      "CfgRegCoSPIIOConfig__SPI1_Bias_Term",
      AD_CfgRegCoSPIIOConfig, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI1_Bias_TermEn,
      "CfgRegCoSPIIOConfig__SPI1_Bias_TermEn",
      AD_CfgRegCoSPIIOConfig, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI1_RxPowerDown,
      "CfgRegCoSPIIOConfig__SPI1_RxPowerDown",
      AD_CfgRegCoSPIIOConfig, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI1_TxPowerDown,
      "CfgRegCoSPIIOConfig__SPI1_TxPowerDown",
      AD_CfgRegCoSPIIOConfig, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI0_NotUsed,
      "CfgRegCoSPIIOConfig__SPI0_NotUsed",
      AD_CfgRegCoSPIIOConfig, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI0_Bias_VSw,
      "CfgRegCoSPIIOConfig__SPI0_Bias_VSw",
      AD_CfgRegCoSPIIOConfig, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPIO_Bias_Term,
      "CfgRegCoSPIIOConfig__SPIO_Bias_Term",
      AD_CfgRegCoSPIIOConfig, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI0_Bias_TermEn,
      "CfgRegCoSPIIOConfig__SPI0_Bias_TermEn",
      AD_CfgRegCoSPIIOConfig, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI0_RxPowerDown,
      "CfgRegCoSPIIOConfig__SPI0_RxPowerDown",
      AD_CfgRegCoSPIIOConfig, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoSPIIOConfig__SPI0_TxPowerDown,
      "CfgRegCoSPIIOConfig__SPI0_TxPowerDown",
      AD_CfgRegCoSPIIOConfig, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { StsRegCoFCPLLLock,
      "StsRegCoFCPLLLock",
      AD_StsRegCoFCPLLLock, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCo2wiremasterSetup,
      "CfgRegCo2wiremasterSetup",
      AD_CfgRegCo2wiremasterSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCo2wiremasterSetup__Cfg2wiremasterPortAddrP1,
      "CfgRegCo2wiremasterSetup__Cfg2wiremasterPortAddrP1",
      AD_CfgRegCo2wiremasterSetup, 13, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCo2wiremasterSetup__Cfg2wiremasterPortAddrP0,
      "CfgRegCo2wiremasterSetup__Cfg2wiremasterPortAddrP0",
      AD_CfgRegCo2wiremasterSetup, 6, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { StsRegCo2wiremaster,
      "StsRegCo2wiremaster",
      AD_StsRegCo2wiremaster, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCo2wiremasterInterrupt,
      "StsRegCo2wiremasterInterrupt",
      AD_StsRegCo2wiremasterInterrupt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegCo2wiremasterInterruptMask,
      "StsRegCo2wiremasterInterruptMask",
      AD_StsRegCo2wiremasterInterruptMask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc,
      "CfgRegCoMisc",
      AD_CfgRegCoMisc, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__Reserved2,
      "CfgRegCoMisc__Reserved2",
      AD_CfgRegCoMisc, 31, 19, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__VarXAUICoreEn1,
      "CfgRegCoMisc__VarXAUICoreEn1",
      AD_CfgRegCoMisc, 18, 18, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__VarXAUICoreEn0,
      "CfgRegCoMisc__VarXAUICoreEn0",
      AD_CfgRegCoMisc, 17, 17, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__VarCpuSlaveEn,
      "CfgRegCoMisc__VarCpuSlaveEn",
      AD_CfgRegCoMisc, 16, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__Reserved1,
      "CfgRegCoMisc__Reserved1",
      AD_CfgRegCoMisc, 15, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__FC1_RDS_ImpSel45,
      "CfgRegCoMisc__FC1_RDS_ImpSel45",
      AD_CfgRegCoMisc, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__FC1_DQ_ImpSel45,
      "CfgRegCoMisc__FC1_DQ_ImpSel45",
      AD_CfgRegCoMisc, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__FC1_CLK_ImpSel45,
      "CfgRegCoMisc__FC1_CLK_ImpSel45",
      AD_CfgRegCoMisc, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__FC1_A_ImpSel45,
      "CfgRegCoMisc__FC1_A_ImpSel45",
      AD_CfgRegCoMisc, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__FC0_RDS_ImpSel45,
      "CfgRegCoMisc__FC0_RDS_ImpSel45",
      AD_CfgRegCoMisc, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__FC0_DQ_ImpSel45,
      "CfgRegCoMisc__FC0_DQ_ImpSel45",
      AD_CfgRegCoMisc, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__FC0_CLK_ImpSel45,
      "CfgRegCoMisc__FC0_CLK_ImpSel45",
      AD_CfgRegCoMisc, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegCoMisc__FC0_A_ImpSel45,
      "CfgRegCoMisc__FC0_A_ImpSel45",
      AD_CfgRegCoMisc, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegMDIOCommand,
      "VarRegMDIOCommand",
      AD_VarRegMDIOCommand, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { VarRegMDIOCommand__MDIOAddrData,
      "VarRegMDIOCommand__MDIOAddrData",
      AD_VarRegMDIOCommand, 29, 14, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegMDIOCommand__MDIODeviceAddr,
      "VarRegMDIOCommand__MDIODeviceAddr",
      AD_VarRegMDIOCommand, 13, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegMDIOCommand__MDIOPortAddr,
      "VarRegMDIOCommand__MDIOPortAddr",
      AD_VarRegMDIOCommand, 8, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegMDIOCommand__MDIOOperation,
      "VarRegMDIOCommand__MDIOOperation",
      AD_VarRegMDIOCommand, 3, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { VarRegMDIOCommand__MDIOStartOfFrm,
      "VarRegMDIOCommand__MDIOStartOfFrm",
      AD_VarRegMDIOCommand, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegMDIOMode,
      "CfgRegMDIOMode",
      AD_CfgRegMDIOMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegMDIOMode__SupressPreamble,
      "CfgRegMDIOMode__SupressPreamble",
      AD_CfgRegMDIOMode, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegMDIOMode__Preamble,
      "CfgRegMDIOMode__Preamble",
      AD_CfgRegMDIOMode, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegMDIOAutoScan,
      "CfgRegMDIOAutoScan",
      AD_CfgRegMDIOAutoScan, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegMDIOAutoScan__En1,
      "CfgRegMDIOAutoScan__En1",
      AD_CfgRegMDIOAutoScan, 21, 21, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegMDIOAutoScan__En0,
      "CfgRegMDIOAutoScan__En0",
      AD_CfgRegMDIOAutoScan, 20, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegMDIOAutoScan__PhyReg1,
      "CfgRegMDIOAutoScan__PhyReg1",
      AD_CfgRegMDIOAutoScan, 19, 15, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegMDIOAutoScan__PhyReg0,
      "CfgRegMDIOAutoScan__PhyReg0",
      AD_CfgRegMDIOAutoScan, 14, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegMDIOAutoScan__Phy1,
      "CfgRegMDIOAutoScan__Phy1",
      AD_CfgRegMDIOAutoScan, 9, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegMDIOAutoScan__Phy0,
      "CfgRegMDIOAutoScan__Phy0",
      AD_CfgRegMDIOAutoScan, 4, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { StsRegMDIOAutoScanReg0,
      "StsRegMDIOAutoScanReg0",
      AD_StsRegMDIOAutoScanReg0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegMDIOAutoScanReg1,
      "StsRegMDIOAutoScanReg1",
      AD_StsRegMDIOAutoScanReg1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegMDIOData,
      "StsRegMDIOData",
      AD_StsRegMDIOData, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegMDIOInterrupt,
      "StsRegMDIOInterrupt",
      AD_StsRegMDIOInterrupt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegMDIOInterruptMask,
      "StsRegMDIOInterruptMask",
      AD_StsRegMDIOInterruptMask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegMDIOBusy,
      "StsRegMDIOBusy",
      AD_StsRegMDIOBusy, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegMDIODiag,
      "StsRegMDIODiag",
      AD_StsRegMDIODiag, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgShadowEventTrigSource,
      "CfgShadowEventTrigSource",
      AD_CfgShadowEventTrigSource, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgCpuShadowEvent,
      "CfgCpuShadowEvent",
      AD_CfgCpuShadowEvent, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgShadowTimerMsb,
      "CfgShadowTimerMsb",
      AD_CfgShadowTimerMsb, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgShadowTimerLsb,
      "CfgShadowTimerLsb",
      AD_CfgShadowTimerLsb, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowEventTrigIntr,
      "StsShadowEventTrigIntr",
      AD_StsShadowEventTrigIntr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowEventTrigIntrMask,
      "StsShadowEventTrigIntrMask",
      AD_StsShadowEventTrigIntrMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegToalFrmsReceived,
      "StsShadowRegToalFrmsReceived",
      AD_StsShadowRegToalFrmsReceived, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegToalFrmsTransmitted,
      "StsShadowRegToalFrmsTransmitted",
      AD_StsShadowRegToalFrmsTransmitted, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegGoodFrmsReceived,
      "StsShadowRegGoodFrmsReceived",
      AD_StsShadowRegGoodFrmsReceived, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegGoodFrmsTransmitted,
      "StsShadowRegGoodFrmsTransmitted",
      AD_StsShadowRegGoodFrmsTransmitted, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegCrcErrsReceived,
      "StsShadowRegCrcErrsReceived",
      AD_StsShadowRegCrcErrsReceived, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegCrcErrsTransmitted,
      "StsShadowRegCrcErrsTransmitted",
      AD_StsShadowRegCrcErrsTransmitted, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegFrmsDropedByRed,
      "StsShadowRegFrmsDropedByRed",
      AD_StsShadowRegFrmsDropedByRed, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegUCastFrmsDroped,
      "StsShadowRegUCastFrmsDroped",
      AD_StsShadowRegUCastFrmsDroped, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegMCastFrmsDroped,
      "StsShadowRegMCastFrmsDroped",
      AD_StsShadowRegMCastFrmsDroped, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegBCastFrmsDroped,
      "StsShadowRegBCastFrmsDroped",
      AD_StsShadowRegBCastFrmsDroped, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegMPLSFrmsDroped,
      "StsShadowRegMPLSFrmsDroped",
      AD_StsShadowRegMPLSFrmsDroped, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegEthTypeMatchFrmsDroped,
      "StsShadowRegEthTypeMatchFrmsDroped",
      AD_StsShadowRegEthTypeMatchFrmsDroped, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegMacFilterFrmsDroped,
      "StsShadowRegMacFilterFrmsDroped",
      AD_StsShadowRegMacFilterFrmsDroped, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegIngFilterFrmsDroped,
      "StsShadowRegIngFilterFrmsDroped",
      AD_StsShadowRegIngFilterFrmsDroped, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegDeqExcessLatencyFrmsDroped,
      "StsShadowRegDeqExcessLatencyFrmsDroped",
      AD_StsShadowRegDeqExcessLatencyFrmsDroped, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsShadowRegEnqMemFullFrmsDroped,
      "StsShadowRegEnqMemFullFrmsDroped",
      AD_StsShadowRegEnqMemFullFrmsDroped, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables,
      "CfgStatusPEnables",
      AD_CfgStatusPEnables, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables__CfgModNrStsEnP,
      "CfgStatusPEnables__CfgModNrStsEnP",
      AD_CfgStatusPEnables, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables__CfgIntrStsEnP,
      "CfgStatusPEnables__CfgIntrStsEnP",
      AD_CfgStatusPEnables, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables__CfgModAbsStsEnP,
      "CfgStatusPEnables__CfgModAbsStsEnP",
      AD_CfgStatusPEnables, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables__CfgRxLosStsEnP,
      "CfgStatusPEnables__CfgRxLosStsEnP",
      AD_CfgStatusPEnables, 6, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables__CfgLasiStsEnP,
      "CfgStatusPEnables__CfgLasiStsEnP",
      AD_CfgStatusPEnables, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables__CfgModDetectStsEnP,
      "CfgStatusPEnables__CfgModDetectStsEnP",
      AD_CfgStatusPEnables, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables__CfgEthLocalFaultIndStsEnP,
      "CfgStatusPEnables__CfgEthLocalFaultIndStsEnP",
      AD_CfgStatusPEnables, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables__CfgEthRemoteFaultIndStsEnP,
      "CfgStatusPEnables__CfgEthRemoteFaultIndStsEnP",
      AD_CfgStatusPEnables, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables__CfgRecovClkOutOfRangeStsEnP,
      "CfgStatusPEnables__CfgRecovClkOutOfRangeStsEnP",
      AD_CfgStatusPEnables, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusPEnables__CfgBadInSigStsEnP,
      "CfgStatusPEnables__CfgBadInSigStsEnP",
      AD_CfgStatusPEnables, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables,
      "CfgStatusNEnables",
      AD_CfgStatusNEnables, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables__CfgModNrStsEnN,
      "CfgStatusNEnables__CfgModNrStsEnN",
      AD_CfgStatusNEnables, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables__CfgIntrStsEnN,
      "CfgStatusNEnables__CfgIntrStsEnN",
      AD_CfgStatusNEnables, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables__CfgModAbsStsEnN,
      "CfgStatusNEnables__CfgModAbsStsEnN",
      AD_CfgStatusNEnables, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables__CfgRxLosStsEnN,
      "CfgStatusNEnables__CfgRxLosStsEnN",
      AD_CfgStatusNEnables, 6, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables__CfgLasiStsEnN,
      "CfgStatusNEnables__CfgLasiStsEnN",
      AD_CfgStatusNEnables, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables__CfgModDetectStsEnN,
      "CfgStatusNEnables__CfgModDetectStsEnN",
      AD_CfgStatusNEnables, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables__CfgEthLocalFaultIndStsEnN,
      "CfgStatusNEnables__CfgEthLocalFaultIndStsEnN",
      AD_CfgStatusNEnables, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables__CfgEthRemoteFaultIndStsEnN,
      "CfgStatusNEnables__CfgEthRemoteFaultIndStsEnN",
      AD_CfgStatusNEnables, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables__CfgRecovClkOutOfRangeStsEnN,
      "CfgStatusNEnables__CfgRecovClkOutOfRangeStsEnN",
      AD_CfgStatusNEnables, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusNEnables__CfgBadInSigStsEnN,
      "CfgStatusNEnables__CfgBadInSigStsEnN",
      AD_CfgStatusNEnables, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusSwOverRide,
      "CfgStatusSwOverRide",
      AD_CfgStatusSwOverRide, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusSwOverRide__CfgStatusSwOverRideEn,
      "CfgStatusSwOverRide__CfgStatusSwOverRideEn",
      AD_CfgStatusSwOverRide, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusSwOverRide__CfgStatusSwDrvrOverRideP,
      "CfgStatusSwOverRide__CfgStatusSwDrvrOverRideP",
      AD_CfgStatusSwOverRide, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgStatusSwOverRide__CfgStatusSwDrvrOverRideN,
      "CfgStatusSwOverRide__CfgStatusSwDrvrOverRideN",
      AD_CfgStatusSwOverRide, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgGlitchCatchPeriod,
      "CfgGlitchCatchPeriod",
      AD_CfgGlitchCatchPeriod, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLedOnPeriod,
      "CfgLedOnPeriod",
      AD_CfgLedOnPeriod, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLedOffPeriod,
      "CfgLedOffPeriod",
      AD_CfgLedOffPeriod, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables,
      "CfgEventPEnables",
      AD_CfgEventPEnables, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables__CfgEventGoodFrmsInEnP,
      "CfgEventPEnables__CfgEventGoodFrmsInEnP",
      AD_CfgEventPEnables, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables__CfgEventEgrGoodFrmsInEnP,
      "CfgEventPEnables__CfgEventEgrGoodFrmsInEnP",
      AD_CfgEventPEnables, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables__CfgEventDropedBcFrmsInEnP,
      "CfgEventPEnables__CfgEventDropedBcFrmsInEnP",
      AD_CfgEventPEnables, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables__CfgEventDropedMcFrmsInEnP,
      "CfgEventPEnables__CfgEventDropedMcFrmsInEnP",
      AD_CfgEventPEnables, 6, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables__CfgEventFrmsDiscIngrsFiltersInEnP,
      "CfgEventPEnables__CfgEventFrmsDiscIngrsFiltersInEnP",
      AD_CfgEventPEnables, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables__CfgEventFrmsDiscTimeStmpFiltersInEnP,
      "CfgEventPEnables__CfgEventFrmsDiscTimeStmpFiltersInEnP",
      AD_CfgEventPEnables, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables__CfgEventFrmsDiscWredInEnP,
      "CfgEventPEnables__CfgEventFrmsDiscWredInEnP",
      AD_CfgEventPEnables, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables__CfgEventSwEnP,
      "CfgEventPEnables__CfgEventSwEnP",
      AD_CfgEventPEnables, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables__CfgEventFrmsDropedDueToSpiErrsInEnP,
      "CfgEventPEnables__CfgEventFrmsDropedDueToSpiErrsInEnP",
      AD_CfgEventPEnables, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventPEnables__CfgEventFrmsDropedDueToBufOverFlowInEnP,
      "CfgEventPEnables__CfgEventFrmsDropedDueToBufOverFlowInEnP",
      AD_CfgEventPEnables, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables,
      "CfgEventNEnables",
      AD_CfgEventNEnables, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables__CfgEventGoodFrmsInEnN,
      "CfgEventNEnables__CfgEventGoodFrmsInEnN",
      AD_CfgEventNEnables, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables__CfgEventEgrGoodFrmsInEnN,
      "CfgEventNEnables__CfgEventEgrGoodFrmsInEnN",
      AD_CfgEventNEnables, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables__CfgEventDropedBcFrmsInEnN,
      "CfgEventNEnables__CfgEventDropedBcFrmsInEnN",
      AD_CfgEventNEnables, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables__CfgEventDropedMcFrmsInEnN,
      "CfgEventNEnables__CfgEventDropedMcFrmsInEnN",
      AD_CfgEventNEnables, 6, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables__CfgEventFrmsDiscIngrsFiltersInEnN,
      "CfgEventNEnables__CfgEventFrmsDiscIngrsFiltersInEnN",
      AD_CfgEventNEnables, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables__CfgEventFrmsDiscTimeStmpFiltersInEnN,
      "CfgEventNEnables__CfgEventFrmsDiscTimeStmpFiltersInEnN",
      AD_CfgEventNEnables, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables__CfgEventFrmsDiscWredInEnN,
      "CfgEventNEnables__CfgEventFrmsDiscWredInEnN",
      AD_CfgEventNEnables, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables__CfgEventSwEnN,
      "CfgEventNEnables__CfgEventSwEnN",
      AD_CfgEventNEnables, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables__CfgEventFrmsDropedDueToSpiErrsInEnN,
      "CfgEventNEnables__CfgEventFrmsDropedDueToSpiErrsInEnN",
      AD_CfgEventNEnables, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventNEnables__CfgEventFrmsDropedDueToBufOverFlowInEnN,
      "CfgEventNEnables__CfgEventFrmsDropedDueToBufOverFlowInEnN",
      AD_CfgEventNEnables, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWinkCtrlOnTimer,
      "CfgWinkCtrlOnTimer",
      AD_CfgWinkCtrlOnTimer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWinkCtrlOffTimer,
      "CfgWinkCtrlOffTimer",
      AD_CfgWinkCtrlOffTimer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgExcessChkMsbTimer,
      "CfgExcessChkMsbTimer",
      AD_CfgExcessChkMsbTimer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgExcessChkLsbTimer,
      "CfgExcessChkLsbTimer",
      AD_CfgExcessChkLsbTimer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventSwOverRide,
      "CfgEventSwOverRide",
      AD_CfgEventSwOverRide, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventSwOverRide__CfgEventSwOverRideEn,
      "CfgEventSwOverRide__CfgEventSwOverRideEn",
      AD_CfgEventSwOverRide, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventSwOverRide__CfgEventSwDrvrOverRideP,
      "CfgEventSwOverRide__CfgEventSwDrvrOverRideP",
      AD_CfgEventSwOverRide, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventSwOverRide__CfgEventSwDrvrOverRideN,
      "CfgEventSwOverRide__CfgEventSwDrvrOverRideN",
      AD_CfgEventSwOverRide, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventOperation,
      "CfgEventOperation",
      AD_CfgEventOperation, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventOperation__CfgWinkCoordEn,
      "CfgEventOperation__CfgWinkCoordEn",
      AD_CfgEventOperation, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventOperation__CfgExcessChkEn,
      "CfgEventOperation__CfgExcessChkEn",
      AD_CfgEventOperation, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgEventSw,
      "CfgEventSw",
      AD_CfgEventSw, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgOnPolarityForStatusLeds,
      "CfgOnPolarityForStatusLeds",
      AD_CfgOnPolarityForStatusLeds, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgOnPolarityForStatusLeds__CfgOnPolarityForStatusPLedIs1,
      "CfgOnPolarityForStatusLeds__CfgOnPolarityForStatusPLedIs1",
      AD_CfgOnPolarityForStatusLeds, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgOnPolarityForStatusLeds__CfgOnPolarityForStatusNLedIs1,
      "CfgOnPolarityForStatusLeds__CfgOnPolarityForStatusNLedIs1",
      AD_CfgOnPolarityForStatusLeds, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgOnPolarityForEventLeds,
      "CfgOnPolarityForEventLeds",
      AD_CfgOnPolarityForEventLeds, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgOnPolarityForEventLeds__CfgOnPolarityForEventPLedIs1,
      "CfgOnPolarityForEventLeds__CfgOnPolarityForEventPLedIs1",
      AD_CfgOnPolarityForEventLeds, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgOnPolarityForEventLeds__CfgOnPolarityForEventNLedIs1,
      "CfgOnPolarityForEventLeds__CfgOnPolarityForEventNLedIs1",
      AD_CfgOnPolarityForEventLeds, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes,
      "CfgRegRxMACModes",
      AD_CfgRegRxMACModes, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxVLANPauseFrmEn,
      "CfgRegRxMACModes__RxVLANPauseFrmEn",
      AD_CfgRegRxMACModes, 23, 23, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxPauseUcastAddrEn,
      "CfgRegRxMACModes__RxPauseUcastAddrEn",
      AD_CfgRegRxMACModes, 22, 22, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxRSNoPrmbleReplace,
      "CfgRegRxMACModes__RxRSNoPrmbleReplace",
      AD_CfgRegRxMACModes, 21, 21, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxConsolidateError,
      "CfgRegRxMACModes__RxConsolidateError",
      AD_CfgRegRxMACModes, 20, 20, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxTransparentMode,
      "CfgRegRxMACModes__RxTransparentMode",
      AD_CfgRegRxMACModes, 19, 19, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__Reserved_0,
      "CfgRegRxMACModes__Reserved_0",
      AD_CfgRegRxMACModes, 18, 18, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxSAStripEn,
      "CfgRegRxMACModes__RxSAStripEn",
      AD_CfgRegRxMACModes, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxDAStripEn,
      "CfgRegRxMACModes__RxDAStripEn",
      AD_CfgRegRxMACModes, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__Reserved_1,
      "CfgRegRxMACModes__Reserved_1",
      AD_CfgRegRxMACModes, 15, 15, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxSendPauseMode,
      "CfgRegRxMACModes__RxSendPauseMode",
      AD_CfgRegRxMACModes, 14, 13, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxBCASTMode,
      "CfgRegRxMACModes__RxBCASTMode",
      AD_CfgRegRxMACModes, 12, 12, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxMCASTMode,
      "CfgRegRxMACModes__RxMCASTMode",
      AD_CfgRegRxMACModes, 11, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxCRCMode,
      "CfgRegRxMACModes__RxCRCMode",
      AD_CfgRegRxMACModes, 9, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxVLANStripEn,
      "CfgRegRxMACModes__RxVLANStripEn",
      AD_CfgRegRxMACModes, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxInsVLANTagEn,
      "CfgRegRxMACModes__RxInsVLANTagEn",
      AD_CfgRegRxMACModes, 6, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxVLANMode,
      "CfgRegRxMACModes__RxVLANMode",
      AD_CfgRegRxMACModes, 5, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxSAFilterEn,
      "CfgRegRxMACModes__RxSAFilterEn",
      AD_CfgRegRxMACModes, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxPromiscousEn,
      "CfgRegRxMACModes__RxPromiscousEn",
      AD_CfgRegRxMACModes, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxOverSizeFEn,
      "CfgRegRxMACModes__RxOverSizeFEn",
      AD_CfgRegRxMACModes, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMACModes__RxJumboFrameEn,
      "CfgRegRxMACModes__RxJumboFrameEn",
      AD_CfgRegRxMACModes, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMaxFSize,
      "CfgRegRxMaxFSize",
      AD_CfgRegRxMaxFSize, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxDAValLSB,
      "CfgRegRxDAValLSB",
      AD_CfgRegRxDAValLSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxDAValMSB,
      "CfgRegRxDAValMSB",
      AD_CfgRegRxDAValMSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxSAValLSB,
      "CfgRegRxSAValLSB",
      AD_CfgRegRxSAValLSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxSAValMSB,
      "CfgRegRxSAValMSB",
      AD_CfgRegRxSAValMSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxCPUValLSB,
      "CfgRegRxCPUValLSB",
      AD_CfgRegRxCPUValLSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxCPUValMSB,
      "CfgRegRxCPUValMSB",
      AD_CfgRegRxCPUValMSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMCASTPassFilterLSB,
      "CfgRegRxMCASTPassFilterLSB",
      AD_CfgRegRxMCASTPassFilterLSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxMCASTPassFilterMSB,
      "CfgRegRxMCASTPassFilterMSB",
      AD_CfgRegRxMCASTPassFilterMSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxVLANTagValue,
      "CfgRegRxVLANTagValue",
      AD_CfgRegRxVLANTagValue, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxVLANTagRcvd,
      "StsRegRxVLANTagRcvd",
      AD_StsRegRxVLANTagRcvd, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxPauseTime,
      "StsRegRxPauseTime",
      AD_StsRegRxPauseTime, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegLsbRxOctetsRcvdOK,
      "StsRegLsbRxOctetsRcvdOK",
      AD_StsRegLsbRxOctetsRcvdOK, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegMsbRxOctetsRcvdOK,
      "StsRegMsbRxOctetsRcvdOK",
      AD_StsRegMsbRxOctetsRcvdOK, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegLsbRxNumOfBadOctets,
      "StsRegLsbRxNumOfBadOctets",
      AD_StsRegLsbRxNumOfBadOctets, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegMsbRxNumOfBadOctets,
      "StsRegMsbRxNumOfBadOctets",
      AD_StsRegMsbRxNumOfBadOctets, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxNumOfBadFrms,
      "StsRegRxNumOfBadFrms",
      AD_StsRegRxNumOfBadFrms, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxFRcvdOK,
      "StsRegRxFRcvdOK",
      AD_StsRegRxFRcvdOK, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxNumOfCRCErrors,
      "StsRegRxNumOfCRCErrors",
      AD_StsRegRxNumOfCRCErrors, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxNumOfBcastFrms,
      "StsRegRxNumOfBcastFrms",
      AD_StsRegRxNumOfBcastFrms, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxNumOfMcastFrms,
      "StsRegRxNumOfMcastFrms",
      AD_StsRegRxNumOfMcastFrms, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxFrmsOf64Octets,
      "StsRegRxFrmsOf64Octets",
      AD_StsRegRxFrmsOf64Octets, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxFrmsOf65to127Octets,
      "StsRegRxFrmsOf65to127Octets",
      AD_StsRegRxFrmsOf65to127Octets, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxFrmsOf128to255Octets,
      "StsRegRxFrmsOf128to255Octets",
      AD_StsRegRxFrmsOf128to255Octets, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxFrmsOf256to511Octets,
      "StsRegRxFrmsOf256to511Octets",
      AD_StsRegRxFrmsOf256to511Octets, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxFrmsOf512to1023Octets,
      "StsRegRxFrmsOf512to1023Octets",
      AD_StsRegRxFrmsOf512to1023Octets, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxFrmsOf1024to1518Octets,
      "StsRegRxFrmsOf1024to1518Octets",
      AD_StsRegRxFrmsOf1024to1518Octets, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxJumboFrms,
      "StsRegRxJumboFrms",
      AD_StsRegRxJumboFrms, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxOversizeFrms,
      "StsRegRxOversizeFrms",
      AD_StsRegRxOversizeFrms, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxUndersizeFrms,
      "StsRegRxUndersizeFrms",
      AD_StsRegRxUndersizeFrms, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxNumOfFragments,
      "StsRegRxNumOfFragments",
      AD_StsRegRxNumOfFragments, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxNumOfJabbers,
      "StsRegRxNumOfJabbers",
      AD_StsRegRxNumOfJabbers, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxNumOfTooLongJabbers,
      "StsRegRxNumOfTooLongJabbers",
      AD_StsRegRxNumOfTooLongJabbers, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxOutOfRangeLenField,
      "StsRegRxOutOfRangeLenField",
      AD_StsRegRxOutOfRangeLenField, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxFTooLongErrors,
      "StsRegRxFTooLongErrors",
      AD_StsRegRxFTooLongErrors, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxMACCtrlFRcvd,
      "StsRegRxMACCtrlFRcvd",
      AD_StsRegRxMACCtrlFRcvd, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxUnsuppOpcodeRcvd,
      "StsRegRxUnsuppOpcodeRcvd",
      AD_StsRegRxUnsuppOpcodeRcvd, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxGoodVLANFRcvd,
      "StsRegRxGoodVLANFRcvd",
      AD_StsRegRxGoodVLANFRcvd, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxBadSAFRcvd,
      "StsRegRxBadSAFRcvd",
      AD_StsRegRxBadSAFRcvd, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxDataError,
      "StsRegRxDataError",
      AD_StsRegRxDataError, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxMcastDrop,
      "StsRegRxMcastDrop",
      AD_StsRegRxMcastDrop, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxBcastDrop,
      "StsRegRxBcastDrop",
      AD_StsRegRxBcastDrop, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxFilDrop,
      "StsRegRxFilDrop",
      AD_StsRegRxFilDrop, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxMACInterrupt,
      "StsRegRxMACInterrupt",
      AD_StsRegRxMACInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxMACInterruptMask,
      "StsRegRxMACInterruptMask",
      AD_StsRegRxMACInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxMACDiag,
      "StsRegRxMACDiag",
      AD_StsRegRxMACDiag, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxIPG5,
      "StsRegRxIPG5",
      AD_StsRegRxIPG5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxIPG6,
      "StsRegRxIPG6",
      AD_StsRegRxIPG6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxIPG7,
      "StsRegRxIPG7",
      AD_StsRegRxIPG7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxIPG8,
      "StsRegRxIPG8",
      AD_StsRegRxIPG8, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxIPG9,
      "StsRegRxIPG9",
      AD_StsRegRxIPG9, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxIPG10,
      "StsRegRxIPG10",
      AD_StsRegRxIPG10, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxIPG11,
      "StsRegRxIPG11",
      AD_StsRegRxIPG11, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxPauseMaxFSize,
      "CfgRegRxPauseMaxFSize",
      AD_CfgRegRxPauseMaxFSize, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxPauseMinFSize,
      "CfgRegRxPauseMinFSize",
      AD_CfgRegRxPauseMinFSize, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMcastWindowSize,
      "CfgMcastWindowSize",
      AD_CfgMcastWindowSize, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBcastWindowSize,
      "CfgBcastWindowSize",
      AD_CfgBcastWindowSize, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMcastLimitCount,
      "CfgMcastLimitCount",
      AD_CfgMcastLimitCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBcastLimitCount,
      "CfgBcastLimitCount",
      AD_CfgBcastLimitCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMacAddrLsb0,
      "CfgLimitMacAddrLsb0",
      AD_CfgLimitMacAddrLsb0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMacAddrMsb0,
      "CfgLimitMacAddrMsb0",
      AD_CfgLimitMacAddrMsb0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMacAddrLsb1,
      "CfgLimitMacAddrLsb1",
      AD_CfgLimitMacAddrLsb1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMacAddrMsb1,
      "CfgLimitMacAddrMsb1",
      AD_CfgLimitMacAddrMsb1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMacAddrLsb2,
      "CfgLimitMacAddrLsb2",
      AD_CfgLimitMacAddrLsb2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMacAddrMsb2,
      "CfgLimitMacAddrMsb2",
      AD_CfgLimitMacAddrMsb2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMacAddrLsb3,
      "CfgLimitMacAddrLsb3",
      AD_CfgLimitMacAddrLsb3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMacAddrMsb3,
      "CfgLimitMacAddrMsb3",
      AD_CfgLimitMacAddrMsb3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgCtrlMacAddrLsb0,
      "CfgCtrlMacAddrLsb0",
      AD_CfgCtrlMacAddrLsb0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgCtrlMacAddrMsb0,
      "CfgCtrlMacAddrMsb0",
      AD_CfgCtrlMacAddrMsb0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgCtrlMacAddrLsb1,
      "CfgCtrlMacAddrLsb1",
      AD_CfgCtrlMacAddrLsb1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgCtrlMacAddrMsb1,
      "CfgCtrlMacAddrMsb1",
      AD_CfgCtrlMacAddrMsb1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMaskMacAddrLsb0,
      "CfgLimitMaskMacAddrLsb0",
      AD_CfgLimitMaskMacAddrLsb0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMaskMacAddrMsb0,
      "CfgLimitMaskMacAddrMsb0",
      AD_CfgLimitMaskMacAddrMsb0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMaskMacAddrLsb1,
      "CfgLimitMaskMacAddrLsb1",
      AD_CfgLimitMaskMacAddrLsb1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMaskMacAddrMsb1,
      "CfgLimitMaskMacAddrMsb1",
      AD_CfgLimitMaskMacAddrMsb1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMaskMacAddrLsb2,
      "CfgLimitMaskMacAddrLsb2",
      AD_CfgLimitMaskMacAddrLsb2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMaskMacAddrMsb2,
      "CfgLimitMaskMacAddrMsb2",
      AD_CfgLimitMaskMacAddrMsb2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMaskMacAddrLsb3,
      "CfgLimitMaskMacAddrLsb3",
      AD_CfgLimitMaskMacAddrLsb3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLimitMaskMacAddrMsb3,
      "CfgLimitMaskMacAddrMsb3",
      AD_CfgLimitMaskMacAddrMsb3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMaskControlMacAddrLsb0,
      "CfgMaskControlMacAddrLsb0",
      AD_CfgMaskControlMacAddrLsb0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMaskControlMacAddrMsb0,
      "CfgMaskControlMacAddrMsb0",
      AD_CfgMaskControlMacAddrMsb0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMaskControlMacAddrLsb1,
      "CfgMaskControlMacAddrLsb1",
      AD_CfgMaskControlMacAddrLsb1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMaskControlMacAddrMsb1,
      "CfgMaskControlMacAddrMsb1",
      AD_CfgMaskControlMacAddrMsb1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMaxFrmSize,
      "CfgMaxFrmSize",
      AD_CfgMaxFrmSize, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMinFrmSize,
      "CfgMinFrmSize",
      AD_CfgMinFrmSize, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDefault,
      "CfgDefault",
      AD_CfgDefault, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDefault__HonorCFI,
      "CfgDefault__HonorCFI",
      AD_CfgDefault, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDefault__CoS,
      "CfgDefault__CoS",
      AD_CfgDefault, 3, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDefault__Discard,
      "CfgDefault__Discard",
      AD_CfgDefault, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters,
      "CfgFilters",
      AD_CfgFilters, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__MacControlAddrCheckEn,
      "CfgFilters__MacControlAddrCheckEn",
      AD_CfgFilters, 15, 15, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__VLANEtherTypeFilterEn,
      "CfgFilters__VLANEtherTypeFilterEn",
      AD_CfgFilters, 14, 14, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__TpLenFieldFilterEn,
      "CfgFilters__TpLenFieldFilterEn",
      AD_CfgFilters, 13, 13, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__LengthCheckEn,
      "CfgFilters__LengthCheckEn",
      AD_CfgFilters, 12, 12, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__BCastLimitEn,
      "CfgFilters__BCastLimitEn",
      AD_CfgFilters, 11, 11, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__MCastLimitEn,
      "CfgFilters__MCastLimitEn",
      AD_CfgFilters, 10, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__IPFilterEn,
      "CfgFilters__IPFilterEn",
      AD_CfgFilters, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__DSCPFilterEn,
      "CfgFilters__DSCPFilterEn",
      AD_CfgFilters, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__MACTypeLenFilterEn,
      "CfgFilters__MACTypeLenFilterEn",
      AD_CfgFilters, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__MACHashFilterEn,
      "CfgFilters__MACHashFilterEn",
      AD_CfgFilters, 6, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__MACDAFilterEn,
      "CfgFilters__MACDAFilterEn",
      AD_CfgFilters, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__InnerVLANEn,
      "CfgFilters__InnerVLANEn",
      AD_CfgFilters, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__OuterVLANEn,
      "CfgFilters__OuterVLANEn",
      AD_CfgFilters, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__SVLANEn,
      "CfgFilters__SVLANEn",
      AD_CfgFilters, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__MPLS3032FilterEn,
      "CfgFilters__MPLS3032FilterEn",
      AD_CfgFilters, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgFilters__MPLSVPLSFilterEn,
      "CfgFilters__MPLSVPLSFilterEn",
      AD_CfgFilters, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl0,
      "CfgMPLSCtrl0",
      AD_CfgMPLSCtrl0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl0__Enable0,
      "CfgMPLSCtrl0__Enable0",
      AD_CfgMPLSCtrl0, 25, 25, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl0__Discard0,
      "CfgMPLSCtrl0__Discard0",
      AD_CfgMPLSCtrl0, 24, 24, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl0__EtherType0,
      "CfgMPLSCtrl0__EtherType0",
      AD_CfgMPLSCtrl0, 23, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl0__CoSType0,
      "CfgMPLSCtrl0__CoSType0",
      AD_CfgMPLSCtrl0, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl0__CValue0,
      "CfgMPLSCtrl0__CValue0",
      AD_CfgMPLSCtrl0, 5, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl0__TimeStampEn0,
      "CfgMPLSCtrl0__TimeStampEn0",
      AD_CfgMPLSCtrl0, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl0__TimeStampSel0,
      "CfgMPLSCtrl0__TimeStampSel0",
      AD_CfgMPLSCtrl0, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl1,
      "CfgMPLSCtrl1",
      AD_CfgMPLSCtrl1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl1__Enable1,
      "CfgMPLSCtrl1__Enable1",
      AD_CfgMPLSCtrl1, 25, 25, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl1__Discard1,
      "CfgMPLSCtrl1__Discard1",
      AD_CfgMPLSCtrl1, 24, 24, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl1__EtherType1,
      "CfgMPLSCtrl1__EtherType1",
      AD_CfgMPLSCtrl1, 23, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl1__CoSType1,
      "CfgMPLSCtrl1__CoSType1",
      AD_CfgMPLSCtrl1, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl1__CValue1,
      "CfgMPLSCtrl1__CValue1",
      AD_CfgMPLSCtrl1, 5, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl1__TimeStampEn1,
      "CfgMPLSCtrl1__TimeStampEn1",
      AD_CfgMPLSCtrl1, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl1__TimeStampSel1,
      "CfgMPLSCtrl1__TimeStampSel1",
      AD_CfgMPLSCtrl1, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl2,
      "CfgMPLSCtrl2",
      AD_CfgMPLSCtrl2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl2__Enable2,
      "CfgMPLSCtrl2__Enable2",
      AD_CfgMPLSCtrl2, 25, 25, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl2__Discard2,
      "CfgMPLSCtrl2__Discard2",
      AD_CfgMPLSCtrl2, 24, 24, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl2__EtherType2,
      "CfgMPLSCtrl2__EtherType2",
      AD_CfgMPLSCtrl2, 23, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl2__CoSType2,
      "CfgMPLSCtrl2__CoSType2",
      AD_CfgMPLSCtrl2, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl2__CValue2,
      "CfgMPLSCtrl2__CValue2",
      AD_CfgMPLSCtrl2, 5, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl2__TimeStampEn2,
      "CfgMPLSCtrl2__TimeStampEn2",
      AD_CfgMPLSCtrl2, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl2__TimeStampSel2,
      "CfgMPLSCtrl2__TimeStampSel2",
      AD_CfgMPLSCtrl2, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl3,
      "CfgMPLSCtrl3",
      AD_CfgMPLSCtrl3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl3__Enable3,
      "CfgMPLSCtrl3__Enable3",
      AD_CfgMPLSCtrl3, 25, 25, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl3__Discard3,
      "CfgMPLSCtrl3__Discard3",
      AD_CfgMPLSCtrl3, 24, 24, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl3__EtherType3,
      "CfgMPLSCtrl3__EtherType3",
      AD_CfgMPLSCtrl3, 23, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl3__CoSType3,
      "CfgMPLSCtrl3__CoSType3",
      AD_CfgMPLSCtrl3, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl3__CValue3,
      "CfgMPLSCtrl3__CValue3",
      AD_CfgMPLSCtrl3, 5, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl3__TimeStampEn3,
      "CfgMPLSCtrl3__TimeStampEn3",
      AD_CfgMPLSCtrl3, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrl3__TimeStampSel3,
      "CfgMPLSCtrl3__TimeStampSel3",
      AD_CfgMPLSCtrl3, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrlD,
      "CfgMPLSCtrlD",
      AD_CfgMPLSCtrlD, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrlD__EnableD,
      "CfgMPLSCtrlD__EnableD",
      AD_CfgMPLSCtrlD, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrlD__DiscardD,
      "CfgMPLSCtrlD__DiscardD",
      AD_CfgMPLSCtrlD, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrlD__CoSTypeD,
      "CfgMPLSCtrlD__CoSTypeD",
      AD_CfgMPLSCtrlD, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrlD__CValueD,
      "CfgMPLSCtrlD__CValueD",
      AD_CfgMPLSCtrlD, 5, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrlD__TimeStampEnD,
      "CfgMPLSCtrlD__TimeStampEnD",
      AD_CfgMPLSCtrlD, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSCtrlD__TimeStampSelD,
      "CfgMPLSCtrlD__TimeStampSelD",
      AD_CfgMPLSCtrlD, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMask0,
      "CfgMPLSLLSPMask0",
      AD_CfgMPLSLLSPMask0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMask1,
      "CfgMPLSLLSPMask1",
      AD_CfgMPLSLLSPMask1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMask2,
      "CfgMPLSLLSPMask2",
      AD_CfgMPLSLLSPMask2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMask3,
      "CfgMPLSLLSPMask3",
      AD_CfgMPLSLLSPMask3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMask4,
      "CfgMPLSLLSPMask4",
      AD_CfgMPLSLLSPMask4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMask5,
      "CfgMPLSLLSPMask5",
      AD_CfgMPLSLLSPMask5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMask6,
      "CfgMPLSLLSPMask6",
      AD_CfgMPLSLLSPMask6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMask7,
      "CfgMPLSLLSPMask7",
      AD_CfgMPLSLLSPMask7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMatch0,
      "CfgMPLSLLSPMatch0",
      AD_CfgMPLSLLSPMatch0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMatch1,
      "CfgMPLSLLSPMatch1",
      AD_CfgMPLSLLSPMatch1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMatch2,
      "CfgMPLSLLSPMatch2",
      AD_CfgMPLSLLSPMatch2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMatch3,
      "CfgMPLSLLSPMatch3",
      AD_CfgMPLSLLSPMatch3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMatch4,
      "CfgMPLSLLSPMatch4",
      AD_CfgMPLSLLSPMatch4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMatch5,
      "CfgMPLSLLSPMatch5",
      AD_CfgMPLSLLSPMatch5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMatch6,
      "CfgMPLSLLSPMatch6",
      AD_CfgMPLSLLSPMatch6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPMatch7,
      "CfgMPLSLLSPMatch7",
      AD_CfgMPLSLLSPMatch7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl0,
      "CfgMPLSLLSPCtrl0",
      AD_CfgMPLSLLSPCtrl0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl0__Discard0,
      "CfgMPLSLLSPCtrl0__Discard0",
      AD_CfgMPLSLLSPCtrl0, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl0__CoSType0,
      "CfgMPLSLLSPCtrl0__CoSType0",
      AD_CfgMPLSLLSPCtrl0, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl0__CValue0,
      "CfgMPLSLLSPCtrl0__CValue0",
      AD_CfgMPLSLLSPCtrl0, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl0__ProgBitIDB0,
      "CfgMPLSLLSPCtrl0__ProgBitIDB0",
      AD_CfgMPLSLLSPCtrl0, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl0__TimeStampEn0,
      "CfgMPLSLLSPCtrl0__TimeStampEn0",
      AD_CfgMPLSLLSPCtrl0, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl0__TimeStampSel0,
      "CfgMPLSLLSPCtrl0__TimeStampSel0",
      AD_CfgMPLSLLSPCtrl0, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl1,
      "CfgMPLSLLSPCtrl1",
      AD_CfgMPLSLLSPCtrl1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl1__Discard1,
      "CfgMPLSLLSPCtrl1__Discard1",
      AD_CfgMPLSLLSPCtrl1, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl1__CoSType1,
      "CfgMPLSLLSPCtrl1__CoSType1",
      AD_CfgMPLSLLSPCtrl1, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl1__CValue1,
      "CfgMPLSLLSPCtrl1__CValue1",
      AD_CfgMPLSLLSPCtrl1, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl1__ProgBitIDB1,
      "CfgMPLSLLSPCtrl1__ProgBitIDB1",
      AD_CfgMPLSLLSPCtrl1, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl1__TimeStampEn1,
      "CfgMPLSLLSPCtrl1__TimeStampEn1",
      AD_CfgMPLSLLSPCtrl1, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl1__TimeStampSel1,
      "CfgMPLSLLSPCtrl1__TimeStampSel1",
      AD_CfgMPLSLLSPCtrl1, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl2,
      "CfgMPLSLLSPCtrl2",
      AD_CfgMPLSLLSPCtrl2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl2__Discard2,
      "CfgMPLSLLSPCtrl2__Discard2",
      AD_CfgMPLSLLSPCtrl2, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl2__CoSType2,
      "CfgMPLSLLSPCtrl2__CoSType2",
      AD_CfgMPLSLLSPCtrl2, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl2__CValue2,
      "CfgMPLSLLSPCtrl2__CValue2",
      AD_CfgMPLSLLSPCtrl2, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl2__ProgBitIDB2,
      "CfgMPLSLLSPCtrl2__ProgBitIDB2",
      AD_CfgMPLSLLSPCtrl2, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl2__TimeStampEn2,
      "CfgMPLSLLSPCtrl2__TimeStampEn2",
      AD_CfgMPLSLLSPCtrl2, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl2__TimeStampSel2,
      "CfgMPLSLLSPCtrl2__TimeStampSel2",
      AD_CfgMPLSLLSPCtrl2, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl3,
      "CfgMPLSLLSPCtrl3",
      AD_CfgMPLSLLSPCtrl3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl3__Discard3,
      "CfgMPLSLLSPCtrl3__Discard3",
      AD_CfgMPLSLLSPCtrl3, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl3__CoSType3,
      "CfgMPLSLLSPCtrl3__CoSType3",
      AD_CfgMPLSLLSPCtrl3, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl3__CValue3,
      "CfgMPLSLLSPCtrl3__CValue3",
      AD_CfgMPLSLLSPCtrl3, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl3__ProgBitIDB3,
      "CfgMPLSLLSPCtrl3__ProgBitIDB3",
      AD_CfgMPLSLLSPCtrl3, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl3__TimeStampEn3,
      "CfgMPLSLLSPCtrl3__TimeStampEn3",
      AD_CfgMPLSLLSPCtrl3, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl3__TimeStampSel3,
      "CfgMPLSLLSPCtrl3__TimeStampSel3",
      AD_CfgMPLSLLSPCtrl3, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl4,
      "CfgMPLSLLSPCtrl4",
      AD_CfgMPLSLLSPCtrl4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl4__Discard4,
      "CfgMPLSLLSPCtrl4__Discard4",
      AD_CfgMPLSLLSPCtrl4, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl4__CoSType4,
      "CfgMPLSLLSPCtrl4__CoSType4",
      AD_CfgMPLSLLSPCtrl4, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl4__CValue4,
      "CfgMPLSLLSPCtrl4__CValue4",
      AD_CfgMPLSLLSPCtrl4, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl4__ProgBitIDB4,
      "CfgMPLSLLSPCtrl4__ProgBitIDB4",
      AD_CfgMPLSLLSPCtrl4, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl4__TimeStampEn4,
      "CfgMPLSLLSPCtrl4__TimeStampEn4",
      AD_CfgMPLSLLSPCtrl4, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl4__TimeStampSel4,
      "CfgMPLSLLSPCtrl4__TimeStampSel4",
      AD_CfgMPLSLLSPCtrl4, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl5,
      "CfgMPLSLLSPCtrl5",
      AD_CfgMPLSLLSPCtrl5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl5__Discard5,
      "CfgMPLSLLSPCtrl5__Discard5",
      AD_CfgMPLSLLSPCtrl5, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl5__CoSType5,
      "CfgMPLSLLSPCtrl5__CoSType5",
      AD_CfgMPLSLLSPCtrl5, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl5__CValue5,
      "CfgMPLSLLSPCtrl5__CValue5",
      AD_CfgMPLSLLSPCtrl5, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl5__ProgBitIDB5,
      "CfgMPLSLLSPCtrl5__ProgBitIDB5",
      AD_CfgMPLSLLSPCtrl5, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl5__TimeStampEn5,
      "CfgMPLSLLSPCtrl5__TimeStampEn5",
      AD_CfgMPLSLLSPCtrl5, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl5__TimeStampSel5,
      "CfgMPLSLLSPCtrl5__TimeStampSel5",
      AD_CfgMPLSLLSPCtrl5, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl6,
      "CfgMPLSLLSPCtrl6",
      AD_CfgMPLSLLSPCtrl6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl6__Discard6,
      "CfgMPLSLLSPCtrl6__Discard6",
      AD_CfgMPLSLLSPCtrl6, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl6__CoSType6,
      "CfgMPLSLLSPCtrl6__CoSType6",
      AD_CfgMPLSLLSPCtrl6, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl6__CValue6,
      "CfgMPLSLLSPCtrl6__CValue6",
      AD_CfgMPLSLLSPCtrl6, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl6__ProgBitIDB6,
      "CfgMPLSLLSPCtrl6__ProgBitIDB6",
      AD_CfgMPLSLLSPCtrl6, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl6__TimeStampEn6,
      "CfgMPLSLLSPCtrl6__TimeStampEn6",
      AD_CfgMPLSLLSPCtrl6, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl6__TimeStampSel6,
      "CfgMPLSLLSPCtrl6__TimeStampSel6",
      AD_CfgMPLSLLSPCtrl6, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl7,
      "CfgMPLSLLSPCtrl7",
      AD_CfgMPLSLLSPCtrl7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl7__Discard7,
      "CfgMPLSLLSPCtrl7__Discard7",
      AD_CfgMPLSLLSPCtrl7, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl7__CoSType7,
      "CfgMPLSLLSPCtrl7__CoSType7",
      AD_CfgMPLSLLSPCtrl7, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl7__CValue7,
      "CfgMPLSLLSPCtrl7__CValue7",
      AD_CfgMPLSLLSPCtrl7, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl7__ProgBitIDB7,
      "CfgMPLSLLSPCtrl7__ProgBitIDB7",
      AD_CfgMPLSLLSPCtrl7, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl7__TimeStampEn7,
      "CfgMPLSLLSPCtrl7__TimeStampEn7",
      AD_CfgMPLSLLSPCtrl7, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrl7__TimeStampSel7,
      "CfgMPLSLLSPCtrl7__TimeStampSel7",
      AD_CfgMPLSLLSPCtrl7, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrlD,
      "CfgMPLSLLSPCtrlD",
      AD_CfgMPLSLLSPCtrlD, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrlD__DiscardD,
      "CfgMPLSLLSPCtrlD__DiscardD",
      AD_CfgMPLSLLSPCtrlD, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrlD__CoSTypeD,
      "CfgMPLSLLSPCtrlD__CoSTypeD",
      AD_CfgMPLSLLSPCtrlD, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrlD__CValueD,
      "CfgMPLSLLSPCtrlD__CValueD",
      AD_CfgMPLSLLSPCtrlD, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrlD__ProgBitIDBD,
      "CfgMPLSLLSPCtrlD__ProgBitIDBD",
      AD_CfgMPLSLLSPCtrlD, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrlD__TimeStampEnD,
      "CfgMPLSLLSPCtrlD__TimeStampEnD",
      AD_CfgMPLSLLSPCtrlD, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMPLSLLSPCtrlD__TimeStampSelD,
      "CfgMPLSLLSPCtrlD__TimeStampSelD",
      AD_CfgMPLSLLSPCtrlD, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE0,
      "CfgVLANEtherTypeE0",
      AD_CfgVLANEtherTypeE0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE0__Enable0,
      "CfgVLANEtherTypeE0__Enable0",
      AD_CfgVLANEtherTypeE0, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE0__Discard0,
      "CfgVLANEtherTypeE0__Discard0",
      AD_CfgVLANEtherTypeE0, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE0__VLANEtherType0,
      "CfgVLANEtherTypeE0__VLANEtherType0",
      AD_CfgVLANEtherTypeE0, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE1,
      "CfgVLANEtherTypeE1",
      AD_CfgVLANEtherTypeE1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE1__Enable1,
      "CfgVLANEtherTypeE1__Enable1",
      AD_CfgVLANEtherTypeE1, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE1__Discard1,
      "CfgVLANEtherTypeE1__Discard1",
      AD_CfgVLANEtherTypeE1, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE1__VLANEtherType1,
      "CfgVLANEtherTypeE1__VLANEtherType1",
      AD_CfgVLANEtherTypeE1, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE2,
      "CfgVLANEtherTypeE2",
      AD_CfgVLANEtherTypeE2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE2__Enable2,
      "CfgVLANEtherTypeE2__Enable2",
      AD_CfgVLANEtherTypeE2, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE2__Discard2,
      "CfgVLANEtherTypeE2__Discard2",
      AD_CfgVLANEtherTypeE2, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE2__VLANEtherType2,
      "CfgVLANEtherTypeE2__VLANEtherType2",
      AD_CfgVLANEtherTypeE2, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE3,
      "CfgVLANEtherTypeE3",
      AD_CfgVLANEtherTypeE3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE3__Enable3,
      "CfgVLANEtherTypeE3__Enable3",
      AD_CfgVLANEtherTypeE3, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE3__Discard3,
      "CfgVLANEtherTypeE3__Discard3",
      AD_CfgVLANEtherTypeE3, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE3__VLANEtherType3,
      "CfgVLANEtherTypeE3__VLANEtherType3",
      AD_CfgVLANEtherTypeE3, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE4,
      "CfgVLANEtherTypeE4",
      AD_CfgVLANEtherTypeE4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE4__Enable4,
      "CfgVLANEtherTypeE4__Enable4",
      AD_CfgVLANEtherTypeE4, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE4__Discard4,
      "CfgVLANEtherTypeE4__Discard4",
      AD_CfgVLANEtherTypeE4, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE4__VLANEtherType4,
      "CfgVLANEtherTypeE4__VLANEtherType4",
      AD_CfgVLANEtherTypeE4, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE5,
      "CfgVLANEtherTypeE5",
      AD_CfgVLANEtherTypeE5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE5__Enable5,
      "CfgVLANEtherTypeE5__Enable5",
      AD_CfgVLANEtherTypeE5, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE5__Discard5,
      "CfgVLANEtherTypeE5__Discard5",
      AD_CfgVLANEtherTypeE5, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE5__VLANEtherType5,
      "CfgVLANEtherTypeE5__VLANEtherType5",
      AD_CfgVLANEtherTypeE5, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE6,
      "CfgVLANEtherTypeE6",
      AD_CfgVLANEtherTypeE6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE6__Enable6,
      "CfgVLANEtherTypeE6__Enable6",
      AD_CfgVLANEtherTypeE6, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE6__Discard6,
      "CfgVLANEtherTypeE6__Discard6",
      AD_CfgVLANEtherTypeE6, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE6__VLANEtherType6,
      "CfgVLANEtherTypeE6__VLANEtherType6",
      AD_CfgVLANEtherTypeE6, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE7,
      "CfgVLANEtherTypeE7",
      AD_CfgVLANEtherTypeE7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE7__Enable7,
      "CfgVLANEtherTypeE7__Enable7",
      AD_CfgVLANEtherTypeE7, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE7__Discard7,
      "CfgVLANEtherTypeE7__Discard7",
      AD_CfgVLANEtherTypeE7, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE7__VLANEtherType7,
      "CfgVLANEtherTypeE7__VLANEtherType7",
      AD_CfgVLANEtherTypeE7, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE8,
      "CfgVLANEtherTypeE8",
      AD_CfgVLANEtherTypeE8, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE8__Enable8,
      "CfgVLANEtherTypeE8__Enable8",
      AD_CfgVLANEtherTypeE8, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE8__Discard8,
      "CfgVLANEtherTypeE8__Discard8",
      AD_CfgVLANEtherTypeE8, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE8__VLANEtherType8,
      "CfgVLANEtherTypeE8__VLANEtherType8",
      AD_CfgVLANEtherTypeE8, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE9,
      "CfgVLANEtherTypeE9",
      AD_CfgVLANEtherTypeE9, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE9__Enable9,
      "CfgVLANEtherTypeE9__Enable9",
      AD_CfgVLANEtherTypeE9, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE9__Discard9,
      "CfgVLANEtherTypeE9__Discard9",
      AD_CfgVLANEtherTypeE9, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE9__VLANEtherType9,
      "CfgVLANEtherTypeE9__VLANEtherType9",
      AD_CfgVLANEtherTypeE9, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE10,
      "CfgVLANEtherTypeE10",
      AD_CfgVLANEtherTypeE10, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE10__Enable10,
      "CfgVLANEtherTypeE10__Enable10",
      AD_CfgVLANEtherTypeE10, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE10__Discard10,
      "CfgVLANEtherTypeE10__Discard10",
      AD_CfgVLANEtherTypeE10, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE10__VLANEtherType10,
      "CfgVLANEtherTypeE10__VLANEtherType10",
      AD_CfgVLANEtherTypeE10, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE11,
      "CfgVLANEtherTypeE11",
      AD_CfgVLANEtherTypeE11, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE11__Enable11,
      "CfgVLANEtherTypeE11__Enable11",
      AD_CfgVLANEtherTypeE11, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE11__Discard11,
      "CfgVLANEtherTypeE11__Discard11",
      AD_CfgVLANEtherTypeE11, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE11__VLANEtherType11,
      "CfgVLANEtherTypeE11__VLANEtherType11",
      AD_CfgVLANEtherTypeE11, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE12,
      "CfgVLANEtherTypeE12",
      AD_CfgVLANEtherTypeE12, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE12__Enable12,
      "CfgVLANEtherTypeE12__Enable12",
      AD_CfgVLANEtherTypeE12, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE12__Discard12,
      "CfgVLANEtherTypeE12__Discard12",
      AD_CfgVLANEtherTypeE12, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE12__VLANEtherType12,
      "CfgVLANEtherTypeE12__VLANEtherType12",
      AD_CfgVLANEtherTypeE12, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE13,
      "CfgVLANEtherTypeE13",
      AD_CfgVLANEtherTypeE13, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE13__Enable13,
      "CfgVLANEtherTypeE13__Enable13",
      AD_CfgVLANEtherTypeE13, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE13__Discard13,
      "CfgVLANEtherTypeE13__Discard13",
      AD_CfgVLANEtherTypeE13, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE13__VLANEtherType13,
      "CfgVLANEtherTypeE13__VLANEtherType13",
      AD_CfgVLANEtherTypeE13, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE14,
      "CfgVLANEtherTypeE14",
      AD_CfgVLANEtherTypeE14, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE14__Enable14,
      "CfgVLANEtherTypeE14__Enable14",
      AD_CfgVLANEtherTypeE14, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE14__Discard14,
      "CfgVLANEtherTypeE14__Discard14",
      AD_CfgVLANEtherTypeE14, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE14__VLANEtherType14,
      "CfgVLANEtherTypeE14__VLANEtherType14",
      AD_CfgVLANEtherTypeE14, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE15,
      "CfgVLANEtherTypeE15",
      AD_CfgVLANEtherTypeE15, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE15__Enable15,
      "CfgVLANEtherTypeE15__Enable15",
      AD_CfgVLANEtherTypeE15, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE15__Discard15,
      "CfgVLANEtherTypeE15__Discard15",
      AD_CfgVLANEtherTypeE15, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgVLANEtherTypeE15__VLANEtherType15,
      "CfgVLANEtherTypeE15__VLANEtherType15",
      AD_CfgVLANEtherTypeE15, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgSVLANEtherType,
      "CfgSVLANEtherType",
      AD_CfgSVLANEtherType, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgSVLANEtherType__Enable,
      "CfgSVLANEtherType__Enable",
      AD_CfgSVLANEtherType, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgSVLANEtherType__Discard,
      "CfgSVLANEtherType__Discard",
      AD_CfgSVLANEtherType, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgSVLANEtherType__SVLANEtherType,
      "CfgSVLANEtherType__SVLANEtherType",
      AD_CfgSVLANEtherType, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgSVLANCtrl,
      "CfgSVLANCtrl",
      AD_CfgSVLANCtrl, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgSVLANCtrl__Length,
      "CfgSVLANCtrl__Length",
      AD_CfgSVLANCtrl, 20, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgSVLANCtrl__QOSOffset,
      "CfgSVLANCtrl__QOSOffset",
      AD_CfgSVLANCtrl, 15, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgSVLANCtrl__IDOffset,
      "CfgSVLANCtrl__IDOffset",
      AD_CfgSVLANCtrl, 7, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0,
      "CfgNoVLANCtrl0",
      AD_CfgNoVLANCtrl0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__IndexJ,
      "CfgNoVLANCtrl0__IndexJ",
      AD_CfgNoVLANCtrl0, 28, 21, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__IndexI,
      "CfgNoVLANCtrl0__IndexI",
      AD_CfgNoVLANCtrl0, 20, 13, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__TagOp,
      "CfgNoVLANCtrl0__TagOp",
      AD_CfgNoVLANCtrl0, 12, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__DAFilterEn,
      "CfgNoVLANCtrl0__DAFilterEn",
      AD_CfgNoVLANCtrl0, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__HashFilterEn,
      "CfgNoVLANCtrl0__HashFilterEn",
      AD_CfgNoVLANCtrl0, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__TypeFilterEn,
      "CfgNoVLANCtrl0__TypeFilterEn",
      AD_CfgNoVLANCtrl0, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__LLCSNAPFilterEn,
      "CfgNoVLANCtrl0__LLCSNAPFilterEn",
      AD_CfgNoVLANCtrl0, 6, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__DSCPFilterEn,
      "CfgNoVLANCtrl0__DSCPFilterEn",
      AD_CfgNoVLANCtrl0, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__IPFilterEn,
      "CfgNoVLANCtrl0__IPFilterEn",
      AD_CfgNoVLANCtrl0, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__TimestampEn,
      "CfgNoVLANCtrl0__TimestampEn",
      AD_CfgNoVLANCtrl0, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__TimestampSel,
      "CfgNoVLANCtrl0__TimestampSel",
      AD_CfgNoVLANCtrl0, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__PriOvrWr,
      "CfgNoVLANCtrl0__PriOvrWr",
      AD_CfgNoVLANCtrl0, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl0__IDD,
      "CfgNoVLANCtrl0__IDD",
      AD_CfgNoVLANCtrl0, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl1,
      "CfgNoVLANCtrl1",
      AD_CfgNoVLANCtrl1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl1__Enable,
      "CfgNoVLANCtrl1__Enable",
      AD_CfgNoVLANCtrl1, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl1__Discard,
      "CfgNoVLANCtrl1__Discard",
      AD_CfgNoVLANCtrl1, 6, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl1__CoSType,
      "CfgNoVLANCtrl1__CoSType",
      AD_CfgNoVLANCtrl1, 5, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNoVLANCtrl1__CValue,
      "CfgNoVLANCtrl1__CValue",
      AD_CfgNoVLANCtrl1, 3, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap0,
      "CfgIngressPrioMap0",
      AD_CfgIngressPrioMap0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap1,
      "CfgIngressPrioMap1",
      AD_CfgIngressPrioMap1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap2,
      "CfgIngressPrioMap2",
      AD_CfgIngressPrioMap2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap3,
      "CfgIngressPrioMap3",
      AD_CfgIngressPrioMap3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap4,
      "CfgIngressPrioMap4",
      AD_CfgIngressPrioMap4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap5,
      "CfgIngressPrioMap5",
      AD_CfgIngressPrioMap5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap6,
      "CfgIngressPrioMap6",
      AD_CfgIngressPrioMap6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap7,
      "CfgIngressPrioMap7",
      AD_CfgIngressPrioMap7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap8,
      "CfgIngressPrioMap8",
      AD_CfgIngressPrioMap8, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap9,
      "CfgIngressPrioMap9",
      AD_CfgIngressPrioMap9, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap10,
      "CfgIngressPrioMap10",
      AD_CfgIngressPrioMap10, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap11,
      "CfgIngressPrioMap11",
      AD_CfgIngressPrioMap11, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap12,
      "CfgIngressPrioMap12",
      AD_CfgIngressPrioMap12, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap13,
      "CfgIngressPrioMap13",
      AD_CfgIngressPrioMap13, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressPrioMap14,
      "CfgIngressPrioMap14",
      AD_CfgIngressPrioMap14, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressExtdPrioMap0,
      "CfgIngressExtdPrioMap0",
      AD_CfgIngressExtdPrioMap0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIngressExtdPrioMap1,
      "CfgIngressExtdPrioMap1",
      AD_CfgIngressExtdPrioMap1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchLSB0,
      "CfgMACDAMatchLSB0",
      AD_CfgMACDAMatchLSB0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchMSB0,
      "CfgMACDAMatchMSB0",
      AD_CfgMACDAMatchMSB0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchLSB1,
      "CfgMACDAMatchLSB1",
      AD_CfgMACDAMatchLSB1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchMSB1,
      "CfgMACDAMatchMSB1",
      AD_CfgMACDAMatchMSB1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchLSB2,
      "CfgMACDAMatchLSB2",
      AD_CfgMACDAMatchLSB2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchMSB2,
      "CfgMACDAMatchMSB2",
      AD_CfgMACDAMatchMSB2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchLSB3,
      "CfgMACDAMatchLSB3",
      AD_CfgMACDAMatchLSB3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchMSB3,
      "CfgMACDAMatchMSB3",
      AD_CfgMACDAMatchMSB3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchLSB4,
      "CfgMACDAMatchLSB4",
      AD_CfgMACDAMatchLSB4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchMSB4,
      "CfgMACDAMatchMSB4",
      AD_CfgMACDAMatchMSB4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchLSB5,
      "CfgMACDAMatchLSB5",
      AD_CfgMACDAMatchLSB5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchMSB5,
      "CfgMACDAMatchMSB5",
      AD_CfgMACDAMatchMSB5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchLSB6,
      "CfgMACDAMatchLSB6",
      AD_CfgMACDAMatchLSB6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchMSB6,
      "CfgMACDAMatchMSB6",
      AD_CfgMACDAMatchMSB6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchLSB7,
      "CfgMACDAMatchLSB7",
      AD_CfgMACDAMatchLSB7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMatchMSB7,
      "CfgMACDAMatchMSB7",
      AD_CfgMACDAMatchMSB7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskLSB0,
      "CfgMACDAMaskLSB0",
      AD_CfgMACDAMaskLSB0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskMSB0,
      "CfgMACDAMaskMSB0",
      AD_CfgMACDAMaskMSB0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskLSB1,
      "CfgMACDAMaskLSB1",
      AD_CfgMACDAMaskLSB1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskMSB1,
      "CfgMACDAMaskMSB1",
      AD_CfgMACDAMaskMSB1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskLSB2,
      "CfgMACDAMaskLSB2",
      AD_CfgMACDAMaskLSB2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskMSB2,
      "CfgMACDAMaskMSB2",
      AD_CfgMACDAMaskMSB2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskLSB3,
      "CfgMACDAMaskLSB3",
      AD_CfgMACDAMaskLSB3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskMSB3,
      "CfgMACDAMaskMSB3",
      AD_CfgMACDAMaskMSB3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskLSB4,
      "CfgMACDAMaskLSB4",
      AD_CfgMACDAMaskLSB4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskMSB4,
      "CfgMACDAMaskMSB4",
      AD_CfgMACDAMaskMSB4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskLSB5,
      "CfgMACDAMaskLSB5",
      AD_CfgMACDAMaskLSB5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskMSB5,
      "CfgMACDAMaskMSB5",
      AD_CfgMACDAMaskMSB5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskLSB6,
      "CfgMACDAMaskLSB6",
      AD_CfgMACDAMaskLSB6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskMSB6,
      "CfgMACDAMaskMSB6",
      AD_CfgMACDAMaskMSB6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskLSB7,
      "CfgMACDAMaskLSB7",
      AD_CfgMACDAMaskLSB7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDAMaskMSB7,
      "CfgMACDAMaskMSB7",
      AD_CfgMACDAMaskMSB7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl0,
      "CfgMACDACtrl0",
      AD_CfgMACDACtrl0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl0__Discard0,
      "CfgMACDACtrl0__Discard0",
      AD_CfgMACDACtrl0, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl0__CoSType0,
      "CfgMACDACtrl0__CoSType0",
      AD_CfgMACDACtrl0, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl0__CValue0,
      "CfgMACDACtrl0__CValue0",
      AD_CfgMACDACtrl0, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl0__IDD0,
      "CfgMACDACtrl0__IDD0",
      AD_CfgMACDACtrl0, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl1,
      "CfgMACDACtrl1",
      AD_CfgMACDACtrl1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl1__Discard1,
      "CfgMACDACtrl1__Discard1",
      AD_CfgMACDACtrl1, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl1__CoSType1,
      "CfgMACDACtrl1__CoSType1",
      AD_CfgMACDACtrl1, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl1__CValue1,
      "CfgMACDACtrl1__CValue1",
      AD_CfgMACDACtrl1, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl1__IDD1,
      "CfgMACDACtrl1__IDD1",
      AD_CfgMACDACtrl1, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl2,
      "CfgMACDACtrl2",
      AD_CfgMACDACtrl2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl2__Discard2,
      "CfgMACDACtrl2__Discard2",
      AD_CfgMACDACtrl2, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl2__CoSType2,
      "CfgMACDACtrl2__CoSType2",
      AD_CfgMACDACtrl2, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl2__CValue2,
      "CfgMACDACtrl2__CValue2",
      AD_CfgMACDACtrl2, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl2__IDD2,
      "CfgMACDACtrl2__IDD2",
      AD_CfgMACDACtrl2, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl3,
      "CfgMACDACtrl3",
      AD_CfgMACDACtrl3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl3__Discard3,
      "CfgMACDACtrl3__Discard3",
      AD_CfgMACDACtrl3, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl3__CoSType3,
      "CfgMACDACtrl3__CoSType3",
      AD_CfgMACDACtrl3, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl3__CValue3,
      "CfgMACDACtrl3__CValue3",
      AD_CfgMACDACtrl3, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl3__IDD3,
      "CfgMACDACtrl3__IDD3",
      AD_CfgMACDACtrl3, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl4,
      "CfgMACDACtrl4",
      AD_CfgMACDACtrl4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl4__Discard4,
      "CfgMACDACtrl4__Discard4",
      AD_CfgMACDACtrl4, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl4__CoSType4,
      "CfgMACDACtrl4__CoSType4",
      AD_CfgMACDACtrl4, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl4__CValue4,
      "CfgMACDACtrl4__CValue4",
      AD_CfgMACDACtrl4, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl4__IDD4,
      "CfgMACDACtrl4__IDD4",
      AD_CfgMACDACtrl4, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl5,
      "CfgMACDACtrl5",
      AD_CfgMACDACtrl5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl5__Discard5,
      "CfgMACDACtrl5__Discard5",
      AD_CfgMACDACtrl5, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl5__CoSType5,
      "CfgMACDACtrl5__CoSType5",
      AD_CfgMACDACtrl5, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl5__CValue5,
      "CfgMACDACtrl5__CValue5",
      AD_CfgMACDACtrl5, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl5__IDD5,
      "CfgMACDACtrl5__IDD5",
      AD_CfgMACDACtrl5, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl6,
      "CfgMACDACtrl6",
      AD_CfgMACDACtrl6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl6__Discard6,
      "CfgMACDACtrl6__Discard6",
      AD_CfgMACDACtrl6, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl6__CoSType6,
      "CfgMACDACtrl6__CoSType6",
      AD_CfgMACDACtrl6, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl6__CValue6,
      "CfgMACDACtrl6__CValue6",
      AD_CfgMACDACtrl6, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl6__IDD6,
      "CfgMACDACtrl6__IDD6",
      AD_CfgMACDACtrl6, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl7,
      "CfgMACDACtrl7",
      AD_CfgMACDACtrl7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl7__Discard7,
      "CfgMACDACtrl7__Discard7",
      AD_CfgMACDACtrl7, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl7__CoSType7,
      "CfgMACDACtrl7__CoSType7",
      AD_CfgMACDACtrl7, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl7__CValue7,
      "CfgMACDACtrl7__CValue7",
      AD_CfgMACDACtrl7, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMACDACtrl7__IDD7,
      "CfgMACDACtrl7__IDD7",
      AD_CfgMACDACtrl7, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgHashSel,
      "CfgHashSel",
      AD_CfgHashSel, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl0,
      "CfgTypeCtrl0",
      AD_CfgTypeCtrl0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl0__Match0,
      "CfgTypeCtrl0__Match0",
      AD_CfgTypeCtrl0, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl0__Enable0,
      "CfgTypeCtrl0__Enable0",
      AD_CfgTypeCtrl0, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl0__Discard0,
      "CfgTypeCtrl0__Discard0",
      AD_CfgTypeCtrl0, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl0__CoSType0,
      "CfgTypeCtrl0__CoSType0",
      AD_CfgTypeCtrl0, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl0__CValue0,
      "CfgTypeCtrl0__CValue0",
      AD_CfgTypeCtrl0, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl0__IDD0,
      "CfgTypeCtrl0__IDD0",
      AD_CfgTypeCtrl0, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl1,
      "CfgTypeCtrl1",
      AD_CfgTypeCtrl1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl1__Match1,
      "CfgTypeCtrl1__Match1",
      AD_CfgTypeCtrl1, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl1__Enable1,
      "CfgTypeCtrl1__Enable1",
      AD_CfgTypeCtrl1, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl1__Discard1,
      "CfgTypeCtrl1__Discard1",
      AD_CfgTypeCtrl1, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl1__CoSType1,
      "CfgTypeCtrl1__CoSType1",
      AD_CfgTypeCtrl1, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl1__CValue1,
      "CfgTypeCtrl1__CValue1",
      AD_CfgTypeCtrl1, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl1__IDD1,
      "CfgTypeCtrl1__IDD1",
      AD_CfgTypeCtrl1, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl2,
      "CfgTypeCtrl2",
      AD_CfgTypeCtrl2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl2__Match2,
      "CfgTypeCtrl2__Match2",
      AD_CfgTypeCtrl2, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl2__Enable2,
      "CfgTypeCtrl2__Enable2",
      AD_CfgTypeCtrl2, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl2__Discard2,
      "CfgTypeCtrl2__Discard2",
      AD_CfgTypeCtrl2, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl2__CoSType2,
      "CfgTypeCtrl2__CoSType2",
      AD_CfgTypeCtrl2, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl2__CValue2,
      "CfgTypeCtrl2__CValue2",
      AD_CfgTypeCtrl2, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl2__IDD2,
      "CfgTypeCtrl2__IDD2",
      AD_CfgTypeCtrl2, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl3,
      "CfgTypeCtrl3",
      AD_CfgTypeCtrl3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl3__Match3,
      "CfgTypeCtrl3__Match3",
      AD_CfgTypeCtrl3, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl3__Enable3,
      "CfgTypeCtrl3__Enable3",
      AD_CfgTypeCtrl3, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl3__Discard3,
      "CfgTypeCtrl3__Discard3",
      AD_CfgTypeCtrl3, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl3__CoSType3,
      "CfgTypeCtrl3__CoSType3",
      AD_CfgTypeCtrl3, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl3__CValue3,
      "CfgTypeCtrl3__CValue3",
      AD_CfgTypeCtrl3, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl3__IDD3,
      "CfgTypeCtrl3__IDD3",
      AD_CfgTypeCtrl3, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl4,
      "CfgTypeCtrl4",
      AD_CfgTypeCtrl4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl4__Match4,
      "CfgTypeCtrl4__Match4",
      AD_CfgTypeCtrl4, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl4__Enable4,
      "CfgTypeCtrl4__Enable4",
      AD_CfgTypeCtrl4, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl4__Discard4,
      "CfgTypeCtrl4__Discard4",
      AD_CfgTypeCtrl4, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl4__CoSType4,
      "CfgTypeCtrl4__CoSType4",
      AD_CfgTypeCtrl4, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl4__CValue4,
      "CfgTypeCtrl4__CValue4",
      AD_CfgTypeCtrl4, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl4__IDD4,
      "CfgTypeCtrl4__IDD4",
      AD_CfgTypeCtrl4, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl5,
      "CfgTypeCtrl5",
      AD_CfgTypeCtrl5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl5__Match5,
      "CfgTypeCtrl5__Match5",
      AD_CfgTypeCtrl5, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl5__Enable5,
      "CfgTypeCtrl5__Enable5",
      AD_CfgTypeCtrl5, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl5__Discard5,
      "CfgTypeCtrl5__Discard5",
      AD_CfgTypeCtrl5, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl5__CoSType5,
      "CfgTypeCtrl5__CoSType5",
      AD_CfgTypeCtrl5, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl5__CValue5,
      "CfgTypeCtrl5__CValue5",
      AD_CfgTypeCtrl5, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl5__IDD5,
      "CfgTypeCtrl5__IDD5",
      AD_CfgTypeCtrl5, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl6,
      "CfgTypeCtrl6",
      AD_CfgTypeCtrl6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl6__Match6,
      "CfgTypeCtrl6__Match6",
      AD_CfgTypeCtrl6, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl6__Enable6,
      "CfgTypeCtrl6__Enable6",
      AD_CfgTypeCtrl6, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl6__Discard6,
      "CfgTypeCtrl6__Discard6",
      AD_CfgTypeCtrl6, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl6__CoSType6,
      "CfgTypeCtrl6__CoSType6",
      AD_CfgTypeCtrl6, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl6__CValue6,
      "CfgTypeCtrl6__CValue6",
      AD_CfgTypeCtrl6, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl6__IDD6,
      "CfgTypeCtrl6__IDD6",
      AD_CfgTypeCtrl6, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl7,
      "CfgTypeCtrl7",
      AD_CfgTypeCtrl7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl7__Match7,
      "CfgTypeCtrl7__Match7",
      AD_CfgTypeCtrl7, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl7__Enable7,
      "CfgTypeCtrl7__Enable7",
      AD_CfgTypeCtrl7, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl7__Discard7,
      "CfgTypeCtrl7__Discard7",
      AD_CfgTypeCtrl7, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl7__CoSType7,
      "CfgTypeCtrl7__CoSType7",
      AD_CfgTypeCtrl7, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl7__CValue7,
      "CfgTypeCtrl7__CValue7",
      AD_CfgTypeCtrl7, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl7__IDD7,
      "CfgTypeCtrl7__IDD7",
      AD_CfgTypeCtrl7, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl8,
      "CfgTypeCtrl8",
      AD_CfgTypeCtrl8, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl8__Match8,
      "CfgTypeCtrl8__Match8",
      AD_CfgTypeCtrl8, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl8__Enable8,
      "CfgTypeCtrl8__Enable8",
      AD_CfgTypeCtrl8, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl8__Discard8,
      "CfgTypeCtrl8__Discard8",
      AD_CfgTypeCtrl8, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl8__CoSType8,
      "CfgTypeCtrl8__CoSType8",
      AD_CfgTypeCtrl8, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl8__CValue8,
      "CfgTypeCtrl8__CValue8",
      AD_CfgTypeCtrl8, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl8__IDD8,
      "CfgTypeCtrl8__IDD8",
      AD_CfgTypeCtrl8, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl9,
      "CfgTypeCtrl9",
      AD_CfgTypeCtrl9, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl9__Match9,
      "CfgTypeCtrl9__Match9",
      AD_CfgTypeCtrl9, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl9__Enable9,
      "CfgTypeCtrl9__Enable9",
      AD_CfgTypeCtrl9, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl9__Discard9,
      "CfgTypeCtrl9__Discard9",
      AD_CfgTypeCtrl9, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl9__CoSType9,
      "CfgTypeCtrl9__CoSType9",
      AD_CfgTypeCtrl9, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl9__CValue9,
      "CfgTypeCtrl9__CValue9",
      AD_CfgTypeCtrl9, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl9__IDD9,
      "CfgTypeCtrl9__IDD9",
      AD_CfgTypeCtrl9, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl10,
      "CfgTypeCtrl10",
      AD_CfgTypeCtrl10, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl10__Match10,
      "CfgTypeCtrl10__Match10",
      AD_CfgTypeCtrl10, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl10__Enable10,
      "CfgTypeCtrl10__Enable10",
      AD_CfgTypeCtrl10, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl10__Discard10,
      "CfgTypeCtrl10__Discard10",
      AD_CfgTypeCtrl10, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl10__CoSType10,
      "CfgTypeCtrl10__CoSType10",
      AD_CfgTypeCtrl10, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl10__CValue10,
      "CfgTypeCtrl10__CValue10",
      AD_CfgTypeCtrl10, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl10__IDD10,
      "CfgTypeCtrl10__IDD10",
      AD_CfgTypeCtrl10, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl11,
      "CfgTypeCtrl11",
      AD_CfgTypeCtrl11, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl11__Match11,
      "CfgTypeCtrl11__Match11",
      AD_CfgTypeCtrl11, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl11__Enable11,
      "CfgTypeCtrl11__Enable11",
      AD_CfgTypeCtrl11, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl11__Discard11,
      "CfgTypeCtrl11__Discard11",
      AD_CfgTypeCtrl11, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl11__CoSType11,
      "CfgTypeCtrl11__CoSType11",
      AD_CfgTypeCtrl11, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl11__CValue11,
      "CfgTypeCtrl11__CValue11",
      AD_CfgTypeCtrl11, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl11__IDD11,
      "CfgTypeCtrl11__IDD11",
      AD_CfgTypeCtrl11, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl12,
      "CfgTypeCtrl12",
      AD_CfgTypeCtrl12, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl12__Match12,
      "CfgTypeCtrl12__Match12",
      AD_CfgTypeCtrl12, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl12__Enable12,
      "CfgTypeCtrl12__Enable12",
      AD_CfgTypeCtrl12, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl12__Discard12,
      "CfgTypeCtrl12__Discard12",
      AD_CfgTypeCtrl12, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl12__CoSType12,
      "CfgTypeCtrl12__CoSType12",
      AD_CfgTypeCtrl12, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl12__CValue12,
      "CfgTypeCtrl12__CValue12",
      AD_CfgTypeCtrl12, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl12__IDD12,
      "CfgTypeCtrl12__IDD12",
      AD_CfgTypeCtrl12, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl13,
      "CfgTypeCtrl13",
      AD_CfgTypeCtrl13, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl13__Match13,
      "CfgTypeCtrl13__Match13",
      AD_CfgTypeCtrl13, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl13__Enable13,
      "CfgTypeCtrl13__Enable13",
      AD_CfgTypeCtrl13, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl13__Discard13,
      "CfgTypeCtrl13__Discard13",
      AD_CfgTypeCtrl13, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl13__CoSType13,
      "CfgTypeCtrl13__CoSType13",
      AD_CfgTypeCtrl13, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl13__CValue13,
      "CfgTypeCtrl13__CValue13",
      AD_CfgTypeCtrl13, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl13__IDD13,
      "CfgTypeCtrl13__IDD13",
      AD_CfgTypeCtrl13, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl14,
      "CfgTypeCtrl14",
      AD_CfgTypeCtrl14, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl14__Match14,
      "CfgTypeCtrl14__Match14",
      AD_CfgTypeCtrl14, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl14__Enable14,
      "CfgTypeCtrl14__Enable14",
      AD_CfgTypeCtrl14, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl14__Discard14,
      "CfgTypeCtrl14__Discard14",
      AD_CfgTypeCtrl14, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl14__CoSType14,
      "CfgTypeCtrl14__CoSType14",
      AD_CfgTypeCtrl14, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl14__CValue14,
      "CfgTypeCtrl14__CValue14",
      AD_CfgTypeCtrl14, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl14__IDD14,
      "CfgTypeCtrl14__IDD14",
      AD_CfgTypeCtrl14, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl15,
      "CfgTypeCtrl15",
      AD_CfgTypeCtrl15, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl15__Match15,
      "CfgTypeCtrl15__Match15",
      AD_CfgTypeCtrl15, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl15__Enable15,
      "CfgTypeCtrl15__Enable15",
      AD_CfgTypeCtrl15, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl15__Discard15,
      "CfgTypeCtrl15__Discard15",
      AD_CfgTypeCtrl15, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl15__CoSType15,
      "CfgTypeCtrl15__CoSType15",
      AD_CfgTypeCtrl15, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl15__CValue15,
      "CfgTypeCtrl15__CValue15",
      AD_CfgTypeCtrl15, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl15__IDD15,
      "CfgTypeCtrl15__IDD15",
      AD_CfgTypeCtrl15, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl16,
      "CfgTypeCtrl16",
      AD_CfgTypeCtrl16, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl16__Match16,
      "CfgTypeCtrl16__Match16",
      AD_CfgTypeCtrl16, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl16__Enable16,
      "CfgTypeCtrl16__Enable16",
      AD_CfgTypeCtrl16, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl16__Discard16,
      "CfgTypeCtrl16__Discard16",
      AD_CfgTypeCtrl16, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl16__CoSType16,
      "CfgTypeCtrl16__CoSType16",
      AD_CfgTypeCtrl16, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl16__CValue16,
      "CfgTypeCtrl16__CValue16",
      AD_CfgTypeCtrl16, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl16__IDD16,
      "CfgTypeCtrl16__IDD16",
      AD_CfgTypeCtrl16, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl17,
      "CfgTypeCtrl17",
      AD_CfgTypeCtrl17, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl17__Match17,
      "CfgTypeCtrl17__Match17",
      AD_CfgTypeCtrl17, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl17__Enable17,
      "CfgTypeCtrl17__Enable17",
      AD_CfgTypeCtrl17, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl17__Discard17,
      "CfgTypeCtrl17__Discard17",
      AD_CfgTypeCtrl17, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl17__CoSType17,
      "CfgTypeCtrl17__CoSType17",
      AD_CfgTypeCtrl17, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl17__CValue17,
      "CfgTypeCtrl17__CValue17",
      AD_CfgTypeCtrl17, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl17__IDD17,
      "CfgTypeCtrl17__IDD17",
      AD_CfgTypeCtrl17, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl18,
      "CfgTypeCtrl18",
      AD_CfgTypeCtrl18, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl18__Match18,
      "CfgTypeCtrl18__Match18",
      AD_CfgTypeCtrl18, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl18__Enable18,
      "CfgTypeCtrl18__Enable18",
      AD_CfgTypeCtrl18, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl18__Discard18,
      "CfgTypeCtrl18__Discard18",
      AD_CfgTypeCtrl18, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl18__CoSType18,
      "CfgTypeCtrl18__CoSType18",
      AD_CfgTypeCtrl18, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl18__CValue18,
      "CfgTypeCtrl18__CValue18",
      AD_CfgTypeCtrl18, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl18__IDD18,
      "CfgTypeCtrl18__IDD18",
      AD_CfgTypeCtrl18, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl19,
      "CfgTypeCtrl19",
      AD_CfgTypeCtrl19, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl19__Match19,
      "CfgTypeCtrl19__Match19",
      AD_CfgTypeCtrl19, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl19__Enable19,
      "CfgTypeCtrl19__Enable19",
      AD_CfgTypeCtrl19, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl19__Discard19,
      "CfgTypeCtrl19__Discard19",
      AD_CfgTypeCtrl19, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl19__CoSType19,
      "CfgTypeCtrl19__CoSType19",
      AD_CfgTypeCtrl19, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl19__CValue19,
      "CfgTypeCtrl19__CValue19",
      AD_CfgTypeCtrl19, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl19__IDD19,
      "CfgTypeCtrl19__IDD19",
      AD_CfgTypeCtrl19, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl20,
      "CfgTypeCtrl20",
      AD_CfgTypeCtrl20, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl20__Match20,
      "CfgTypeCtrl20__Match20",
      AD_CfgTypeCtrl20, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl20__Enable20,
      "CfgTypeCtrl20__Enable20",
      AD_CfgTypeCtrl20, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl20__Discard20,
      "CfgTypeCtrl20__Discard20",
      AD_CfgTypeCtrl20, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl20__CoSType20,
      "CfgTypeCtrl20__CoSType20",
      AD_CfgTypeCtrl20, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl20__CValue20,
      "CfgTypeCtrl20__CValue20",
      AD_CfgTypeCtrl20, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl20__IDD20,
      "CfgTypeCtrl20__IDD20",
      AD_CfgTypeCtrl20, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl21,
      "CfgTypeCtrl21",
      AD_CfgTypeCtrl21, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl21__Match21,
      "CfgTypeCtrl21__Match21",
      AD_CfgTypeCtrl21, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl21__Enable21,
      "CfgTypeCtrl21__Enable21",
      AD_CfgTypeCtrl21, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl21__Discard21,
      "CfgTypeCtrl21__Discard21",
      AD_CfgTypeCtrl21, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl21__CoSType21,
      "CfgTypeCtrl21__CoSType21",
      AD_CfgTypeCtrl21, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl21__CValue21,
      "CfgTypeCtrl21__CValue21",
      AD_CfgTypeCtrl21, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl21__IDD21,
      "CfgTypeCtrl21__IDD21",
      AD_CfgTypeCtrl21, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl22,
      "CfgTypeCtrl22",
      AD_CfgTypeCtrl22, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl22__Match22,
      "CfgTypeCtrl22__Match22",
      AD_CfgTypeCtrl22, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl22__Enable22,
      "CfgTypeCtrl22__Enable22",
      AD_CfgTypeCtrl22, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl22__Discard22,
      "CfgTypeCtrl22__Discard22",
      AD_CfgTypeCtrl22, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl22__CoSType22,
      "CfgTypeCtrl22__CoSType22",
      AD_CfgTypeCtrl22, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl22__CValue22,
      "CfgTypeCtrl22__CValue22",
      AD_CfgTypeCtrl22, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl22__IDD22,
      "CfgTypeCtrl22__IDD22",
      AD_CfgTypeCtrl22, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl23,
      "CfgTypeCtrl23",
      AD_CfgTypeCtrl23, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl23__Match23,
      "CfgTypeCtrl23__Match23",
      AD_CfgTypeCtrl23, 24, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl23__Enable23,
      "CfgTypeCtrl23__Enable23",
      AD_CfgTypeCtrl23, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl23__Discard23,
      "CfgTypeCtrl23__Discard23",
      AD_CfgTypeCtrl23, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl23__CoSType23,
      "CfgTypeCtrl23__CoSType23",
      AD_CfgTypeCtrl23, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl23__CValue23,
      "CfgTypeCtrl23__CValue23",
      AD_CfgTypeCtrl23, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrl23__IDD23,
      "CfgTypeCtrl23__IDD23",
      AD_CfgTypeCtrl23, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrlD,
      "CfgTypeCtrlD",
      AD_CfgTypeCtrlD, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrlD__EnableD,
      "CfgTypeCtrlD__EnableD",
      AD_CfgTypeCtrlD, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrlD__DiscardD,
      "CfgTypeCtrlD__DiscardD",
      AD_CfgTypeCtrlD, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrlD__CoSTypeD,
      "CfgTypeCtrlD__CoSTypeD",
      AD_CfgTypeCtrlD, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrlD__CValueD,
      "CfgTypeCtrlD__CValueD",
      AD_CfgTypeCtrlD, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTypeCtrlD__IDDD,
      "CfgTypeCtrlD__IDDD",
      AD_CfgTypeCtrlD, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNetBIOSCtrl,
      "CfgNetBIOSCtrl",
      AD_CfgNetBIOSCtrl, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgNetBIOSCtrl__Enable,
      "CfgNetBIOSCtrl__Enable",
      AD_CfgNetBIOSCtrl, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNetBIOSCtrl__Discard,
      "CfgNetBIOSCtrl__Discard",
      AD_CfgNetBIOSCtrl, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNetBIOSCtrl__CoSType,
      "CfgNetBIOSCtrl__CoSType",
      AD_CfgNetBIOSCtrl, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNetBIOSCtrl__CValue,
      "CfgNetBIOSCtrl__CValue",
      AD_CfgNetBIOSCtrl, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgNetBIOSCtrl__IDD,
      "CfgNetBIOSCtrl__IDD",
      AD_CfgNetBIOSCtrl, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPXCtrl,
      "CfgIPXCtrl",
      AD_CfgIPXCtrl, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPXCtrl__Enable,
      "CfgIPXCtrl__Enable",
      AD_CfgIPXCtrl, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPXCtrl__Discard,
      "CfgIPXCtrl__Discard",
      AD_CfgIPXCtrl, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPXCtrl__CoSType,
      "CfgIPXCtrl__CoSType",
      AD_CfgIPXCtrl, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPXCtrl__CValue,
      "CfgIPXCtrl__CValue",
      AD_CfgIPXCtrl, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPXCtrl__IDD,
      "CfgIPXCtrl__IDD",
      AD_CfgIPXCtrl, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgAppleTalkCtrl,
      "CfgAppleTalkCtrl",
      AD_CfgAppleTalkCtrl, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgAppleTalkCtrl__Enable,
      "CfgAppleTalkCtrl__Enable",
      AD_CfgAppleTalkCtrl, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgAppleTalkCtrl__Discard,
      "CfgAppleTalkCtrl__Discard",
      AD_CfgAppleTalkCtrl, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgAppleTalkCtrl__CoSType,
      "CfgAppleTalkCtrl__CoSType",
      AD_CfgAppleTalkCtrl, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgAppleTalkCtrl__CValue,
      "CfgAppleTalkCtrl__CValue",
      AD_CfgAppleTalkCtrl, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgAppleTalkCtrl__IDD,
      "CfgAppleTalkCtrl__IDD",
      AD_CfgAppleTalkCtrl, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgOtherLLCCtrl,
      "CfgOtherLLCCtrl",
      AD_CfgOtherLLCCtrl, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgOtherLLCCtrl__Enable,
      "CfgOtherLLCCtrl__Enable",
      AD_CfgOtherLLCCtrl, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgOtherLLCCtrl__Discard,
      "CfgOtherLLCCtrl__Discard",
      AD_CfgOtherLLCCtrl, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgOtherLLCCtrl__CoSType,
      "CfgOtherLLCCtrl__CoSType",
      AD_CfgOtherLLCCtrl, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgOtherLLCCtrl__CValue,
      "CfgOtherLLCCtrl__CValue",
      AD_CfgOtherLLCCtrl, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgOtherLLCCtrl__IDD,
      "CfgOtherLLCCtrl__IDD",
      AD_CfgOtherLLCCtrl, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { Cfg8021HBTCtrl,
      "Cfg8021HBTCtrl",
      AD_Cfg8021HBTCtrl, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { Cfg8021HBTCtrl__Enable,
      "Cfg8021HBTCtrl__Enable",
      AD_Cfg8021HBTCtrl, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { Cfg8021HBTCtrl__Discard,
      "Cfg8021HBTCtrl__Discard",
      AD_Cfg8021HBTCtrl, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { Cfg8021HBTCtrl__CoSType,
      "Cfg8021HBTCtrl__CoSType",
      AD_Cfg8021HBTCtrl, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { Cfg8021HBTCtrl__CValue,
      "Cfg8021HBTCtrl__CValue",
      AD_Cfg8021HBTCtrl, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { Cfg8021HBTCtrl__IDD,
      "Cfg8021HBTCtrl__IDD",
      AD_Cfg8021HBTCtrl, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgUnknownProCtrl,
      "CfgUnknownProCtrl",
      AD_CfgUnknownProCtrl, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgUnknownProCtrl__Enable,
      "CfgUnknownProCtrl__Enable",
      AD_CfgUnknownProCtrl, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgUnknownProCtrl__Discard,
      "CfgUnknownProCtrl__Discard",
      AD_CfgUnknownProCtrl, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgUnknownProCtrl__CoSType,
      "CfgUnknownProCtrl__CoSType",
      AD_CfgUnknownProCtrl, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgUnknownProCtrl__CValue,
      "CfgUnknownProCtrl__CValue",
      AD_CfgUnknownProCtrl, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgUnknownProCtrl__IDD,
      "CfgUnknownProCtrl__IDD",
      AD_CfgUnknownProCtrl, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl0,
      "CfgPureLLCCtrl0",
      AD_CfgPureLLCCtrl0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl0__Match0,
      "CfgPureLLCCtrl0__Match0",
      AD_CfgPureLLCCtrl0, 16, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl0__Enable0,
      "CfgPureLLCCtrl0__Enable0",
      AD_CfgPureLLCCtrl0, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl0__Discard0,
      "CfgPureLLCCtrl0__Discard0",
      AD_CfgPureLLCCtrl0, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl0__CoSType0,
      "CfgPureLLCCtrl0__CoSType0",
      AD_CfgPureLLCCtrl0, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl0__CValue0,
      "CfgPureLLCCtrl0__CValue0",
      AD_CfgPureLLCCtrl0, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl0__IDD0,
      "CfgPureLLCCtrl0__IDD0",
      AD_CfgPureLLCCtrl0, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl1,
      "CfgPureLLCCtrl1",
      AD_CfgPureLLCCtrl1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl1__Match1,
      "CfgPureLLCCtrl1__Match1",
      AD_CfgPureLLCCtrl1, 16, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl1__Enable1,
      "CfgPureLLCCtrl1__Enable1",
      AD_CfgPureLLCCtrl1, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl1__Discard1,
      "CfgPureLLCCtrl1__Discard1",
      AD_CfgPureLLCCtrl1, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl1__CoSType1,
      "CfgPureLLCCtrl1__CoSType1",
      AD_CfgPureLLCCtrl1, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl1__CValue1,
      "CfgPureLLCCtrl1__CValue1",
      AD_CfgPureLLCCtrl1, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl1__IDD1,
      "CfgPureLLCCtrl1__IDD1",
      AD_CfgPureLLCCtrl1, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl2,
      "CfgPureLLCCtrl2",
      AD_CfgPureLLCCtrl2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl2__Match2,
      "CfgPureLLCCtrl2__Match2",
      AD_CfgPureLLCCtrl2, 16, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl2__Enable2,
      "CfgPureLLCCtrl2__Enable2",
      AD_CfgPureLLCCtrl2, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl2__Discard2,
      "CfgPureLLCCtrl2__Discard2",
      AD_CfgPureLLCCtrl2, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl2__CoSType2,
      "CfgPureLLCCtrl2__CoSType2",
      AD_CfgPureLLCCtrl2, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl2__CValue2,
      "CfgPureLLCCtrl2__CValue2",
      AD_CfgPureLLCCtrl2, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl2__IDD2,
      "CfgPureLLCCtrl2__IDD2",
      AD_CfgPureLLCCtrl2, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl3,
      "CfgPureLLCCtrl3",
      AD_CfgPureLLCCtrl3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl3__Match3,
      "CfgPureLLCCtrl3__Match3",
      AD_CfgPureLLCCtrl3, 16, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl3__Enable3,
      "CfgPureLLCCtrl3__Enable3",
      AD_CfgPureLLCCtrl3, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl3__Discard3,
      "CfgPureLLCCtrl3__Discard3",
      AD_CfgPureLLCCtrl3, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl3__CoSType3,
      "CfgPureLLCCtrl3__CoSType3",
      AD_CfgPureLLCCtrl3, 6, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl3__CValue3,
      "CfgPureLLCCtrl3__CValue3",
      AD_CfgPureLLCCtrl3, 4, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgPureLLCCtrl3__IDD3,
      "CfgPureLLCCtrl3__IDD3",
      AD_CfgPureLLCCtrl3, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch0,
      "CfgDSCPTypeMatch0",
      AD_CfgDSCPTypeMatch0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch0__Z0,
      "CfgDSCPTypeMatch0__Z0",
      AD_CfgDSCPTypeMatch0, 17, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch0__TypeMatch0,
      "CfgDSCPTypeMatch0__TypeMatch0",
      AD_CfgDSCPTypeMatch0, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch1,
      "CfgDSCPTypeMatch1",
      AD_CfgDSCPTypeMatch1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch1__Z1,
      "CfgDSCPTypeMatch1__Z1",
      AD_CfgDSCPTypeMatch1, 17, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch1__TypeMatch1,
      "CfgDSCPTypeMatch1__TypeMatch1",
      AD_CfgDSCPTypeMatch1, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch2,
      "CfgDSCPTypeMatch2",
      AD_CfgDSCPTypeMatch2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch2__Z2,
      "CfgDSCPTypeMatch2__Z2",
      AD_CfgDSCPTypeMatch2, 17, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch2__TypeMatch2,
      "CfgDSCPTypeMatch2__TypeMatch2",
      AD_CfgDSCPTypeMatch2, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch3,
      "CfgDSCPTypeMatch3",
      AD_CfgDSCPTypeMatch3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch3__Z3,
      "CfgDSCPTypeMatch3__Z3",
      AD_CfgDSCPTypeMatch3, 17, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch3__TypeMatch3,
      "CfgDSCPTypeMatch3__TypeMatch3",
      AD_CfgDSCPTypeMatch3, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch4,
      "CfgDSCPTypeMatch4",
      AD_CfgDSCPTypeMatch4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch4__Z4,
      "CfgDSCPTypeMatch4__Z4",
      AD_CfgDSCPTypeMatch4, 17, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch4__TypeMatch4,
      "CfgDSCPTypeMatch4__TypeMatch4",
      AD_CfgDSCPTypeMatch4, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch5,
      "CfgDSCPTypeMatch5",
      AD_CfgDSCPTypeMatch5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch5__Z5,
      "CfgDSCPTypeMatch5__Z5",
      AD_CfgDSCPTypeMatch5, 17, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch5__TypeMatch5,
      "CfgDSCPTypeMatch5__TypeMatch5",
      AD_CfgDSCPTypeMatch5, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch6,
      "CfgDSCPTypeMatch6",
      AD_CfgDSCPTypeMatch6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch6__Z6,
      "CfgDSCPTypeMatch6__Z6",
      AD_CfgDSCPTypeMatch6, 17, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch6__TypeMatch6,
      "CfgDSCPTypeMatch6__TypeMatch6",
      AD_CfgDSCPTypeMatch6, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch7,
      "CfgDSCPTypeMatch7",
      AD_CfgDSCPTypeMatch7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch7__Z7,
      "CfgDSCPTypeMatch7__Z7",
      AD_CfgDSCPTypeMatch7, 17, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPTypeMatch7__TypeMatch7,
      "CfgDSCPTypeMatch7__TypeMatch7",
      AD_CfgDSCPTypeMatch7, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgZFieldEncode0,
      "CfgZFieldEncode0",
      AD_CfgZFieldEncode0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgZFieldEncode0__DSCPOffset0,
      "CfgZFieldEncode0__DSCPOffset0",
      AD_CfgZFieldEncode0, 7, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgZFieldEncode0__VerMatch0,
      "CfgZFieldEncode0__VerMatch0",
      AD_CfgZFieldEncode0, 3, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPDefaultMatch,
      "CfgDSCPDefaultMatch",
      AD_CfgDSCPDefaultMatch, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPDefaultMatch__Enable,
      "CfgDSCPDefaultMatch__Enable",
      AD_CfgDSCPDefaultMatch, 10, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPDefaultMatch__Discard,
      "CfgDSCPDefaultMatch__Discard",
      AD_CfgDSCPDefaultMatch, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPDefaultMatch__CoSType,
      "CfgDSCPDefaultMatch__CoSType",
      AD_CfgDSCPDefaultMatch, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPDefaultMatch__CValue,
      "CfgDSCPDefaultMatch__CValue",
      AD_CfgDSCPDefaultMatch, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPDefaultMatch__IDD,
      "CfgDSCPDefaultMatch__IDD",
      AD_CfgDSCPDefaultMatch, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPDefaultMatch__TimestampEn,
      "CfgDSCPDefaultMatch__TimestampEn",
      AD_CfgDSCPDefaultMatch, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPDefaultMatch__TimestampSel,
      "CfgDSCPDefaultMatch__TimestampSel",
      AD_CfgDSCPDefaultMatch, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPVerMismatchCtrl,
      "CfgDSCPVerMismatchCtrl",
      AD_CfgDSCPVerMismatchCtrl, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPVerMismatchCtrl__Enable,
      "CfgDSCPVerMismatchCtrl__Enable",
      AD_CfgDSCPVerMismatchCtrl, 10, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPVerMismatchCtrl__Discard,
      "CfgDSCPVerMismatchCtrl__Discard",
      AD_CfgDSCPVerMismatchCtrl, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPVerMismatchCtrl__CoSType,
      "CfgDSCPVerMismatchCtrl__CoSType",
      AD_CfgDSCPVerMismatchCtrl, 8, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPVerMismatchCtrl__CValue,
      "CfgDSCPVerMismatchCtrl__CValue",
      AD_CfgDSCPVerMismatchCtrl, 6, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPVerMismatchCtrl__IDD,
      "CfgDSCPVerMismatchCtrl__IDD",
      AD_CfgDSCPVerMismatchCtrl, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPVerMismatchCtrl__TimestampEn,
      "CfgDSCPVerMismatchCtrl__TimestampEn",
      AD_CfgDSCPVerMismatchCtrl, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDSCPVerMismatchCtrl__TimestampSel,
      "CfgDSCPVerMismatchCtrl__TimestampSel",
      AD_CfgDSCPVerMismatchCtrl, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl0,
      "CfgIPCtrl0",
      AD_CfgIPCtrl0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl0__Match0,
      "CfgIPCtrl0__Match0",
      AD_CfgIPCtrl0, 17, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl0__Enable0,
      "CfgIPCtrl0__Enable0",
      AD_CfgIPCtrl0, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl0__Discard0,
      "CfgIPCtrl0__Discard0",
      AD_CfgIPCtrl0, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl0__CoSType0,
      "CfgIPCtrl0__CoSType0",
      AD_CfgIPCtrl0, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl0__CValue0,
      "CfgIPCtrl0__CValue0",
      AD_CfgIPCtrl0, 5, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl0__TimeStampEn0,
      "CfgIPCtrl0__TimeStampEn0",
      AD_CfgIPCtrl0, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl0__TimeStampSel0,
      "CfgIPCtrl0__TimeStampSel0",
      AD_CfgIPCtrl0, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl1,
      "CfgIPCtrl1",
      AD_CfgIPCtrl1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl1__Match1,
      "CfgIPCtrl1__Match1",
      AD_CfgIPCtrl1, 17, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl1__Enable1,
      "CfgIPCtrl1__Enable1",
      AD_CfgIPCtrl1, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl1__Discard1,
      "CfgIPCtrl1__Discard1",
      AD_CfgIPCtrl1, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl1__CoSType1,
      "CfgIPCtrl1__CoSType1",
      AD_CfgIPCtrl1, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl1__CValue1,
      "CfgIPCtrl1__CValue1",
      AD_CfgIPCtrl1, 5, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl1__TimeStampEn1,
      "CfgIPCtrl1__TimeStampEn1",
      AD_CfgIPCtrl1, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl1__TimeStampSel1,
      "CfgIPCtrl1__TimeStampSel1",
      AD_CfgIPCtrl1, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl2,
      "CfgIPCtrl2",
      AD_CfgIPCtrl2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl2__Match2,
      "CfgIPCtrl2__Match2",
      AD_CfgIPCtrl2, 17, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl2__Enable2,
      "CfgIPCtrl2__Enable2",
      AD_CfgIPCtrl2, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl2__Discard2,
      "CfgIPCtrl2__Discard2",
      AD_CfgIPCtrl2, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl2__CoSType2,
      "CfgIPCtrl2__CoSType2",
      AD_CfgIPCtrl2, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl2__CValue2,
      "CfgIPCtrl2__CValue2",
      AD_CfgIPCtrl2, 5, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl2__TimeStampEn2,
      "CfgIPCtrl2__TimeStampEn2",
      AD_CfgIPCtrl2, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl2__TimeStampSel2,
      "CfgIPCtrl2__TimeStampSel2",
      AD_CfgIPCtrl2, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl3,
      "CfgIPCtrl3",
      AD_CfgIPCtrl3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl3__Match3,
      "CfgIPCtrl3__Match3",
      AD_CfgIPCtrl3, 17, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl3__Enable3,
      "CfgIPCtrl3__Enable3",
      AD_CfgIPCtrl3, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl3__Discard3,
      "CfgIPCtrl3__Discard3",
      AD_CfgIPCtrl3, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl3__CoSType3,
      "CfgIPCtrl3__CoSType3",
      AD_CfgIPCtrl3, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl3__CValue3,
      "CfgIPCtrl3__CValue3",
      AD_CfgIPCtrl3, 5, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl3__TimeStampEn3,
      "CfgIPCtrl3__TimeStampEn3",
      AD_CfgIPCtrl3, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrl3__TimeStampSel3,
      "CfgIPCtrl3__TimeStampSel3",
      AD_CfgIPCtrl3, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrlD,
      "CfgIPCtrlD",
      AD_CfgIPCtrlD, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrlD__EnableD,
      "CfgIPCtrlD__EnableD",
      AD_CfgIPCtrlD, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrlD__DiscardD,
      "CfgIPCtrlD__DiscardD",
      AD_CfgIPCtrlD, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrlD__CoSTypeD,
      "CfgIPCtrlD__CoSTypeD",
      AD_CfgIPCtrlD, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrlD__CValueD,
      "CfgIPCtrlD__CValueD",
      AD_CfgIPCtrlD, 5, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrlD__TimeStampEnD,
      "CfgIPCtrlD__TimeStampEnD",
      AD_CfgIPCtrlD, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIPCtrlD__TimeStampSelD,
      "CfgIPCtrlD__TimeStampSelD",
      AD_CfgIPCtrlD, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc,
      "CfgMisc",
      AD_CfgMisc, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__MPLSNoChange,
      "CfgMisc__MPLSNoChange",
      AD_CfgMisc, 15, 15, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__NoCRCModif,
      "CfgMisc__NoCRCModif",
      AD_CfgMisc, 14, 14, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__DisableEccCheckIVLANCtrl,
      "CfgMisc__DisableEccCheckIVLANCtrl",
      AD_CfgMisc, 13, 13, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__DisableEccCheckIVLANCPU,
      "CfgMisc__DisableEccCheckIVLANCPU",
      AD_CfgMisc, 12, 12, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__DisableEccCheckOVLANCtrl,
      "CfgMisc__DisableEccCheckOVLANCtrl",
      AD_CfgMisc, 11, 11, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__DisableEccCheckOVLANCPU,
      "CfgMisc__DisableEccCheckOVLANCPU",
      AD_CfgMisc, 10, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__AllowGTPLdLength,
      "CfgMisc__AllowGTPLdLength",
      AD_CfgMisc, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__CRCErrDiscard,
      "CfgMisc__CRCErrDiscard",
      AD_CfgMisc, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__LengthErrDiscard,
      "CfgMisc__LengthErrDiscard",
      AD_CfgMisc, 7, 7, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__DAStripEn,
      "CfgMisc__DAStripEn",
      AD_CfgMisc, 6, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__SAStripEn,
      "CfgMisc__SAStripEn",
      AD_CfgMisc, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__DisableEccCheck,
      "CfgMisc__DisableEccCheck",
      AD_CfgMisc, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__DisableDrop,
      "CfgMisc__DisableDrop",
      AD_CfgMisc, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__DisableRead,
      "CfgMisc__DisableRead",
      AD_CfgMisc, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__CRCPassEn,
      "CfgMisc__CRCPassEn",
      AD_CfgMisc, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMisc__EMLModeEn,
      "CfgMisc__EMLModeEn",
      AD_CfgMisc, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscReadOnThreshold,
      "CfgMiscReadOnThreshold",
      AD_CfgMiscReadOnThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscReadOffThreshold,
      "CfgMiscReadOffThreshold",
      AD_CfgMiscReadOffThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscReadTimerValue,
      "CfgMiscReadTimerValue",
      AD_CfgMiscReadTimerValue, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscEccErrorInterrupt,
      "StsMiscEccErrorInterrupt",
      AD_StsMiscEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscEccErrorInterruptMask,
      "StsMiscEccErrorInterruptMask",
      AD_StsMiscEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscEccSingleErrorInterrupt,
      "StsMiscEccSingleErrorInterrupt",
      AD_StsMiscEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscEccSingleErrorInterruptMask,
      "StsMiscEccSingleErrorInterruptMask",
      AD_StsMiscEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscEccDoubleErrorInterrupt,
      "StsMiscEccDoubleErrorInterrupt",
      AD_StsMiscEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscEccDoubleErrorInterruptMask,
      "StsMiscEccDoubleErrorInterruptMask",
      AD_StsMiscEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscWritePointer,
      "StsMiscWritePointer",
      AD_StsMiscWritePointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscReadPointer,
      "StsMiscReadPointer",
      AD_StsMiscReadPointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscCommitPointer,
      "StsMiscCommitPointer",
      AD_StsMiscCommitPointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUAccess,
      "CfgMiscCPUAccess",
      AD_CfgMiscCPUAccess, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUAccess__CPUCommitPtrSet,
      "CfgMiscCPUAccess__CPUCommitPtrSet",
      AD_CfgMiscCPUAccess, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUAccess__CPURead,
      "CfgMiscCPUAccess__CPURead",
      AD_CfgMiscCPUAccess, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUAccess__CPUWrite,
      "CfgMiscCPUAccess__CPUWrite",
      AD_CfgMiscCPUAccess, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUAccess__CPUAccessEn,
      "CfgMiscCPUAccess__CPUAccessEn",
      AD_CfgMiscCPUAccess, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUWriteAddress,
      "CfgMiscCPUWriteAddress",
      AD_CfgMiscCPUWriteAddress, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUReadAddress,
      "CfgMiscCPUReadAddress",
      AD_CfgMiscCPUReadAddress, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUCommitPointer,
      "CfgMiscCPUCommitPointer",
      AD_CfgMiscCPUCommitPointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUWriteData_0,
      "CfgMiscCPUWriteData_0",
      AD_CfgMiscCPUWriteData_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUWriteData_1,
      "CfgMiscCPUWriteData_1",
      AD_CfgMiscCPUWriteData_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscCPUWriteData_2,
      "CfgMiscCPUWriteData_2",
      AD_CfgMiscCPUWriteData_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscCPUReadData_0,
      "StsMiscCPUReadData_0",
      AD_StsMiscCPUReadData_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscCPUReadData_1,
      "StsMiscCPUReadData_1",
      AD_StsMiscCPUReadData_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscCPUReadData_2,
      "StsMiscCPUReadData_2",
      AD_StsMiscCPUReadData_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCPUEccErrorInterrupt,
      "StsOVLANCPUEccErrorInterrupt",
      AD_StsOVLANCPUEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCPUEccErrorInterruptMask,
      "StsOVLANCPUEccErrorInterruptMask",
      AD_StsOVLANCPUEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCPUEccSingleErrorInterrupt,
      "StsOVLANCPUEccSingleErrorInterrupt",
      AD_StsOVLANCPUEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCPUEccSingleErrorInterruptMask,
      "StsOVLANCPUEccSingleErrorInterruptMask",
      AD_StsOVLANCPUEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCPUEccDoubleErrorInterrupt,
      "StsOVLANCPUEccDoubleErrorInterrupt",
      AD_StsOVLANCPUEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCPUEccDoubleErrorInterruptMask,
      "StsOVLANCPUEccDoubleErrorInterruptMask",
      AD_StsOVLANCPUEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCtrlEccErrorInterrupt,
      "StsOVLANCtrlEccErrorInterrupt",
      AD_StsOVLANCtrlEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCtrlEccErrorInterruptMask,
      "StsOVLANCtrlEccErrorInterruptMask",
      AD_StsOVLANCtrlEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCtrlEccSingleErrorInterrupt,
      "StsOVLANCtrlEccSingleErrorInterrupt",
      AD_StsOVLANCtrlEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCtrlEccSingleErrorInterruptMask,
      "StsOVLANCtrlEccSingleErrorInterruptMask",
      AD_StsOVLANCtrlEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCtrlEccDoubleErrorInterrupt,
      "StsOVLANCtrlEccDoubleErrorInterrupt",
      AD_StsOVLANCtrlEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOVLANCtrlEccDoubleErrorInterruptMask,
      "StsOVLANCtrlEccDoubleErrorInterruptMask",
      AD_StsOVLANCtrlEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCPUEccErrorInterrupt,
      "StsIVLANCPUEccErrorInterrupt",
      AD_StsIVLANCPUEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCPUEccErrorInterruptMask,
      "StsIVLANCPUEccErrorInterruptMask",
      AD_StsIVLANCPUEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCPUEccSingleErrorInterrupt,
      "StsIVLANCPUEccSingleErrorInterrupt",
      AD_StsIVLANCPUEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCPUEccSingleErrorInterruptMask,
      "StsIVLANCPUEccSingleErrorInterruptMask",
      AD_StsIVLANCPUEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCPUEccDoubleErrorInterrupt,
      "StsIVLANCPUEccDoubleErrorInterrupt",
      AD_StsIVLANCPUEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCPUEccDoubleErrorInterruptMask,
      "StsIVLANCPUEccDoubleErrorInterruptMask",
      AD_StsIVLANCPUEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCtrlEccErrorInterrupt,
      "StsIVLANCtrlEccErrorInterrupt",
      AD_StsIVLANCtrlEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCtrlEccErrorInterruptMask,
      "StsIVLANCtrlEccErrorInterruptMask",
      AD_StsIVLANCtrlEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCtrlEccSingleErrorInterrupt,
      "StsIVLANCtrlEccSingleErrorInterrupt",
      AD_StsIVLANCtrlEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCtrlEccSingleErrorInterruptMask,
      "StsIVLANCtrlEccSingleErrorInterruptMask",
      AD_StsIVLANCtrlEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCtrlEccDoubleErrorInterrupt,
      "StsIVLANCtrlEccDoubleErrorInterrupt",
      AD_StsIVLANCtrlEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIVLANCtrlEccDoubleErrorInterruptMask,
      "StsIVLANCtrlEccDoubleErrorInterruptMask",
      AD_StsIVLANCtrlEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgAsynFIFOFullThreshold,
      "CfgAsynFIFOFullThreshold",
      AD_CfgAsynFIFOFullThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMiscTailDropCount,
      "StsMiscTailDropCount",
      AD_StsMiscTailDropCount, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxDefaultDroppedFrms,
      "StsRegRxDefaultDroppedFrms",
      AD_StsRegRxDefaultDroppedFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegMSBRxDefaultDroppedOctets,
      "StsRegMSBRxDefaultDroppedOctets",
      AD_StsRegMSBRxDefaultDroppedOctets, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegLSBRxDefaultDroppedOctets,
      "StsRegLSBRxDefaultDroppedOctets",
      AD_StsRegLSBRxDefaultDroppedOctets, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxDroppedBCastFrms,
      "StsRegRxDroppedBCastFrms",
      AD_StsRegRxDroppedBCastFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxDroppedMCastFrms,
      "StsRegRxDroppedMCastFrms",
      AD_StsRegRxDroppedMCastFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegMSBRxDroppedBCastMCastOctets,
      "StsRegMSBRxDroppedBCastMCastOctets",
      AD_StsRegMSBRxDroppedBCastMCastOctets, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegLSBRxDroppedBCastMCastOctets,
      "StsRegLSBRxDroppedBCastMCastOctets",
      AD_StsRegLSBRxDroppedBCastMCastOctets, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxMPLSTypeMatchFrms,
      "StsRegRxMPLSTypeMatchFrms",
      AD_StsRegRxMPLSTypeMatchFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxMPLSDefaultMatchFrms,
      "StsRegRxMPLSDefaultMatchFrms",
      AD_StsRegRxMPLSDefaultMatchFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxMPLSLLSPMatchFrms,
      "StsRegRxMPLSLLSPMatchFrms",
      AD_StsRegRxMPLSLLSPMatchFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxMPLSDLLSPMatchFrms,
      "StsRegRxMPLSDLLSPMatchFrms",
      AD_StsRegRxMPLSDLLSPMatchFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxMPLSDroppedFrms,
      "StsRegRxMPLSDroppedFrms",
      AD_StsRegRxMPLSDroppedFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegMSBRxMPLSDroppedOctets,
      "StsRegMSBRxMPLSDroppedOctets",
      AD_StsRegMSBRxMPLSDroppedOctets, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegLSBRxMPLSDroppedOctets,
      "StsRegLSBRxMPLSDroppedOctets",
      AD_StsRegLSBRxMPLSDroppedOctets, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxVLANEthertypeFrms,
      "StsRegRxVLANEthertypeFrms",
      AD_StsRegRxVLANEthertypeFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxSVLANEthertypeFrms,
      "StsRegRxSVLANEthertypeFrms",
      AD_StsRegRxSVLANEthertypeFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxVLANSVLANEtherDropFrms,
      "StsRegRxVLANSVLANEtherDropFrms",
      AD_StsRegRxVLANSVLANEtherDropFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxStdPriMapFrms,
      "StsRegRxStdPriMapFrms",
      AD_StsRegRxStdPriMapFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxExtdPriMapFrms,
      "StsRegRxExtdPriMapFrms",
      AD_StsRegRxExtdPriMapFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxNoVLANTagFrms,
      "StsRegRxNoVLANTagFrms",
      AD_StsRegRxNoVLANTagFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxSingleVLANTagFrms,
      "StsRegRxSingleVLANTagFrms",
      AD_StsRegRxSingleVLANTagFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxDoubleVLANTagFrms,
      "StsRegRxDoubleVLANTagFrms",
      AD_StsRegRxDoubleVLANTagFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxMT2VLANTagFrms,
      "StsRegRxMT2VLANTagFrms",
      AD_StsRegRxMT2VLANTagFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxVLANControlDropFrms,
      "StsRegRxVLANControlDropFrms",
      AD_StsRegRxVLANControlDropFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxExtdVLANTagFrms,
      "StsRegRxExtdVLANTagFrms",
      AD_StsRegRxExtdVLANTagFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxVLANTagOpFrms,
      "StsRegRxVLANTagOpFrms",
      AD_StsRegRxVLANTagOpFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxVLANPrioOvrwrFrms,
      "StsRegRxVLANPrioOvrwrFrms",
      AD_StsRegRxVLANPrioOvrwrFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxDAMatchFrms,
      "StsRegRxDAMatchFrms",
      AD_StsRegRxDAMatchFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxMultiHashFrms,
      "StsRegRxMultiHashFrms",
      AD_StsRegRxMultiHashFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxTypeFrms,
      "StsRegRxTypeFrms",
      AD_StsRegRxTypeFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxOtherTypeFrms,
      "StsRegRxOtherTypeFrms",
      AD_StsRegRxOtherTypeFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxLLCSNAPFrms,
      "StsRegRxLLCSNAPFrms",
      AD_StsRegRxLLCSNAPFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxUnknownLLCSNAPFrms,
      "StsRegRxUnknownLLCSNAPFrms",
      AD_StsRegRxUnknownLLCSNAPFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxMACDropFrms,
      "StsRegRxMACDropFrms",
      AD_StsRegRxMACDropFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegMSBRxVLANMACDropOctets,
      "StsRegMSBRxVLANMACDropOctets",
      AD_StsRegMSBRxVLANMACDropOctets, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegLSBRxVLANMACDropOctets,
      "StsRegLSBRxVLANMACDropOctets",
      AD_StsRegLSBRxVLANMACDropOctets, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxDSCPIPVerMismatchFrms,
      "StsRegRxDSCPIPVerMismatchFrms",
      AD_StsRegRxDSCPIPVerMismatchFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxDSCPAssignFrms,
      "StsRegRxDSCPAssignFrms",
      AD_StsRegRxDSCPAssignFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxIPAssignFrms,
      "StsRegRxIPAssignFrms",
      AD_StsRegRxIPAssignFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxDIPAssignFrms,
      "StsRegRxDIPAssignFrms",
      AD_StsRegRxDIPAssignFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxDSCPIPDropFrms,
      "StsRegRxDSCPIPDropFrms",
      AD_StsRegRxDSCPIPDropFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegMSBRxDSCPIPDropOctets,
      "StsRegMSBRxDSCPIPDropOctets",
      AD_StsRegMSBRxDSCPIPDropOctets, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegLSBRxDSCPIPDropOctets,
      "StsRegLSBRxDSCPIPDropOctets",
      AD_StsRegLSBRxDSCPIPDropOctets, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxDropControlEOFs,
      "StsRegRxDropControlEOFs",
      AD_StsRegRxDropControlEOFs, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsOVLANCtrlRdData,
      "StsOVLANCtrlRdData",
      AD_StsOVLANCtrlRdData, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsIVLANCtrlRdData,
      "StsIVLANCtrlRdData",
      AD_StsIVLANCtrlRdData, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsVLANIDRdData,
      "StsVLANIDRdData",
      AD_StsVLANIDRdData, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsHashRdData,
      "StsHashRdData",
      AD_StsHashRdData, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsDSCPAssignData,
      "StsDSCPAssignData",
      AD_StsDSCPAssignData, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxIllegalTypeLenFrms,
      "StsRegRxIllegalTypeLenFrms",
      AD_StsRegRxIllegalTypeLenFrms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgOVLANCtrl,
      "CfgOVLANCtrl",
      AD_CfgOVLANCtrl, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgOVLANCtrl__Addr,
      "CfgOVLANCtrl__Addr",
      AD_CfgOVLANCtrl, 12, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgOVLANCtrl__Wr,
      "CfgOVLANCtrl__Wr",
      AD_CfgOVLANCtrl, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgOVLANCtrlData,
      "CfgOVLANCtrlData",
      AD_CfgOVLANCtrlData, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgIVLANCtrl,
      "CfgIVLANCtrl",
      AD_CfgIVLANCtrl, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgIVLANCtrl__Addr,
      "CfgIVLANCtrl__Addr",
      AD_CfgIVLANCtrl, 12, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgIVLANCtrl__Wr,
      "CfgIVLANCtrl__Wr",
      AD_CfgIVLANCtrl, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgIVLANCtrlData,
      "CfgIVLANCtrlData",
      AD_CfgIVLANCtrlData, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgVLANID,
      "CfgVLANID",
      AD_CfgVLANID, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgVLANID__Addr,
      "CfgVLANID__Addr",
      AD_CfgVLANID, 8, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgVLANID__Wr,
      "CfgVLANID__Wr",
      AD_CfgVLANID, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgVLANIDData,
      "CfgVLANIDData",
      AD_CfgVLANIDData, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRd256x32RxVlanTagRamReg,
      "CfgRd256x32RxVlanTagRamReg",
      AD_CfgRd256x32RxVlanTagRamReg, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRd256x32RxVlanTagRamReg__CfgRdAddrRxVlanTagRam,
      "CfgRd256x32RxVlanTagRamReg__CfgRdAddrRxVlanTagRam",
      AD_CfgRd256x32RxVlanTagRamReg, 8, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgRd256x32RxVlanTagRamReg__CfgRdEnRxVlanTagRam,
      "CfgRd256x32RxVlanTagRamReg__CfgRdEnRxVlanTagRam",
      AD_CfgRd256x32RxVlanTagRamReg, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { StsRdDataRxVlanTagRam,
      "StsRdDataRxVlanTagRam",
      AD_StsRdDataRxVlanTagRam, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgHashCtrl,
      "CfgHashCtrl",
      AD_CfgHashCtrl, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgHashCtrl__Data,
      "CfgHashCtrl__Data",
      AD_CfgHashCtrl, 14, 7, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgHashCtrl__Addr,
      "CfgHashCtrl__Addr",
      AD_CfgHashCtrl, 6, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgHashCtrl__Wr,
      "CfgHashCtrl__Wr",
      AD_CfgHashCtrl, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgDSCPAssign,
      "CfgDSCPAssign",
      AD_CfgDSCPAssign, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgDSCPAssign__Data,
      "CfgDSCPAssign__Data",
      AD_CfgDSCPAssign, 16, 7, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgDSCPAssign__Addr,
      "CfgDSCPAssign__Addr",
      AD_CfgDSCPAssign, 6, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgDSCPAssign__Wr,
      "CfgDSCPAssign__Wr",
      AD_CfgDSCPAssign, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgProgBitIDA,
      "CfgProgBitIDA",
      AD_CfgProgBitIDA, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgFunnel,
      "CfgFunnel",
      AD_CfgFunnel, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgSourcePort,
      "CfgSourcePort",
      AD_CfgSourcePort, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgDestinationPort,
      "CfgDestinationPort",
      AD_CfgDestinationPort, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgProgRegIDE,
      "CfgProgRegIDE",
      AD_CfgProgRegIDE, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgOVLANRdCtrl,
      "CfgOVLANRdCtrl",
      AD_CfgOVLANRdCtrl, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgOVLANRdCtrl__Addr,
      "CfgOVLANRdCtrl__Addr",
      AD_CfgOVLANRdCtrl, 12, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgOVLANRdCtrl__Rd,
      "CfgOVLANRdCtrl__Rd",
      AD_CfgOVLANRdCtrl, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgIVLANRdCtrl,
      "CfgIVLANRdCtrl",
      AD_CfgIVLANRdCtrl, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgIVLANRdCtrl__Addr,
      "CfgIVLANRdCtrl__Addr",
      AD_CfgIVLANRdCtrl, 12, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgIVLANRdCtrl__Rd,
      "CfgIVLANRdCtrl__Rd",
      AD_CfgIVLANRdCtrl, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgVLANIDRd,
      "CfgVLANIDRd",
      AD_CfgVLANIDRd, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgVLANIDRd__Addr,
      "CfgVLANIDRd__Addr",
      AD_CfgVLANIDRd, 8, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgVLANIDRd__Rd,
      "CfgVLANIDRd__Rd",
      AD_CfgVLANIDRd, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgHashRdCtrl,
      "CfgHashRdCtrl",
      AD_CfgHashRdCtrl, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgHashRdCtrl__Addr,
      "CfgHashRdCtrl__Addr",
      AD_CfgHashRdCtrl, 6, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgHashRdCtrl__Rd,
      "CfgHashRdCtrl__Rd",
      AD_CfgHashRdCtrl, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgDSCPAssignRd,
      "CfgDSCPAssignRd",
      AD_CfgDSCPAssignRd, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgDSCPAssignRd__Addr,
      "CfgDSCPAssignRd__Addr",
      AD_CfgDSCPAssignRd, 6, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgDSCPAssignRd__Rd,
      "CfgDSCPAssignRd__Rd",
      AD_CfgDSCPAssignRd, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxInRangeLengthErrs,
      "StsRegRxInRangeLengthErrs",
      AD_StsRegRxInRangeLengthErrs, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxOutofRangeLengthErrs,
      "StsRegRxOutofRangeLengthErrs",
      AD_StsRegRxOutofRangeLengthErrs, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxQueue0Frms,
      "StsRegRxQueue0Frms",
      AD_StsRegRxQueue0Frms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxQueue1Frms,
      "StsRegRxQueue1Frms",
      AD_StsRegRxQueue1Frms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxQueue2Frms,
      "StsRegRxQueue2Frms",
      AD_StsRegRxQueue2Frms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxQueue3Frms,
      "StsRegRxQueue3Frms",
      AD_StsRegRxQueue3Frms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxQueue4Frms,
      "StsRegRxQueue4Frms",
      AD_StsRegRxQueue4Frms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxQueue5Frms,
      "StsRegRxQueue5Frms",
      AD_StsRegRxQueue5Frms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxQueue6Frms,
      "StsRegRxQueue6Frms",
      AD_StsRegRxQueue6Frms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRegRxQueue7Frms,
      "StsRegRxQueue7Frms",
      AD_StsRegRxQueue7Frms, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA0LSB,
      "CfgBPDUDA0LSB",
      AD_CfgBPDUDA0LSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA0MSB,
      "CfgBPDUDA0MSB",
      AD_CfgBPDUDA0MSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA1LSB,
      "CfgBPDUDA1LSB",
      AD_CfgBPDUDA1LSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA1MSB,
      "CfgBPDUDA1MSB",
      AD_CfgBPDUDA1MSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA2LSB,
      "CfgBPDUDA2LSB",
      AD_CfgBPDUDA2LSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA2MSB,
      "CfgBPDUDA2MSB",
      AD_CfgBPDUDA2MSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA3LSB,
      "CfgBPDUDA3LSB",
      AD_CfgBPDUDA3LSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA3MSB,
      "CfgBPDUDA3MSB",
      AD_CfgBPDUDA3MSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA0MaskLSB,
      "CfgBPDUDA0MaskLSB",
      AD_CfgBPDUDA0MaskLSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA0MaskMSB,
      "CfgBPDUDA0MaskMSB",
      AD_CfgBPDUDA0MaskMSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA1MaskLSB,
      "CfgBPDUDA1MaskLSB",
      AD_CfgBPDUDA1MaskLSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA1MaskMSB,
      "CfgBPDUDA1MaskMSB",
      AD_CfgBPDUDA1MaskMSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA2MaskLSB,
      "CfgBPDUDA2MaskLSB",
      AD_CfgBPDUDA2MaskLSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA2MaskMSB,
      "CfgBPDUDA2MaskMSB",
      AD_CfgBPDUDA2MaskMSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA3MaskLSB,
      "CfgBPDUDA3MaskLSB",
      AD_CfgBPDUDA3MaskLSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgBPDUDA3MaskMSB,
      "CfgBPDUDA3MaskMSB",
      AD_CfgBPDUDA3MaskMSB, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgWREDMode,
      "CfgWREDMode",
      AD_CfgWREDMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMode__ColorMarkEn,
      "CfgWREDMode__ColorMarkEn",
      AD_CfgWREDMode, 31, 24, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMode__NonBPDUDropEn,
      "CfgWREDMode__NonBPDUDropEn",
      AD_CfgWREDMode, 23, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMode__TailDropEn,
      "CfgWREDMode__TailDropEn",
      AD_CfgWREDMode, 15, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMode__WREDEn,
      "CfgWREDMode__WREDEn",
      AD_CfgWREDMode, 7, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDQSmoothingMode,
      "CfgWREDQSmoothingMode",
      AD_CfgWREDQSmoothingMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMaxThrQ_0,
      "CfgWREDMaxThrQ_0",
      AD_CfgWREDMaxThrQ_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMaxThrQ_1,
      "CfgWREDMaxThrQ_1",
      AD_CfgWREDMaxThrQ_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMaxThrQ_2,
      "CfgWREDMaxThrQ_2",
      AD_CfgWREDMaxThrQ_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMaxThrQ_3,
      "CfgWREDMaxThrQ_3",
      AD_CfgWREDMaxThrQ_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMaxThrQ_4,
      "CfgWREDMaxThrQ_4",
      AD_CfgWREDMaxThrQ_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMaxThrQ_5,
      "CfgWREDMaxThrQ_5",
      AD_CfgWREDMaxThrQ_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMaxThrQ_6,
      "CfgWREDMaxThrQ_6",
      AD_CfgWREDMaxThrQ_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMaxThrQ_7,
      "CfgWREDMaxThrQ_7",
      AD_CfgWREDMaxThrQ_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMinThrFactorQ_0,
      "CfgWREDMinThrFactorQ_0",
      AD_CfgWREDMinThrFactorQ_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMinThrFactorQ_1,
      "CfgWREDMinThrFactorQ_1",
      AD_CfgWREDMinThrFactorQ_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMinThrFactorQ_2,
      "CfgWREDMinThrFactorQ_2",
      AD_CfgWREDMinThrFactorQ_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMinThrFactorQ_3,
      "CfgWREDMinThrFactorQ_3",
      AD_CfgWREDMinThrFactorQ_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMinThrFactorQ_4,
      "CfgWREDMinThrFactorQ_4",
      AD_CfgWREDMinThrFactorQ_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMinThrFactorQ_5,
      "CfgWREDMinThrFactorQ_5",
      AD_CfgWREDMinThrFactorQ_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMinThrFactorQ_6,
      "CfgWREDMinThrFactorQ_6",
      AD_CfgWREDMinThrFactorQ_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDMinThrFactorQ_7,
      "CfgWREDMinThrFactorQ_7",
      AD_CfgWREDMinThrFactorQ_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBPDUThreshold_0,
      "CfgBPDUThreshold_0",
      AD_CfgBPDUThreshold_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBPDUThreshold_1,
      "CfgBPDUThreshold_1",
      AD_CfgBPDUThreshold_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBPDUThreshold_2,
      "CfgBPDUThreshold_2",
      AD_CfgBPDUThreshold_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBPDUThreshold_3,
      "CfgBPDUThreshold_3",
      AD_CfgBPDUThreshold_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBPDUThreshold_4,
      "CfgBPDUThreshold_4",
      AD_CfgBPDUThreshold_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBPDUThreshold_5,
      "CfgBPDUThreshold_5",
      AD_CfgBPDUThreshold_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBPDUThreshold_6,
      "CfgBPDUThreshold_6",
      AD_CfgBPDUThreshold_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBPDUThreshold_7,
      "CfgBPDUThreshold_7",
      AD_CfgBPDUThreshold_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTailDropThreshold_0,
      "CfgTailDropThreshold_0",
      AD_CfgTailDropThreshold_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTailDropThreshold_1,
      "CfgTailDropThreshold_1",
      AD_CfgTailDropThreshold_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTailDropThreshold_2,
      "CfgTailDropThreshold_2",
      AD_CfgTailDropThreshold_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTailDropThreshold_3,
      "CfgTailDropThreshold_3",
      AD_CfgTailDropThreshold_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTailDropThreshold_4,
      "CfgTailDropThreshold_4",
      AD_CfgTailDropThreshold_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTailDropThreshold_5,
      "CfgTailDropThreshold_5",
      AD_CfgTailDropThreshold_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTailDropThreshold_6,
      "CfgTailDropThreshold_6",
      AD_CfgTailDropThreshold_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTailDropThreshold_7,
      "CfgTailDropThreshold_7",
      AD_CfgTailDropThreshold_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgFctQ_0,
      "CfgWREDAvgFctQ_0",
      AD_CfgWREDAvgFctQ_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgFctQ_1,
      "CfgWREDAvgFctQ_1",
      AD_CfgWREDAvgFctQ_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgFctQ_2,
      "CfgWREDAvgFctQ_2",
      AD_CfgWREDAvgFctQ_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgFctQ_3,
      "CfgWREDAvgFctQ_3",
      AD_CfgWREDAvgFctQ_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgFctQ_4,
      "CfgWREDAvgFctQ_4",
      AD_CfgWREDAvgFctQ_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgFctQ_5,
      "CfgWREDAvgFctQ_5",
      AD_CfgWREDAvgFctQ_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgFctQ_6,
      "CfgWREDAvgFctQ_6",
      AD_CfgWREDAvgFctQ_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgFctQ_7,
      "CfgWREDAvgFctQ_7",
      AD_CfgWREDAvgFctQ_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTimerBasedAvgLenEn,
      "CfgTimerBasedAvgLenEn",
      AD_CfgTimerBasedAvgLenEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgQSizeTimer_0,
      "CfgWREDAvgQSizeTimer_0",
      AD_CfgWREDAvgQSizeTimer_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgQSizeTimer_1,
      "CfgWREDAvgQSizeTimer_1",
      AD_CfgWREDAvgQSizeTimer_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgQSizeTimer_2,
      "CfgWREDAvgQSizeTimer_2",
      AD_CfgWREDAvgQSizeTimer_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgQSizeTimer_3,
      "CfgWREDAvgQSizeTimer_3",
      AD_CfgWREDAvgQSizeTimer_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgQSizeTimer_4,
      "CfgWREDAvgQSizeTimer_4",
      AD_CfgWREDAvgQSizeTimer_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgQSizeTimer_5,
      "CfgWREDAvgQSizeTimer_5",
      AD_CfgWREDAvgQSizeTimer_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgQSizeTimer_6,
      "CfgWREDAvgQSizeTimer_6",
      AD_CfgWREDAvgQSizeTimer_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDAvgQSizeTimer_7,
      "CfgWREDAvgQSizeTimer_7",
      AD_CfgWREDAvgQSizeTimer_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDProbabilityTable,
      "CfgWREDProbabilityTable",
      AD_CfgWREDProbabilityTable, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDProbabilityTable__REn,
      "CfgWREDProbabilityTable__REn",
      AD_CfgWREDProbabilityTable, 14, 14, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDProbabilityTable__WEn,
      "CfgWREDProbabilityTable__WEn",
      AD_CfgWREDProbabilityTable, 13, 13, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDProbabilityTable__QueueID,
      "CfgWREDProbabilityTable__QueueID",
      AD_CfgWREDProbabilityTable, 12, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDProbabilityTable__Pointer,
      "CfgWREDProbabilityTable__Pointer",
      AD_CfgWREDProbabilityTable, 9, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDDropProbability,
      "CfgWREDDropProbability",
      AD_CfgWREDDropProbability, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsWREDDropProbability,
      "StsWREDDropProbability",
      AD_StsWREDDropProbability, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDGreenThreshold,
      "CfgWREDGreenThreshold",
      AD_CfgWREDGreenThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDYellowThreshold,
      "CfgWREDYellowThreshold",
      AD_CfgWREDYellowThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDOrangeThreshold,
      "CfgWREDOrangeThreshold",
      AD_CfgWREDOrangeThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWREDRedThreshold,
      "CfgWREDRedThreshold",
      AD_CfgWREDRedThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsWREDDrop_0,
      "StsWREDDrop_0",
      AD_StsWREDDrop_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsWREDDrop_1,
      "StsWREDDrop_1",
      AD_StsWREDDrop_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsWREDDrop_2,
      "StsWREDDrop_2",
      AD_StsWREDDrop_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsWREDDrop_3,
      "StsWREDDrop_3",
      AD_StsWREDDrop_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsWREDDrop_4,
      "StsWREDDrop_4",
      AD_StsWREDDrop_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsWREDDrop_5,
      "StsWREDDrop_5",
      AD_StsWREDDrop_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsWREDDrop_6,
      "StsWREDDrop_6",
      AD_StsWREDDrop_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsWREDDrop_7,
      "StsWREDDrop_7",
      AD_StsWREDDrop_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsBPDUDrop_0,
      "StsBPDUDrop_0",
      AD_StsBPDUDrop_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsBPDUDrop_1,
      "StsBPDUDrop_1",
      AD_StsBPDUDrop_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsBPDUDrop_2,
      "StsBPDUDrop_2",
      AD_StsBPDUDrop_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsBPDUDrop_3,
      "StsBPDUDrop_3",
      AD_StsBPDUDrop_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsBPDUDrop_4,
      "StsBPDUDrop_4",
      AD_StsBPDUDrop_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsBPDUDrop_5,
      "StsBPDUDrop_5",
      AD_StsBPDUDrop_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsBPDUDrop_6,
      "StsBPDUDrop_6",
      AD_StsBPDUDrop_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsBPDUDrop_7,
      "StsBPDUDrop_7",
      AD_StsBPDUDrop_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTailDrop_0,
      "StsTailDrop_0",
      AD_StsTailDrop_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTailDrop_1,
      "StsTailDrop_1",
      AD_StsTailDrop_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTailDrop_2,
      "StsTailDrop_2",
      AD_StsTailDrop_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTailDrop_3,
      "StsTailDrop_3",
      AD_StsTailDrop_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTailDrop_4,
      "StsTailDrop_4",
      AD_StsTailDrop_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTailDrop_5,
      "StsTailDrop_5",
      AD_StsTailDrop_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTailDrop_6,
      "StsTailDrop_6",
      AD_StsTailDrop_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTailDrop_7,
      "StsTailDrop_7",
      AD_StsTailDrop_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsGreenColorMark_0,
      "StsGreenColorMark_0",
      AD_StsGreenColorMark_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsGreenColorMark_1,
      "StsGreenColorMark_1",
      AD_StsGreenColorMark_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsGreenColorMark_2,
      "StsGreenColorMark_2",
      AD_StsGreenColorMark_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsGreenColorMark_3,
      "StsGreenColorMark_3",
      AD_StsGreenColorMark_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsGreenColorMark_4,
      "StsGreenColorMark_4",
      AD_StsGreenColorMark_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsGreenColorMark_5,
      "StsGreenColorMark_5",
      AD_StsGreenColorMark_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsGreenColorMark_6,
      "StsGreenColorMark_6",
      AD_StsGreenColorMark_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsGreenColorMark_7,
      "StsGreenColorMark_7",
      AD_StsGreenColorMark_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsYelloColorMark_0,
      "StsYelloColorMark_0",
      AD_StsYelloColorMark_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsYelloColorMark_1,
      "StsYelloColorMark_1",
      AD_StsYelloColorMark_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsYelloColorMark_2,
      "StsYelloColorMark_2",
      AD_StsYelloColorMark_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsYelloColorMark_3,
      "StsYelloColorMark_3",
      AD_StsYelloColorMark_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsYelloColorMark_4,
      "StsYelloColorMark_4",
      AD_StsYelloColorMark_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsYelloColorMark_5,
      "StsYelloColorMark_5",
      AD_StsYelloColorMark_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsYelloColorMark_6,
      "StsYelloColorMark_6",
      AD_StsYelloColorMark_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsYelloColorMark_7,
      "StsYelloColorMark_7",
      AD_StsYelloColorMark_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOrangeColorMark_0,
      "StsOrangeColorMark_0",
      AD_StsOrangeColorMark_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOrangeColorMark_1,
      "StsOrangeColorMark_1",
      AD_StsOrangeColorMark_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOrangeColorMark_2,
      "StsOrangeColorMark_2",
      AD_StsOrangeColorMark_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOrangeColorMark_3,
      "StsOrangeColorMark_3",
      AD_StsOrangeColorMark_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOrangeColorMark_4,
      "StsOrangeColorMark_4",
      AD_StsOrangeColorMark_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOrangeColorMark_5,
      "StsOrangeColorMark_5",
      AD_StsOrangeColorMark_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOrangeColorMark_6,
      "StsOrangeColorMark_6",
      AD_StsOrangeColorMark_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsOrangeColorMark_7,
      "StsOrangeColorMark_7",
      AD_StsOrangeColorMark_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsColorRedMark_0,
      "StsColorRedMark_0",
      AD_StsColorRedMark_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsColorRedMark_1,
      "StsColorRedMark_1",
      AD_StsColorRedMark_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsColorRedMark_2,
      "StsColorRedMark_2",
      AD_StsColorRedMark_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsColorRedMark_3,
      "StsColorRedMark_3",
      AD_StsColorRedMark_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsColorRedMark_4,
      "StsColorRedMark_4",
      AD_StsColorRedMark_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsColorRedMark_5,
      "StsColorRedMark_5",
      AD_StsColorRedMark_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsColorRedMark_6,
      "StsColorRedMark_6",
      AD_StsColorRedMark_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsColorRedMark_7,
      "StsColorRedMark_7",
      AD_StsColorRedMark_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExCongMark_0,
      "StsExCongMark_0",
      AD_StsExCongMark_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExCongMark_1,
      "StsExCongMark_1",
      AD_StsExCongMark_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExCongMark_2,
      "StsExCongMark_2",
      AD_StsExCongMark_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExCongMark_3,
      "StsExCongMark_3",
      AD_StsExCongMark_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExCongMark_4,
      "StsExCongMark_4",
      AD_StsExCongMark_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExCongMark_5,
      "StsExCongMark_5",
      AD_StsExCongMark_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExCongMark_6,
      "StsExCongMark_6",
      AD_StsExCongMark_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExCongMark_7,
      "StsExCongMark_7",
      AD_StsExCongMark_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEopCount,
      "StsEopCount",
      AD_StsEopCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgEccCheckEn,
      "CfgEccCheckEn",
      AD_CfgEccCheckEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgInsertEccErrorMode,
      "CfgInsertEccErrorMode",
      AD_CfgInsertEccErrorMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEccErrorInterrupt,
      "StsEccErrorInterrupt",
      AD_StsEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEccErrorInterruptMask,
      "StsEccErrorInterruptMask",
      AD_StsEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEccSingleErrorInterrupt,
      "StsEccSingleErrorInterrupt",
      AD_StsEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEccSingleErrorInterruptMask,
      "StsEccSingleErrorInterruptMask",
      AD_StsEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEccDoubleErrorInterrupt,
      "StsEccDoubleErrorInterrupt",
      AD_StsEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEccDoubleErrorInterruptMask,
      "StsEccDoubleErrorInterruptMask",
      AD_StsEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg0,
      "StsLineToCpuDataReg0",
      AD_StsLineToCpuDataReg0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg1,
      "StsLineToCpuDataReg1",
      AD_StsLineToCpuDataReg1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg2,
      "StsLineToCpuDataReg2",
      AD_StsLineToCpuDataReg2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg3,
      "StsLineToCpuDataReg3",
      AD_StsLineToCpuDataReg3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg4,
      "StsLineToCpuDataReg4",
      AD_StsLineToCpuDataReg4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg5,
      "StsLineToCpuDataReg5",
      AD_StsLineToCpuDataReg5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg6,
      "StsLineToCpuDataReg6",
      AD_StsLineToCpuDataReg6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg7,
      "StsLineToCpuDataReg7",
      AD_StsLineToCpuDataReg7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg8,
      "StsLineToCpuDataReg8",
      AD_StsLineToCpuDataReg8, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg9,
      "StsLineToCpuDataReg9",
      AD_StsLineToCpuDataReg9, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg10,
      "StsLineToCpuDataReg10",
      AD_StsLineToCpuDataReg10, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg11,
      "StsLineToCpuDataReg11",
      AD_StsLineToCpuDataReg11, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDataReg12,
      "StsLineToCpuDataReg12",
      AD_StsLineToCpuDataReg12, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineRegDataVld,
      "StsLineRegDataVld",
      AD_StsLineRegDataVld, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuFifoFull,
      "StsLineToCpuFifoFull",
      AD_StsLineToCpuFifoFull, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuFifoEmpty,
      "StsLineToCpuFifoEmpty",
      AD_StsLineToCpuFifoEmpty, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuFifoNearlyFull,
      "StsLineToCpuFifoNearlyFull",
      AD_StsLineToCpuFifoNearlyFull, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuFifoNearlyEmpty,
      "StsLineToCpuFifoNearlyEmpty",
      AD_StsLineToCpuFifoNearlyEmpty, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuFullPacketMode,
      "CfgLineToCpuFullPacketMode",
      AD_CfgLineToCpuFullPacketMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDisableRead,
      "CfgLineToCpuDisableRead",
      AD_CfgLineToCpuDisableRead, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuNearFullThresh,
      "CfgLineToCpuNearFullThresh",
      AD_CfgLineToCpuNearFullThresh, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuNearEmptyThresh,
      "CfgLineToCpuNearEmptyThresh",
      AD_CfgLineToCpuNearEmptyThresh, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA0LSB,
      "CfgLineToCpuDA0LSB",
      AD_CfgLineToCpuDA0LSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA0MSB,
      "CfgLineToCpuDA0MSB",
      AD_CfgLineToCpuDA0MSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA1LSB,
      "CfgLineToCpuDA1LSB",
      AD_CfgLineToCpuDA1LSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA1MSB,
      "CfgLineToCpuDA1MSB",
      AD_CfgLineToCpuDA1MSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA2LSB,
      "CfgLineToCpuDA2LSB",
      AD_CfgLineToCpuDA2LSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA2MSB,
      "CfgLineToCpuDA2MSB",
      AD_CfgLineToCpuDA2MSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA3LSB,
      "CfgLineToCpuDA3LSB",
      AD_CfgLineToCpuDA3LSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA3MSB,
      "CfgLineToCpuDA3MSB",
      AD_CfgLineToCpuDA3MSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA0MaskLSB,
      "CfgLineToCpuDA0MaskLSB",
      AD_CfgLineToCpuDA0MaskLSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA0MaskMSB,
      "CfgLineToCpuDA0MaskMSB",
      AD_CfgLineToCpuDA0MaskMSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA1MaskLSB,
      "CfgLineToCpuDA1MaskLSB",
      AD_CfgLineToCpuDA1MaskLSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA1MaskMSB,
      "CfgLineToCpuDA1MaskMSB",
      AD_CfgLineToCpuDA1MaskMSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA2MaskLSB,
      "CfgLineToCpuDA2MaskLSB",
      AD_CfgLineToCpuDA2MaskLSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA2MaskMSB,
      "CfgLineToCpuDA2MaskMSB",
      AD_CfgLineToCpuDA2MaskMSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA3MaskLSB,
      "CfgLineToCpuDA3MaskLSB",
      AD_CfgLineToCpuDA3MaskLSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDA3MaskMSB,
      "CfgLineToCpuDA3MaskMSB",
      AD_CfgLineToCpuDA3MaskMSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuEccChkDis,
      "CfgLineToCpuEccChkDis",
      AD_CfgLineToCpuEccChkDis, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuDropEn,
      "CfgLineToCpuDropEn",
      AD_CfgLineToCpuDropEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUWritePointer,
      "StsLineToCPUWritePointer",
      AD_StsLineToCPUWritePointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUReadPointer,
      "StsLineToCPUReadPointer",
      AD_StsLineToCPUReadPointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUCommitPointer,
      "StsLineToCPUCommitPointer",
      AD_StsLineToCPUCommitPointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUFifoFullInterrupt,
      "StsLineToCPUFifoFullInterrupt",
      AD_StsLineToCPUFifoFullInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUFifoFullInterruptMask,
      "StsLineToCPUFifoFullInterruptMask",
      AD_StsLineToCPUFifoFullInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUFifoEmptyInterrupt,
      "StsLineToCPUFifoEmptyInterrupt",
      AD_StsLineToCPUFifoEmptyInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUFifoEmptyInterruptMask,
      "StsLineToCPUFifoEmptyInterruptMask",
      AD_StsLineToCPUFifoEmptyInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUFifoDataInterrupt,
      "StsLineToCPUFifoDataInterrupt",
      AD_StsLineToCPUFifoDataInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUFifoDataInterruptMask,
      "StsLineToCPUFifoDataInterruptMask",
      AD_StsLineToCPUFifoDataInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCPUReadOnThresh,
      "CfgLineToCPUReadOnThresh",
      AD_CfgLineToCPUReadOnThresh, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCPUReadOffThresh,
      "CfgLineToCPUReadOffThresh",
      AD_CfgLineToCPUReadOffThresh, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUEccErrorInterrupt,
      "StsLineToCPUEccErrorInterrupt",
      AD_StsLineToCPUEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUEccErrorInterruptMask,
      "StsLineToCPUEccErrorInterruptMask",
      AD_StsLineToCPUEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUEccSingleErrorInterrupt,
      "StsLineToCPUEccSingleErrorInterrupt",
      AD_StsLineToCPUEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUEccSingleErrorInterruptMask,
      "StsLineToCPUEccSingleErrorInterruptMask",
      AD_StsLineToCPUEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUEccDoubleErrorInterrupt,
      "StsLineToCPUEccDoubleErrorInterrupt",
      AD_StsLineToCPUEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUEccDoubleErrorInterruptMask,
      "StsLineToCPUEccDoubleErrorInterruptMask",
      AD_StsLineToCPUEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuFifoTailDropEn,
      "CfgLineToCpuFifoTailDropEn",
      AD_CfgLineToCpuFifoTailDropEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuPktDropEn,
      "CfgLineToCpuPktDropEn",
      AD_CfgLineToCpuPktDropEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgLineToCpuReadTimerValue,
      "CfgLineToCpuReadTimerValue",
      AD_CfgLineToCpuReadTimerValue, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCpuDropPktCnt,
      "StsLineToCpuDropPktCnt",
      AD_StsLineToCpuDropPktCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUFifoUnderrunInterrupt,
      "StsLineToCPUFifoUnderrunInterrupt",
      AD_StsLineToCPUFifoUnderrunInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsLineToCPUFifoUnderrunInterruptMask,
      "StsLineToCPUFifoUnderrunInterruptMask",
      AD_StsLineToCPUFifoUnderrunInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBurstSize,
      "CfgBurstSize",
      AD_CfgBurstSize, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBurstSize__ReadDisable,
      "CfgBurstSize__ReadDisable",
      AD_CfgBurstSize, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgBurstSize__BurstSize,
      "CfgBurstSize__BurstSize",
      AD_CfgBurstSize, 4, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemAccessCommand,
      "CfgIntMemAccessCommand",
      AD_CfgIntMemAccessCommand, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemAccessCommand__Address,
      "CfgIntMemAccessCommand__Address",
      AD_CfgIntMemAccessCommand, 13, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemAccessCommand__RdWr,
      "CfgIntMemAccessCommand__RdWr",
      AD_CfgIntMemAccessCommand, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemData_0,
      "CfgIntMemData_0",
      AD_CfgIntMemData_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemData_1,
      "CfgIntMemData_1",
      AD_CfgIntMemData_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemData_2,
      "CfgIntMemData_2",
      AD_CfgIntMemData_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemData_3,
      "CfgIntMemData_3",
      AD_CfgIntMemData_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemData_4,
      "CfgIntMemData_4",
      AD_CfgIntMemData_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemData_5,
      "CfgIntMemData_5",
      AD_CfgIntMemData_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemData_6,
      "CfgIntMemData_6",
      AD_CfgIntMemData_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgIntMemData_7,
      "CfgIntMemData_7",
      AD_CfgIntMemData_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIntMemData_0,
      "StsIntMemData_0",
      AD_StsIntMemData_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIntMemData_1,
      "StsIntMemData_1",
      AD_StsIntMemData_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIntMemData_2,
      "StsIntMemData_2",
      AD_StsIntMemData_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIntMemData_3,
      "StsIntMemData_3",
      AD_StsIntMemData_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIntMemData_4,
      "StsIntMemData_4",
      AD_StsIntMemData_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIntMemData_5,
      "StsIntMemData_5",
      AD_StsIntMemData_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIntMemData_6,
      "StsIntMemData_6",
      AD_StsIntMemData_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIntMemData_7,
      "StsIntMemData_7",
      AD_StsIntMemData_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIntMemCurrentRdAddress,
      "StsIntMemCurrentRdAddress",
      AD_StsIntMemCurrentRdAddress, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsIntMemCurrentWrAddress,
      "StsIntMemCurrentWrAddress",
      AD_StsIntMemCurrentWrAddress, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDMECCErrorMode,
      "CfgDMECCErrorMode",
      AD_CfgDMECCErrorMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDMDisableEccCheck,
      "CfgDMDisableEccCheck",
      AD_CfgDMDisableEccCheck, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDMEccErrorInterrupt,
      "StsDMEccErrorInterrupt",
      AD_StsDMEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDMEccErrorInterruptMask,
      "StsDMEccErrorInterruptMask",
      AD_StsDMEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDMEccSingleErrorInterrupt,
      "StsDMEccSingleErrorInterrupt",
      AD_StsDMEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDMEccSingleErrorInterruptMask,
      "StsDMEccSingleErrorInterruptMask",
      AD_StsDMEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDMEccDoubleErrorInterrupt,
      "StsDMEccDoubleErrorInterrupt",
      AD_StsDMEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDMEccDoubleErrorInterruptMask,
      "StsDMEccDoubleErrorInterruptMask",
      AD_StsDMEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqIgrPktCnt,
      "StsEnqIgrPktCnt",
      AD_StsEnqIgrPktCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqEgrPktCnt,
      "StsEnqEgrPktCnt",
      AD_StsEnqEgrPktCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDropPktCnt,
      "StsEnqDropPktCnt",
      AD_StsEnqDropPktCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDropPktCntQNum0,
      "StsEnqDropPktCntQNum0",
      AD_StsEnqDropPktCntQNum0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDropPktCntQNum1,
      "StsEnqDropPktCntQNum1",
      AD_StsEnqDropPktCntQNum1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDropPktCntQNum2,
      "StsEnqDropPktCntQNum2",
      AD_StsEnqDropPktCntQNum2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDropPktCntQNum3,
      "StsEnqDropPktCntQNum3",
      AD_StsEnqDropPktCntQNum3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDropPktCntQNum4,
      "StsEnqDropPktCntQNum4",
      AD_StsEnqDropPktCntQNum4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDropPktCntQNum5,
      "StsEnqDropPktCntQNum5",
      AD_StsEnqDropPktCntQNum5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDropPktCntQNum6,
      "StsEnqDropPktCntQNum6",
      AD_StsEnqDropPktCntQNum6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDropPktCntQNum7,
      "StsEnqDropPktCntQNum7",
      AD_StsEnqDropPktCntQNum7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqSequenceErrInterrupt,
      "StsEnqSequenceErrInterrupt",
      AD_StsEnqSequenceErrInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqSequenceErrInterruptMask,
      "StsEnqSequenceErrInterruptMask",
      AD_StsEnqSequenceErrInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDFifoOverflowInterrupt,
      "StsEnqDFifoOverflowInterrupt",
      AD_StsEnqDFifoOverflowInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqDFifoOverflowInterruptMask,
      "StsEnqDFifoOverflowInterruptMask",
      AD_StsEnqDFifoOverflowInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqSzLstFifoOverflowInterrupt,
      "StsEnqSzLstFifoOverflowInterrupt",
      AD_StsEnqSzLstFifoOverflowInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEnqSzLstFifoOverflowInterruptMask,
      "StsEnqSzLstFifoOverflowInterruptMask",
      AD_StsEnqSzLstFifoOverflowInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgInitFCRAM,
      "CfgInitFCRAM",
      AD_CfgInitFCRAM, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgInitFCRAM__DoneCount,
      "CfgInitFCRAM__DoneCount",
      AD_CfgInitFCRAM, 31, 24, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgInitFCRAM__REF2Count,
      "CfgInitFCRAM__REF2Count",
      AD_CfgInitFCRAM, 23, 18, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgInitFCRAM__REF1Count,
      "CfgInitFCRAM__REF1Count",
      AD_CfgInitFCRAM, 17, 12, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgInitFCRAM__MRSCount,
      "CfgInitFCRAM__MRSCount",
      AD_CfgInitFCRAM, 11, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgInitFCRAM__IdleCount,
      "CfgInitFCRAM__IdleCount",
      AD_CfgInitFCRAM, 5, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgInitEMSAddr,
      "CfgInitEMSAddr",
      AD_CfgInitEMSAddr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgInitMRSAddr,
      "CfgInitMRSAddr",
      AD_CfgInitMRSAddr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgBankTrc,
      "CfgBankTrc",
      AD_CfgBankTrc, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRefreshDiv,
      "CfgRefreshDiv",
      AD_CfgRefreshDiv, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMemAccessCommand,
      "CfgMemAccessCommand",
      AD_CfgMemAccessCommand, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMemAccessCommand__Address,
      "CfgMemAccessCommand__Address",
      AD_CfgMemAccessCommand, 24, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMemAccessCommand__BankAddr,
      "CfgMemAccessCommand__BankAddr",
      AD_CfgMemAccessCommand, 2, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMemAccessCommand__RdWr,
      "CfgMemAccessCommand__RdWr",
      AD_CfgMemAccessCommand, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgExtMemData_0,
      "CfgExtMemData_0",
      AD_CfgExtMemData_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgExtMemData_1,
      "CfgExtMemData_1",
      AD_CfgExtMemData_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgExtMemData_2,
      "CfgExtMemData_2",
      AD_CfgExtMemData_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgExtMemData_3,
      "CfgExtMemData_3",
      AD_CfgExtMemData_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgExtMemData_4,
      "CfgExtMemData_4",
      AD_CfgExtMemData_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgExtMemData_5,
      "CfgExtMemData_5",
      AD_CfgExtMemData_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgExtMemData_6,
      "CfgExtMemData_6",
      AD_CfgExtMemData_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgExtMemData_7,
      "CfgExtMemData_7",
      AD_CfgExtMemData_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExtMemData_0,
      "StsExtMemData_0",
      AD_StsExtMemData_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExtMemData_1,
      "StsExtMemData_1",
      AD_StsExtMemData_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExtMemData_2,
      "StsExtMemData_2",
      AD_StsExtMemData_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExtMemData_3,
      "StsExtMemData_3",
      AD_StsExtMemData_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExtMemData_4,
      "StsExtMemData_4",
      AD_StsExtMemData_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExtMemData_5,
      "StsExtMemData_5",
      AD_StsExtMemData_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExtMemData_6,
      "StsExtMemData_6",
      AD_StsExtMemData_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExtMemData_7,
      "StsExtMemData_7",
      AD_StsExtMemData_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExtMemCurrentRdAddress,
      "StsExtMemCurrentRdAddress",
      AD_StsExtMemCurrentRdAddress, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsExtMemCurrentWrAddress,
      "StsExtMemCurrentWrAddress",
      AD_StsExtMemCurrentWrAddress, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsInitFCRAM,
      "StsInitFCRAM",
      AD_StsInitFCRAM, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMemAccessInterrupt,
      "StsMemAccessInterrupt",
      AD_StsMemAccessInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMemAccessInterruptMask,
      "StsMemAccessInterruptMask",
      AD_StsMemAccessInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgFreePageTableInit,
      "CfgFreePageTableInit",
      AD_CfgFreePageTableInit, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsFreePageTableInitDone,
      "StsFreePageTableInitDone",
      AD_StsFreePageTableInitDone, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgQueueManagerReadDisable,
      "CfgQueueManagerReadDisable",
      AD_CfgQueueManagerReadDisable, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgPageFullPntr,
      "CfgPageFullPntr",
      AD_CfgPageFullPntr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgQueueManagerEnable,
      "CfgQueueManagerEnable",
      AD_CfgQueueManagerEnable, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgQueueManagerEnable__MaxPageCountWrEn,
      "CfgQueueManagerEnable__MaxPageCountWrEn",
      AD_CfgQueueManagerEnable, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgQueueManagerEnable__MaxPageCountRdEn,
      "CfgQueueManagerEnable__MaxPageCountRdEn",
      AD_CfgQueueManagerEnable, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgQueueManagerEnable__RsvdPageCountWrEn,
      "CfgQueueManagerEnable__RsvdPageCountWrEn",
      AD_CfgQueueManagerEnable, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgQueueManagerEnable__RsvdPageCountRdEn,
      "CfgQueueManagerEnable__RsvdPageCountRdEn",
      AD_CfgQueueManagerEnable, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgQueueManagerEnable__UsedPageCountRdEn,
      "CfgQueueManagerEnable__UsedPageCountRdEn",
      AD_CfgQueueManagerEnable, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgQueueManagerEnable__QueueFillReadEn,
      "CfgQueueManagerEnable__QueueFillReadEn",
      AD_CfgQueueManagerEnable, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMaxPageCountWrQnum,
      "CfgMaxPageCountWrQnum",
      AD_CfgMaxPageCountWrQnum, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMaxPageCountWr,
      "CfgMaxPageCountWr",
      AD_CfgMaxPageCountWr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMaxPageCountRdQnum,
      "CfgMaxPageCountRdQnum",
      AD_CfgMaxPageCountRdQnum, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMaxPageCountRd,
      "StsMaxPageCountRd",
      AD_StsMaxPageCountRd, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRsvdPageCountWrQnum,
      "CfgRsvdPageCountWrQnum",
      AD_CfgRsvdPageCountWrQnum, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRsvdPageCountWr,
      "CfgRsvdPageCountWr",
      AD_CfgRsvdPageCountWr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTotalRsvdPageCount,
      "CfgTotalRsvdPageCount",
      AD_CfgTotalRsvdPageCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRsvdPageCountRdQnum,
      "CfgRsvdPageCountRdQnum",
      AD_CfgRsvdPageCountRdQnum, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRsvdPageCountRd,
      "StsRsvdPageCountRd",
      AD_StsRsvdPageCountRd, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgUsedPageCountRdQnum,
      "CfgUsedPageCountRdQnum",
      AD_CfgUsedPageCountRdQnum, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsUsedPageCountRd,
      "StsUsedPageCountRd",
      AD_StsUsedPageCountRd, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgStartRsvdPoolPagePntr,
      "CfgStartRsvdPoolPagePntr",
      AD_CfgStartRsvdPoolPagePntr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgStartFreePoolPagePntr,
      "CfgStartFreePoolPagePntr",
      AD_CfgStartFreePoolPagePntr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRsvdPoolPagePntr,
      "StsRsvdPoolPagePntr",
      AD_StsRsvdPoolPagePntr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsFreePoolPagePntr,
      "StsFreePoolPagePntr",
      AD_StsFreePoolPagePntr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMemoryFullCount,
      "StsMemoryFullCount",
      AD_StsMemoryFullCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgQueueFillReadQnum,
      "CfgQueueFillReadQnum",
      AD_CfgQueueFillReadQnum, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQueueFillLevel,
      "StsQueueFillLevel",
      AD_StsQueueFillLevel, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTotalRsvdPageCountInterrupt,
      "StsTotalRsvdPageCountInterrupt",
      AD_StsTotalRsvdPageCountInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTotalRsvdPageCountInterruptMask,
      "StsTotalRsvdPageCountInterruptMask",
      AD_StsTotalRsvdPageCountInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsPageFifoOverflowInterrupt,
      "StsPageFifoOverflowInterrupt",
      AD_StsPageFifoOverflowInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsPageFifoOverflowInterruptMask,
      "StsPageFifoOverflowInterruptMask",
      AD_StsPageFifoOverflowInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgPauseFrameOnThreshold,
      "CfgPauseFrameOnThreshold",
      AD_CfgPauseFrameOnThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgPauseFrameOffThreshold,
      "CfgPauseFrameOffThreshold",
      AD_CfgPauseFrameOffThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgQmFptDisableEccCheck,
      "CfgQmFptDisableEccCheck",
      AD_CfgQmFptDisableEccCheck, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgQmPltDisableEccCheck,
      "CfgQmPltDisableEccCheck",
      AD_CfgQmPltDisableEccCheck, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmFptEccErrorInterrupt,
      "StsQmFptEccErrorInterrupt",
      AD_StsQmFptEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmFptEccErrorInterruptMask,
      "StsQmFptEccErrorInterruptMask",
      AD_StsQmFptEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmFptEccSingleErrorInterrupt,
      "StsQmFptEccSingleErrorInterrupt",
      AD_StsQmFptEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmFptEccSingleErrorInterruptMask,
      "StsQmFptEccSingleErrorInterruptMask",
      AD_StsQmFptEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmFptEccDoubleErrorInterrupt,
      "StsQmFptEccDoubleErrorInterrupt",
      AD_StsQmFptEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmFptEccDoubleErrorInterruptMask,
      "StsQmFptEccDoubleErrorInterruptMask",
      AD_StsQmFptEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmPltEccErrorInterrupt,
      "StsQmPltEccErrorInterrupt",
      AD_StsQmPltEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmPltEccErrorInterruptMask,
      "StsQmPltEccErrorInterruptMask",
      AD_StsQmPltEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmPltEccSingleErrorInterrupt,
      "StsQmPltEccSingleErrorInterrupt",
      AD_StsQmPltEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmPltEccSingleErrorInterruptMask,
      "StsQmPltEccSingleErrorInterruptMask",
      AD_StsQmPltEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmPltEccDoubleErrorInterrupt,
      "StsQmPltEccDoubleErrorInterrupt",
      AD_StsQmPltEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsQmPltEccDoubleErrorInterruptMask,
      "StsQmPltEccDoubleErrorInterruptMask",
      AD_StsQmPltEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrCreditQ0,
      "CfgDeqMdrrCreditQ0",
      AD_CfgDeqMdrrCreditQ0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrCreditQ1,
      "CfgDeqMdrrCreditQ1",
      AD_CfgDeqMdrrCreditQ1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrCreditQ2,
      "CfgDeqMdrrCreditQ2",
      AD_CfgDeqMdrrCreditQ2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrCreditQ3,
      "CfgDeqMdrrCreditQ3",
      AD_CfgDeqMdrrCreditQ3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrCreditQ4,
      "CfgDeqMdrrCreditQ4",
      AD_CfgDeqMdrrCreditQ4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrCreditQ5,
      "CfgDeqMdrrCreditQ5",
      AD_CfgDeqMdrrCreditQ5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrCreditQ6,
      "CfgDeqMdrrCreditQ6",
      AD_CfgDeqMdrrCreditQ6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrCreditQ7,
      "CfgDeqMdrrCreditQ7",
      AD_CfgDeqMdrrCreditQ7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrStrictPriorityMode,
      "CfgDeqMdrrStrictPriorityMode",
      AD_CfgDeqMdrrStrictPriorityMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrStrictPriorityMode__Q7Q6AlternateStrictPriority,
      "CfgDeqMdrrStrictPriorityMode__Q7Q6AlternateStrictPriority",
      AD_CfgDeqMdrrStrictPriorityMode, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrStrictPriorityMode__Q7Q6StrictPriority,
      "CfgDeqMdrrStrictPriorityMode__Q7Q6StrictPriority",
      AD_CfgDeqMdrrStrictPriorityMode, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMdrrStrictPriorityMode__Q7StrictPriority,
      "CfgDeqMdrrStrictPriorityMode__Q7StrictPriority",
      AD_CfgDeqMdrrStrictPriorityMode, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqFullPacketMode,
      "CfgDeqFullPacketMode",
      AD_CfgDeqFullPacketMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqReadOnThreshold,
      "CfgDeqReadOnThreshold",
      AD_CfgDeqReadOnThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqReadOffThreshold,
      "CfgDeqReadOffThreshold",
      AD_CfgDeqReadOffThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqReadTimerValue,
      "CfgDeqReadTimerValue",
      AD_CfgDeqReadTimerValue, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqDisableRead,
      "CfgDeqDisableRead",
      AD_CfgDeqDisableRead, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqDisableRead__Reserved,
      "CfgDeqDisableRead__Reserved",
      AD_CfgDeqDisableRead, 15, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqDisableRead__DisableRead,
      "CfgDeqDisableRead__DisableRead",
      AD_CfgDeqDisableRead, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqDisableDrop,
      "CfgDeqDisableDrop",
      AD_CfgDeqDisableDrop, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqTailDropEn,
      "CfgDeqTailDropEn",
      AD_CfgDeqTailDropEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqTailDropCount,
      "StsDeqTailDropCount",
      AD_StsDeqTailDropCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqDisableEccCheck,
      "CfgDeqDisableEccCheck",
      AD_CfgDeqDisableEccCheck, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqLoopbackMode,
      "CfgDeqLoopbackMode",
      AD_CfgDeqLoopbackMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqLoopbackMode__LoopbackMode2,
      "CfgDeqLoopbackMode__LoopbackMode2",
      AD_CfgDeqLoopbackMode, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqLoopbackMode__LoopbackMode1,
      "CfgDeqLoopbackMode__LoopbackMode1",
      AD_CfgDeqLoopbackMode, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqLoopbackMode__LoopbackMode0,
      "CfgDeqLoopbackMode__LoopbackMode0",
      AD_CfgDeqLoopbackMode, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqLoopbackVlan0,
      "CfgDeqLoopbackVlan0",
      AD_CfgDeqLoopbackVlan0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqLoopbackVlan1,
      "CfgDeqLoopbackVlan1",
      AD_CfgDeqLoopbackVlan1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqLoopbackVlan2,
      "CfgDeqLoopbackVlan2",
      AD_CfgDeqLoopbackVlan2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqLoopbackVlan3,
      "CfgDeqLoopbackVlan3",
      AD_CfgDeqLoopbackVlan3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqLpbkEgressHeader0,
      "CfgDeqLpbkEgressHeader0",
      AD_CfgDeqLpbkEgressHeader0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqLpbkEgressHeader1,
      "CfgDeqLpbkEgressHeader1",
      AD_CfgDeqLpbkEgressHeader1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqTimeStampControl,
      "CfgDeqTimeStampControl",
      AD_CfgDeqTimeStampControl, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqTimeStampControl__TimeStampUnit,
      "CfgDeqTimeStampControl__TimeStampUnit",
      AD_CfgDeqTimeStampControl, 3, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqTimeStampControl__TimeStampRun,
      "CfgDeqTimeStampControl__TimeStampRun",
      AD_CfgDeqTimeStampControl, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqTimeStampControl__TimeStampEnable,
      "CfgDeqTimeStampControl__TimeStampEnable",
      AD_CfgDeqTimeStampControl, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqExcessLatencyControl0,
      "CfgDeqExcessLatencyControl0",
      AD_CfgDeqExcessLatencyControl0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqExcessLatencyControl0__DeltaTime,
      "CfgDeqExcessLatencyControl0__DeltaTime",
      AD_CfgDeqExcessLatencyControl0, 9, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqExcessLatencyControl0__Discard,
      "CfgDeqExcessLatencyControl0__Discard",
      AD_CfgDeqExcessLatencyControl0, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqExcessLatencyControl0__Enable,
      "CfgDeqExcessLatencyControl0__Enable",
      AD_CfgDeqExcessLatencyControl0, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqExcessLatencyControl1,
      "CfgDeqExcessLatencyControl1",
      AD_CfgDeqExcessLatencyControl1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqExcessLatencyControl1__DeltaTime,
      "CfgDeqExcessLatencyControl1__DeltaTime",
      AD_CfgDeqExcessLatencyControl1, 9, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqExcessLatencyControl1__Discard,
      "CfgDeqExcessLatencyControl1__Discard",
      AD_CfgDeqExcessLatencyControl1, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqExcessLatencyControl1__Enable,
      "CfgDeqExcessLatencyControl1__Enable",
      AD_CfgDeqExcessLatencyControl1, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqHeaderStripControl,
      "CfgDeqHeaderStripControl",
      AD_CfgDeqHeaderStripControl, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqHeaderStripControl__HeaderBytesToPass,
      "CfgDeqHeaderStripControl__HeaderBytesToPass",
      AD_CfgDeqHeaderStripControl, 21, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqHeaderStripControl__HeaderStripMask,
      "CfgDeqHeaderStripControl__HeaderStripMask",
      AD_CfgDeqHeaderStripControl, 16, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqHeaderStripControl__HeaderStripEn,
      "CfgDeqHeaderStripControl__HeaderStripEn",
      AD_CfgDeqHeaderStripControl, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqIngressHeaderBigEndian,
      "CfgDeqIngressHeaderBigEndian",
      AD_CfgDeqIngressHeaderBigEndian, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqEOPAbortEn,
      "CfgDeqEOPAbortEn",
      AD_CfgDeqEOPAbortEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqEOFCount,
      "StsDeqEOFCount",
      AD_StsDeqEOFCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqLpbkEOFCount,
      "StsDeqLpbkEOFCount",
      AD_StsDeqLpbkEOFCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqPktCountQ0,
      "StsDeqPktCountQ0",
      AD_StsDeqPktCountQ0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqPktCountQ1,
      "StsDeqPktCountQ1",
      AD_StsDeqPktCountQ1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqPktCountQ2,
      "StsDeqPktCountQ2",
      AD_StsDeqPktCountQ2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqPktCountQ3,
      "StsDeqPktCountQ3",
      AD_StsDeqPktCountQ3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqPktCountQ4,
      "StsDeqPktCountQ4",
      AD_StsDeqPktCountQ4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqPktCountQ5,
      "StsDeqPktCountQ5",
      AD_StsDeqPktCountQ5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqPktCountQ6,
      "StsDeqPktCountQ6",
      AD_StsDeqPktCountQ6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqPktCountQ7,
      "StsDeqPktCountQ7",
      AD_StsDeqPktCountQ7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqExcessLatencyDropCountQ0,
      "StsDeqExcessLatencyDropCountQ0",
      AD_StsDeqExcessLatencyDropCountQ0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqExcessLatencyDropCountQ1,
      "StsDeqExcessLatencyDropCountQ1",
      AD_StsDeqExcessLatencyDropCountQ1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqExcessLatencyDropCountQ2,
      "StsDeqExcessLatencyDropCountQ2",
      AD_StsDeqExcessLatencyDropCountQ2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqExcessLatencyDropCountQ3,
      "StsDeqExcessLatencyDropCountQ3",
      AD_StsDeqExcessLatencyDropCountQ3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqExcessLatencyDropCountQ4,
      "StsDeqExcessLatencyDropCountQ4",
      AD_StsDeqExcessLatencyDropCountQ4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqExcessLatencyDropCountQ5,
      "StsDeqExcessLatencyDropCountQ5",
      AD_StsDeqExcessLatencyDropCountQ5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqExcessLatencyDropCountQ6,
      "StsDeqExcessLatencyDropCountQ6",
      AD_StsDeqExcessLatencyDropCountQ6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqExcessLatencyDropCountQ7,
      "StsDeqExcessLatencyDropCountQ7",
      AD_StsDeqExcessLatencyDropCountQ7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqQnumFifoOverflowInterrupt,
      "StsDeqQnumFifoOverflowInterrupt",
      AD_StsDeqQnumFifoOverflowInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqQnumFifoOverflowInterruptMask,
      "StsDeqQnumFifoOverflowInterruptMask",
      AD_StsDeqQnumFifoOverflowInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt0,
      "StsDeqDataFifoOverflowInterrupt0",
      AD_StsDeqDataFifoOverflowInterrupt0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt0Mask,
      "StsDeqDataFifoOverflowInterrupt0Mask",
      AD_StsDeqDataFifoOverflowInterrupt0Mask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt1,
      "StsDeqDataFifoOverflowInterrupt1",
      AD_StsDeqDataFifoOverflowInterrupt1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt1Mask,
      "StsDeqDataFifoOverflowInterrupt1Mask",
      AD_StsDeqDataFifoOverflowInterrupt1Mask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt2,
      "StsDeqDataFifoOverflowInterrupt2",
      AD_StsDeqDataFifoOverflowInterrupt2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt2Mask,
      "StsDeqDataFifoOverflowInterrupt2Mask",
      AD_StsDeqDataFifoOverflowInterrupt2Mask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt3,
      "StsDeqDataFifoOverflowInterrupt3",
      AD_StsDeqDataFifoOverflowInterrupt3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt3Mask,
      "StsDeqDataFifoOverflowInterrupt3Mask",
      AD_StsDeqDataFifoOverflowInterrupt3Mask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt4,
      "StsDeqDataFifoOverflowInterrupt4",
      AD_StsDeqDataFifoOverflowInterrupt4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt4Mask,
      "StsDeqDataFifoOverflowInterrupt4Mask",
      AD_StsDeqDataFifoOverflowInterrupt4Mask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt5,
      "StsDeqDataFifoOverflowInterrupt5",
      AD_StsDeqDataFifoOverflowInterrupt5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt5Mask,
      "StsDeqDataFifoOverflowInterrupt5Mask",
      AD_StsDeqDataFifoOverflowInterrupt5Mask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt6,
      "StsDeqDataFifoOverflowInterrupt6",
      AD_StsDeqDataFifoOverflowInterrupt6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt6Mask,
      "StsDeqDataFifoOverflowInterrupt6Mask",
      AD_StsDeqDataFifoOverflowInterrupt6Mask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt7,
      "StsDeqDataFifoOverflowInterrupt7",
      AD_StsDeqDataFifoOverflowInterrupt7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqDataFifoOverflowInterrupt7Mask,
      "StsDeqDataFifoOverflowInterrupt7Mask",
      AD_StsDeqDataFifoOverflowInterrupt7Mask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqEccErrorInterrupt,
      "StsDeqEccErrorInterrupt",
      AD_StsDeqEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqEccErrorInterruptMask,
      "StsDeqEccErrorInterruptMask",
      AD_StsDeqEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqEccSingleErrorInterrupt,
      "StsDeqEccSingleErrorInterrupt",
      AD_StsDeqEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqEccSingleErrorInterruptMask,
      "StsDeqEccSingleErrorInterruptMask",
      AD_StsDeqEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqEccDoubleErrorInterrupt,
      "StsDeqEccDoubleErrorInterrupt",
      AD_StsDeqEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqEccDoubleErrorInterruptMask,
      "StsDeqEccDoubleErrorInterruptMask",
      AD_StsDeqEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqWritePointer,
      "StsDeqWritePointer",
      AD_StsDeqWritePointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqReadPointer,
      "StsDeqReadPointer",
      AD_StsDeqReadPointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqCommitPointer,
      "StsDeqCommitPointer",
      AD_StsDeqCommitPointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUAccess,
      "CfgDeqCPUAccess",
      AD_CfgDeqCPUAccess, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUAccess__CPUCommitPtrSet,
      "CfgDeqCPUAccess__CPUCommitPtrSet",
      AD_CfgDeqCPUAccess, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUAccess__CPURead,
      "CfgDeqCPUAccess__CPURead",
      AD_CfgDeqCPUAccess, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUAccess__CPUWrite,
      "CfgDeqCPUAccess__CPUWrite",
      AD_CfgDeqCPUAccess, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUAccess__CPUAccessEn,
      "CfgDeqCPUAccess__CPUAccessEn",
      AD_CfgDeqCPUAccess, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUWriteAddress,
      "CfgDeqCPUWriteAddress",
      AD_CfgDeqCPUWriteAddress, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUReadAddress,
      "CfgDeqCPUReadAddress",
      AD_CfgDeqCPUReadAddress, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUCommitPointer,
      "CfgDeqCPUCommitPointer",
      AD_CfgDeqCPUCommitPointer, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUWriteData_0,
      "CfgDeqCPUWriteData_0",
      AD_CfgDeqCPUWriteData_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUWriteData_1,
      "CfgDeqCPUWriteData_1",
      AD_CfgDeqCPUWriteData_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUWriteData_2,
      "CfgDeqCPUWriteData_2",
      AD_CfgDeqCPUWriteData_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUWriteData_3,
      "CfgDeqCPUWriteData_3",
      AD_CfgDeqCPUWriteData_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUWriteData_4,
      "CfgDeqCPUWriteData_4",
      AD_CfgDeqCPUWriteData_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUWriteData_5,
      "CfgDeqCPUWriteData_5",
      AD_CfgDeqCPUWriteData_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUWriteData_6,
      "CfgDeqCPUWriteData_6",
      AD_CfgDeqCPUWriteData_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUWriteData_7,
      "CfgDeqCPUWriteData_7",
      AD_CfgDeqCPUWriteData_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqCPUWriteData_8,
      "CfgDeqCPUWriteData_8",
      AD_CfgDeqCPUWriteData_8, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqCPUReadData_0,
      "StsDeqCPUReadData_0",
      AD_StsDeqCPUReadData_0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqCPUReadData_1,
      "StsDeqCPUReadData_1",
      AD_StsDeqCPUReadData_1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqCPUReadData_2,
      "StsDeqCPUReadData_2",
      AD_StsDeqCPUReadData_2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqCPUReadData_3,
      "StsDeqCPUReadData_3",
      AD_StsDeqCPUReadData_3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqCPUReadData_4,
      "StsDeqCPUReadData_4",
      AD_StsDeqCPUReadData_4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqCPUReadData_5,
      "StsDeqCPUReadData_5",
      AD_StsDeqCPUReadData_5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqCPUReadData_6,
      "StsDeqCPUReadData_6",
      AD_StsDeqCPUReadData_6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqCPUReadData_7,
      "StsDeqCPUReadData_7",
      AD_StsDeqCPUReadData_7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDeqCPUReadData_8,
      "StsDeqCPUReadData_8",
      AD_StsDeqCPUReadData_8, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqMTUFullnessThreshold,
      "CfgDeqMTUFullnessThreshold",
      AD_CfgDeqMTUFullnessThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqOutputToNpuIsPSD,
      "CfgDeqOutputToNpuIsPSD",
      AD_CfgDeqOutputToNpuIsPSD, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqPauseFrameOnThreshold,
      "CfgDeqPauseFrameOnThreshold",
      AD_CfgDeqPauseFrameOnThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDeqPauseFrameOffThreshold,
      "CfgDeqPauseFrameOffThreshold",
      AD_CfgDeqPauseFrameOffThreshold, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxpSpiSetup,
      "CfgRegRxpSpiSetup",
      AD_CfgRegRxpSpiSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__InsertDIP4Err,
      "CfgRegRxpSpiSetup__InsertDIP4Err",
      AD_CfgRegRxpSpiSetup, 15, 15, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__EnMaintinAPSMode,
      "CfgRegRxpSpiSetup__EnMaintinAPSMode",
      AD_CfgRegRxpSpiSetup, 14, 14, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__FlowCntrl4to1FunnelMode,
      "CfgRegRxpSpiSetup__FlowCntrl4to1FunnelMode",
      AD_CfgRegRxpSpiSetup, 13, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__DisSysXauiFlowCntrl,
      "CfgRegRxpSpiSetup__DisSysXauiFlowCntrl",
      AD_CfgRegRxpSpiSetup, 12, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__DisAbortInsonLOS,
      "CfgRegRxpSpiSetup__DisAbortInsonLOS",
      AD_CfgRegRxpSpiSetup, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__AllowNonMb1Mb2Burst,
      "CfgRegRxpSpiSetup__AllowNonMb1Mb2Burst",
      AD_CfgRegRxpSpiSetup, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__MDRRDis,
      "CfgRegRxpSpiSetup__MDRRDis",
      AD_CfgRegRxpSpiSetup, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__BandWidthMeterDis,
      "CfgRegRxpSpiSetup__BandWidthMeterDis",
      AD_CfgRegRxpSpiSetup, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__FlipRDATBusBitOrder,
      "CfgRegRxpSpiSetup__FlipRDATBusBitOrder",
      AD_CfgRegRxpSpiSetup, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__EnShdwCalmode,
      "CfgRegRxpSpiSetup__EnShdwCalmode",
      AD_CfgRegRxpSpiSetup, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__CtlWdPackDis,
      "CfgRegRxpSpiSetup__CtlWdPackDis",
      AD_CfgRegRxpSpiSetup, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__HarrierModeEn,
      "CfgRegRxpSpiSetup__HarrierModeEn",
      AD_CfgRegRxpSpiSetup, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__EnableStatus,
      "CfgRegRxpSpiSetup__EnableStatus",
      AD_CfgRegRxpSpiSetup, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__PacketMode,
      "CfgRegRxpSpiSetup__PacketMode",
      AD_CfgRegRxpSpiSetup, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__IgnoreErrors,
      "CfgRegRxpSpiSetup__IgnoreErrors",
      AD_CfgRegRxpSpiSetup, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSetup__EnableTraining,
      "CfgRegRxpSpiSetup__EnableTraining",
      AD_CfgRegRxpSpiSetup, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSwitchPattern,
      "CfgRegRxpSpiSwitchPattern",
      AD_CfgRegRxpSpiSwitchPattern, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSwitchPattern__ShdSwitchPattern,
      "CfgRegRxpSpiSwitchPattern__ShdSwitchPattern",
      AD_CfgRegRxpSpiSwitchPattern, 19, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiSwitchPattern__PriSwitchPattern,
      "CfgRegRxpSpiSwitchPattern__PriSwitchPattern",
      AD_CfgRegRxpSpiSwitchPattern, 9, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiLocalPortMaxBurst,
      "CfgRegRxpSpiLocalPortMaxBurst",
      AD_CfgRegRxpSpiLocalPortMaxBurst, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiLocalPortMaxBurst__StartBurstifCreditGTMB2,
      "CfgRegRxpSpiLocalPortMaxBurst__StartBurstifCreditGTMB2",
      AD_CfgRegRxpSpiLocalPortMaxBurst, 16, 16, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiLocalPortMaxBurst__MaxBurstShdw2,
      "CfgRegRxpSpiLocalPortMaxBurst__MaxBurstShdw2",
      AD_CfgRegRxpSpiLocalPortMaxBurst, 15, 12, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiLocalPortMaxBurst__MaxBurstShdw1,
      "CfgRegRxpSpiLocalPortMaxBurst__MaxBurstShdw1",
      AD_CfgRegRxpSpiLocalPortMaxBurst, 11, 8, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri2,
      "CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri2",
      AD_CfgRegRxpSpiLocalPortMaxBurst, 7, 4, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri1,
      "CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri1",
      AD_CfgRegRxpSpiLocalPortMaxBurst, 3, 0, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiCascadePortMaxBurst,
      "CfgRegRxpSpiCascadePortMaxBurst",
      AD_CfgRegRxpSpiCascadePortMaxBurst, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiCascadePortMaxBurst__StartBurstifCreditGTMB2,
      "CfgRegRxpSpiCascadePortMaxBurst__StartBurstifCreditGTMB2",
      AD_CfgRegRxpSpiCascadePortMaxBurst, 16, 16, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiCascadePortMaxBurst__MaxBurstShdw2,
      "CfgRegRxpSpiCascadePortMaxBurst__MaxBurstShdw2",
      AD_CfgRegRxpSpiCascadePortMaxBurst, 15, 12, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiCascadePortMaxBurst__MaxBurstShdw1,
      "CfgRegRxpSpiCascadePortMaxBurst__MaxBurstShdw1",
      AD_CfgRegRxpSpiCascadePortMaxBurst, 11, 8, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiCascadePortMaxBurst__MaxBurstPri2,
      "CfgRegRxpSpiCascadePortMaxBurst__MaxBurstPri2",
      AD_CfgRegRxpSpiCascadePortMaxBurst, 7, 4, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiCascadePortMaxBurst__MaxBurstPri1,
      "CfgRegRxpSpiCascadePortMaxBurst__MaxBurstPri1",
      AD_CfgRegRxpSpiCascadePortMaxBurst, 3, 0, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiMaintPortMaxBurst,
      "CfgRegRxpSpiMaintPortMaxBurst",
      AD_CfgRegRxpSpiMaintPortMaxBurst, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaintPortMaxBurst__StartBurstifCreditGTMB2,
      "CfgRegRxpSpiMaintPortMaxBurst__StartBurstifCreditGTMB2",
      AD_CfgRegRxpSpiMaintPortMaxBurst, 16, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaintPortMaxBurst__MaxBurstShdw2,
      "CfgRegRxpSpiMaintPortMaxBurst__MaxBurstShdw2",
      AD_CfgRegRxpSpiMaintPortMaxBurst, 15, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaintPortMaxBurst__MaxBurstShdw1,
      "CfgRegRxpSpiMaintPortMaxBurst__MaxBurstShdw1",
      AD_CfgRegRxpSpiMaintPortMaxBurst, 11, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaintPortMaxBurst__MaxBurstPri2,
      "CfgRegRxpSpiMaintPortMaxBurst__MaxBurstPri2",
      AD_CfgRegRxpSpiMaintPortMaxBurst, 7, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaintPortMaxBurst__MaxBurstPri1,
      "CfgRegRxpSpiMaintPortMaxBurst__MaxBurstPri1",
      AD_CfgRegRxpSpiMaintPortMaxBurst, 3, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiLocalBWMeterWin,
      "CfgRegRxpSpiLocalBWMeterWin",
      AD_CfgRegRxpSpiLocalBWMeterWin, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiLocalMinMaxCredit,
      "CfgRegRxpSpiLocalMinMaxCredit",
      AD_CfgRegRxpSpiLocalMinMaxCredit, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiLocalMinMaxCredit__MaxCredit,
      "CfgRegRxpSpiLocalMinMaxCredit__MaxCredit",
      AD_CfgRegRxpSpiLocalMinMaxCredit, 31, 16, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiLocalMinMaxCredit__MinCredit,
      "CfgRegRxpSpiLocalMinMaxCredit__MinCredit",
      AD_CfgRegRxpSpiLocalMinMaxCredit, 15, 0, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiCascadeBWMeterWin,
      "CfgRegRxpSpiCascadeBWMeterWin",
      AD_CfgRegRxpSpiCascadeBWMeterWin, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiCascadeMinMaxCredit,
      "CfgRegRxpSpiCascadeMinMaxCredit",
      AD_CfgRegRxpSpiCascadeMinMaxCredit, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiCascadeMinMaxCredit__MaxCredit,
      "CfgRegRxpSpiCascadeMinMaxCredit__MaxCredit",
      AD_CfgRegRxpSpiCascadeMinMaxCredit, 31, 16, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiCascadeMinMaxCredit__MinCredit,
      "CfgRegRxpSpiCascadeMinMaxCredit__MinCredit",
      AD_CfgRegRxpSpiCascadeMinMaxCredit, 15, 0, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxpSpiMaintBWMeterWin,
      "CfgRegRxpSpiMaintBWMeterWin",
      AD_CfgRegRxpSpiMaintBWMeterWin, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaintMinMaxCredit,
      "CfgRegRxpSpiMaintMinMaxCredit",
      AD_CfgRegRxpSpiMaintMinMaxCredit, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaintMinMaxCredit__MaxCredits,
      "CfgRegRxpSpiMaintMinMaxCredit__MaxCredits",
      AD_CfgRegRxpSpiMaintMinMaxCredit, 31, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaintMinMaxCredit__MinCredits,
      "CfgRegRxpSpiMaintMinMaxCredit__MinCredits",
      AD_CfgRegRxpSpiMaintMinMaxCredit, 15, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiAddressMap,
      "CfgRegRxpSpiAddressMap",
      AD_CfgRegRxpSpiAddressMap, 0, 0, PROP_RW_WHOLE,
      0x4, INST5, 0, 0, 0 },

    { CfgRegRxpSpiAlpha,
      "CfgRegRxpSpiAlpha",
      AD_CfgRegRxpSpiAlpha, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDataMaxTLsb,
      "CfgRegRxpSpiDataMaxTLsb",
      AD_CfgRegRxpSpiDataMaxTLsb, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDataMaxTMsb,
      "CfgRegRxpSpiDataMaxTMsb",
      AD_CfgRegRxpSpiDataMaxTMsb, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiIntFifoThr,
      "CfgRegRxpSpiIntFifoThr",
      AD_CfgRegRxpSpiIntFifoThr, 0, 0, PROP_RW_WHOLE,
      0x4, INST5, 0, 0, 0 },

    { CfgRegRxpSpiIntFifoThr__IntFifoFullThr,
      "CfgRegRxpSpiIntFifoThr__IntFifoFullThr",
      AD_CfgRegRxpSpiIntFifoThr, 7, 4, PROP_RW,
      0x4, INST5, 0, 0, 0 },

    { CfgRegRxpSpiIntFifoThr__IntFifoEmptyThr,
      "CfgRegRxpSpiIntFifoThr__IntFifoEmptyThr",
      AD_CfgRegRxpSpiIntFifoThr, 3, 0, PROP_RW,
      0x4, INST5, 0, 0, 0 },

    { CfgRegRxpSpiOutFifoThr,
      "CfgRegRxpSpiOutFifoThr",
      AD_CfgRegRxpSpiOutFifoThr, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiOutFifoThr__OutFifoFullThrInTrain,
      "CfgRegRxpSpiOutFifoThr__OutFifoFullThrInTrain",
      AD_CfgRegRxpSpiOutFifoThr, 11, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiOutFifoThr__OutFifoFullThr,
      "CfgRegRxpSpiOutFifoThr__OutFifoFullThr",
      AD_CfgRegRxpSpiOutFifoThr, 5, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMinMdrrWindow,
      "CfgRegRxpSpiMinMdrrWindow",
      AD_CfgRegRxpSpiMinMdrrWindow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMinMdrrWindow__RstCreditAllSat,
      "CfgRegRxpSpiMinMdrrWindow__RstCreditAllSat",
      AD_CfgRegRxpSpiMinMdrrWindow, 25, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMinMdrrWindow__LimitCredit,
      "CfgRegRxpSpiMinMdrrWindow__LimitCredit",
      AD_CfgRegRxpSpiMinMdrrWindow, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMinMdrrWindow__WindowSize,
      "CfgRegRxpSpiMinMdrrWindow__WindowSize",
      AD_CfgRegRxpSpiMinMdrrWindow, 23, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMinMdrrCredit,
      "CfgRegRxpSpiMinMdrrCredit",
      AD_CfgRegRxpSpiMinMdrrCredit, 0, 0, PROP_RW_WHOLE,
      0x4, INST5, 0, 0, 0 },

    { CfgRegRxpSpiMaxMdrrWindow,
      "CfgRegRxpSpiMaxMdrrWindow",
      AD_CfgRegRxpSpiMaxMdrrWindow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaxMdrrWindow__MaxCreditSel,
      "CfgRegRxpSpiMaxMdrrWindow__MaxCreditSel",
      AD_CfgRegRxpSpiMaxMdrrWindow, 26, 26, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaxMdrrWindow__RstCreditAllSat,
      "CfgRegRxpSpiMaxMdrrWindow__RstCreditAllSat",
      AD_CfgRegRxpSpiMaxMdrrWindow, 25, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaxMdrrWindow__LimitCredit,
      "CfgRegRxpSpiMaxMdrrWindow__LimitCredit",
      AD_CfgRegRxpSpiMaxMdrrWindow, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaxMdrrWindow__WindowSize,
      "CfgRegRxpSpiMaxMdrrWindow__WindowSize",
      AD_CfgRegRxpSpiMaxMdrrWindow, 23, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaxMdrrCredit,
      "CfgRegRxpSpiMaxMdrrCredit",
      AD_CfgRegRxpSpiMaxMdrrCredit, 0, 0, PROP_RW_WHOLE,
      0x4, INST5, 0, 0, 0 },

    { CfgRegRxpspiInPipeBurstCnt,
      "CfgRegRxpspiInPipeBurstCnt",
      AD_CfgRegRxpspiInPipeBurstCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpspiInPipeBurstCnt__InPipeBurstCntDis,
      "CfgRegRxpspiInPipeBurstCnt__InPipeBurstCntDis",
      AD_CfgRegRxpspiInPipeBurstCnt, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpspiInPipeBurstCnt__InPipeBurstCnt,
      "CfgRegRxpspiInPipeBurstCnt__InPipeBurstCnt",
      AD_CfgRegRxpspiInPipeBurstCnt, 4, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaxPacketSize,
      "CfgRegRxpSpiMaxPacketSize",
      AD_CfgRegRxpSpiMaxPacketSize, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaxPacketSize__BurstOverMb2,
      "CfgRegRxpSpiMaxPacketSize__BurstOverMb2",
      AD_CfgRegRxpSpiMaxPacketSize, 18, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiMaxPacketSize__MaxPktSize,
      "CfgRegRxpSpiMaxPacketSize__MaxPktSize",
      AD_CfgRegRxpSpiMaxPacketSize, 15, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHarMdrrStopThr,
      "CfgRegRxpSpiHarMdrrStopThr",
      AD_CfgRegRxpSpiHarMdrrStopThr, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHarMdrrStopThr__HarPreFetchFifoFullThr,
      "CfgRegRxpSpiHarMdrrStopThr__HarPreFetchFifoFullThr",
      AD_CfgRegRxpSpiHarMdrrStopThr, 28, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHarMdrrStopThr__EnHarModeFlowCtrl,
      "CfgRegRxpSpiHarMdrrStopThr__EnHarModeFlowCtrl",
      AD_CfgRegRxpSpiHarMdrrStopThr, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHarMdrrStopThr__HarMdrrStopThr,
      "CfgRegRxpSpiHarMdrrStopThr__HarMdrrStopThr",
      AD_CfgRegRxpSpiHarMdrrStopThr, 23, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHMMisc,
      "CfgRegRxpSpiHMMisc",
      AD_CfgRegRxpSpiHMMisc, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHMMisc__RSPI_BERT_TX_EN,
      "CfgRegRxpSpiHMMisc__RSPI_BERT_TX_EN",
      AD_CfgRegRxpSpiHMMisc, 22, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHMMisc__RSPI_BERT_RX_EN,
      "CfgRegRxpSpiHMMisc__RSPI_BERT_RX_EN",
      AD_CfgRegRxpSpiHMMisc, 21, 21, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHMMisc__RSPI_BYPASS_EN,
      "CfgRegRxpSpiHMMisc__RSPI_BYPASS_EN",
      AD_CfgRegRxpSpiHMMisc, 20, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHMMisc__RSPI_SFI_CLOCK_MODE,
      "CfgRegRxpSpiHMMisc__RSPI_SFI_CLOCK_MODE",
      AD_CfgRegRxpSpiHMMisc, 19, 19, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHMMisc__RSPI_POWER_DOWN,
      "CfgRegRxpSpiHMMisc__RSPI_POWER_DOWN",
      AD_CfgRegRxpSpiHMMisc, 18, 18, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiHMMisc__RSPI_LOOPBACK,
      "CfgRegRxpSpiHMMisc__RSPI_LOOPBACK",
      AD_CfgRegRxpSpiHMMisc, 17, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWMisc,
      "CfgRegRxpSpiDESKEWMisc",
      AD_CfgRegRxpSpiDESKEWMisc, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWMisc__SpiChShift,
      "CfgRegRxpSpiDESKEWMisc__SpiChShift",
      AD_CfgRegRxpSpiDESKEWMisc, 24, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWMisc__SpiRxMode,
      "CfgRegRxpSpiDESKEWMisc__SpiRxMode",
      AD_CfgRegRxpSpiDESKEWMisc, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWMisc__SpiTxMode,
      "CfgRegRxpSpiDESKEWMisc__SpiTxMode",
      AD_CfgRegRxpSpiDESKEWMisc, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWMisc__SpiTestMode,
      "CfgRegRxpSpiDESKEWMisc__SpiTestMode",
      AD_CfgRegRxpSpiDESKEWMisc, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWMisc__SpiTrainEn,
      "CfgRegRxpSpiDESKEWMisc__SpiTrainEn",
      AD_CfgRegRxpSpiDESKEWMisc, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWMisc__OutOfRangeEn,
      "CfgRegRxpSpiDESKEWMisc__OutOfRangeEn",
      AD_CfgRegRxpSpiDESKEWMisc, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWMisc__RxClearDeskew,
      "CfgRegRxpSpiDESKEWMisc__RxClearDeskew",
      AD_CfgRegRxpSpiDESKEWMisc, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWMisc__BitAlignModeEn,
      "CfgRegRxpSpiDESKEWMisc__BitAlignModeEn",
      AD_CfgRegRxpSpiDESKEWMisc, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWMisc__TxClearDeskew,
      "CfgRegRxpSpiDESKEWMisc__TxClearDeskew",
      AD_CfgRegRxpSpiDESKEWMisc, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWTraPat0,
      "CfgRegRxpSpiDESKEWTraPat0",
      AD_CfgRegRxpSpiDESKEWTraPat0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWTraPat1,
      "CfgRegRxpSpiDESKEWTraPat1",
      AD_CfgRegRxpSpiDESKEWTraPat1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWReg0,
      "CfgRegRxpSpiDESKEWReg0",
      AD_CfgRegRxpSpiDESKEWReg0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDESKEWReg1,
      "CfgRegRxpSpiDESKEWReg1",
      AD_CfgRegRxpSpiDESKEWReg1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiIntLBFifoRdThresh,
      "CfgRegRxpSpiIntLBFifoRdThresh",
      AD_CfgRegRxpSpiIntLBFifoRdThresh, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRpSpiSkewOutofRange,
      "StsRpSpiSkewOutofRange",
      AD_StsRpSpiSkewOutofRange, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRpSpiPLLLockDet,
      "StsRpSpiPLLLockDet",
      AD_StsRpSpiPLLLockDet, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRpSpiTrainAct,
      "StsRpSpiTrainAct",
      AD_StsRpSpiTrainAct, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxpSpiInFifoEopCnt,
      "StsRegRxpSpiInFifoEopCnt",
      AD_StsRegRxpSpiInFifoEopCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxpSpiSopCount,
      "StsRegRxpSpiSopCount",
      AD_StsRegRxpSpiSopCount, 0, 0, PROP_RW_WHOLE,
      0x4, INST5, 0, 0, 0 },

    { StsRegRxpSpiEop1Count,
      "StsRegRxpSpiEop1Count",
      AD_StsRegRxpSpiEop1Count, 0, 0, PROP_RW_WHOLE,
      0x4, INST5, 0, 0, 0 },

    { StsRegRxpSpiEop2Count,
      "StsRegRxpSpiEop2Count",
      AD_StsRegRxpSpiEop2Count, 0, 0, PROP_RW_WHOLE,
      0x4, INST5, 0, 0, 0 },

    { StsRegRxpSpiEopACount,
      "StsRegRxpSpiEopACount",
      AD_StsRegRxpSpiEopACount, 0, 0, PROP_RW_WHOLE,
      0x4, INST5, 0, 0, 0 },

    { StsRegRxpSpiTrainingCount,
      "StsRegRxpSpiTrainingCount",
      AD_StsRegRxpSpiTrainingCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxpSpiMdrrCreditCntr,
      "StsRegRxpSpiMdrrCreditCntr",
      AD_StsRegRxpSpiMdrrCreditCntr, 0, 0, PROP_RW_WHOLE,
      0x4, INST5, 0, 0, 0 },

    { StsRegRxpSpiPortBurstCntr,
      "StsRegRxpSpiPortBurstCntr",
      AD_StsRegRxpSpiPortBurstCntr, 0, 0, PROP_RW_WHOLE,
      0x4, INST5, 0, 0, 0 },

    { StsRegRxpSpiPerFetchFifoUFlow,
      "StsRegRxpSpiPerFetchFifoUFlow",
      AD_StsRegRxpSpiPerFetchFifoUFlow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxpSpiOutputFifoUFlow,
      "StsRegRxpSpiOutputFifoUFlow",
      AD_StsRegRxpSpiOutputFifoUFlow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxpSpiDiag,
      "StsRegRxpSpiDiag",
      AD_StsRegRxpSpiDiag, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxpShdwCalendarAct,
      "StsRegRxpShdwCalendarAct",
      AD_StsRegRxpShdwCalendarAct, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMemRxpSpiCalPri,
      "CfgMemRxpSpiCalPri",
      AD_CfgMemRxpSpiCalPri, 0, 0, PROP_RW_WHOLE,
      0x4, INST128, 0, 0, 0 },

    { CfgMemRxpSpiCalShadow,
      "CfgMemRxpSpiCalShadow",
      AD_CfgMemRxpSpiCalShadow, 0, 0, PROP_RW_WHOLE,
      0x4, INST128, 0, 0, 0 },

    { CfgRegRxpSpiCalSetup,
      "CfgRegRxpSpiCalSetup",
      AD_CfgRegRxpSpiCalSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiCalSetup__ShCalL,
      "CfgRegRxpSpiCalSetup__ShCalL",
      AD_CfgRegRxpSpiCalSetup, 21, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiCalSetup__ShCalM,
      "CfgRegRxpSpiCalSetup__ShCalM",
      AD_CfgRegRxpSpiCalSetup, 12, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiCalSetup__CalL,
      "CfgRegRxpSpiCalSetup__CalL",
      AD_CfgRegRxpSpiCalSetup, 10, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiCalSetup__CalM,
      "CfgRegRxpSpiCalSetup__CalM",
      AD_CfgRegRxpSpiCalSetup, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDip2Thr,
      "CfgRegRxpSpiDip2Thr",
      AD_CfgRegRxpSpiDip2Thr, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDip2Thr__LOSFrmPatThr,
      "CfgRegRxpSpiDip2Thr__LOSFrmPatThr",
      AD_CfgRegRxpSpiDip2Thr, 12, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxpSpiDip2Thr__LOSDip2ErrThr,
      "CfgRegRxpSpiDip2Thr__LOSDip2ErrThr",
      AD_CfgRegRxpSpiDip2Thr, 7, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { StsRegRxpSpiDip2ErrCount,
      "StsRegRxpSpiDip2ErrCount",
      AD_StsRegRxpSpiDip2ErrCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxpSpiLosStatus,
      "StsRegRxpSpiLosStatus",
      AD_StsRegRxpSpiLosStatus, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxpSpiInterrupt,
      "StsRegRxpSpiInterrupt",
      AD_StsRegRxpSpiInterrupt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxpSpiInterruptMask,
      "StsRegRxpSpiInterruptMask",
      AD_StsRegRxpSpiInterruptMask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup,
      "CfgRegRxsSpiSetup",
      AD_CfgRegRxsSpiSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__InsertDIP4Err,
      "CfgRegRxsSpiSetup__InsertDIP4Err",
      AD_CfgRegRxsSpiSetup, 13, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__DisSysXauiFlowCntrl,
      "CfgRegRxsSpiSetup__DisSysXauiFlowCntrl",
      AD_CfgRegRxsSpiSetup, 12, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__DisAbortInsonLOS,
      "CfgRegRxsSpiSetup__DisAbortInsonLOS",
      AD_CfgRegRxsSpiSetup, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__AllowNonMb1Mb2Burst,
      "CfgRegRxsSpiSetup__AllowNonMb1Mb2Burst",
      AD_CfgRegRxsSpiSetup, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__MDRRDis,
      "CfgRegRxsSpiSetup__MDRRDis",
      AD_CfgRegRxsSpiSetup, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__BandWidthMeterDis,
      "CfgRegRxsSpiSetup__BandWidthMeterDis",
      AD_CfgRegRxsSpiSetup, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__FlipRDATBusBitOrder,
      "CfgRegRxsSpiSetup__FlipRDATBusBitOrder",
      AD_CfgRegRxsSpiSetup, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__EnShdwCalmode,
      "CfgRegRxsSpiSetup__EnShdwCalmode",
      AD_CfgRegRxsSpiSetup, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__CtlWdPackDis,
      "CfgRegRxsSpiSetup__CtlWdPackDis",
      AD_CfgRegRxsSpiSetup, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__HarrierModeEn,
      "CfgRegRxsSpiSetup__HarrierModeEn",
      AD_CfgRegRxsSpiSetup, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__EnableStatus,
      "CfgRegRxsSpiSetup__EnableStatus",
      AD_CfgRegRxsSpiSetup, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__PacketMode,
      "CfgRegRxsSpiSetup__PacketMode",
      AD_CfgRegRxsSpiSetup, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__IgnoreErrors,
      "CfgRegRxsSpiSetup__IgnoreErrors",
      AD_CfgRegRxsSpiSetup, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSetup__EnableTraining,
      "CfgRegRxsSpiSetup__EnableTraining",
      AD_CfgRegRxsSpiSetup, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSwitchPattern,
      "CfgRegRxsSpiSwitchPattern",
      AD_CfgRegRxsSpiSwitchPattern, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSwitchPattern__ShdSwitchPattern,
      "CfgRegRxsSpiSwitchPattern__ShdSwitchPattern",
      AD_CfgRegRxsSpiSwitchPattern, 19, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiSwitchPattern__PriSwitchPattern,
      "CfgRegRxsSpiSwitchPattern__PriSwitchPattern",
      AD_CfgRegRxsSpiSwitchPattern, 9, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiLocalPortMaxBurst,
      "CfgRegRxsSpiLocalPortMaxBurst",
      AD_CfgRegRxsSpiLocalPortMaxBurst, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiLocalPortMaxBurst__StartBurstifCreditGTMB2,
      "CfgRegRxsSpiLocalPortMaxBurst__StartBurstifCreditGTMB2",
      AD_CfgRegRxsSpiLocalPortMaxBurst, 16, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiLocalPortMaxBurst__MaxBurstShdw2,
      "CfgRegRxsSpiLocalPortMaxBurst__MaxBurstShdw2",
      AD_CfgRegRxsSpiLocalPortMaxBurst, 15, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiLocalPortMaxBurst__MaxBurstShdw1,
      "CfgRegRxsSpiLocalPortMaxBurst__MaxBurstShdw1",
      AD_CfgRegRxsSpiLocalPortMaxBurst, 11, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiLocalPortMaxBurst__MaxBurstPri2,
      "CfgRegRxsSpiLocalPortMaxBurst__MaxBurstPri2",
      AD_CfgRegRxsSpiLocalPortMaxBurst, 7, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiLocalPortMaxBurst__MaxBurstPri1,
      "CfgRegRxsSpiLocalPortMaxBurst__MaxBurstPri1",
      AD_CfgRegRxsSpiLocalPortMaxBurst, 3, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCascadePortMaxBurst,
      "CfgRegRxsSpiCascadePortMaxBurst",
      AD_CfgRegRxsSpiCascadePortMaxBurst, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCascadePortMaxBurst__StartBurstifCreditGTMB2,
      "CfgRegRxsSpiCascadePortMaxBurst__StartBurstifCreditGTMB2",
      AD_CfgRegRxsSpiCascadePortMaxBurst, 16, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCascadePortMaxBurst__MaxBurstShdw2,
      "CfgRegRxsSpiCascadePortMaxBurst__MaxBurstShdw2",
      AD_CfgRegRxsSpiCascadePortMaxBurst, 15, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCascadePortMaxBurst__MaxBurstShdw1,
      "CfgRegRxsSpiCascadePortMaxBurst__MaxBurstShdw1",
      AD_CfgRegRxsSpiCascadePortMaxBurst, 11, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCascadePortMaxBurst__MaxBurstPri2,
      "CfgRegRxsSpiCascadePortMaxBurst__MaxBurstPri2",
      AD_CfgRegRxsSpiCascadePortMaxBurst, 7, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCascadePortMaxBurst__MaxBurstPri1,
      "CfgRegRxsSpiCascadePortMaxBurst__MaxBurstPri1",
      AD_CfgRegRxsSpiCascadePortMaxBurst, 3, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiLocalBWMeterWin,
      "CfgRegRxsSpiLocalBWMeterWin",
      AD_CfgRegRxsSpiLocalBWMeterWin, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiLocalMinMaxCredit,
      "CfgRegRxsSpiLocalMinMaxCredit",
      AD_CfgRegRxsSpiLocalMinMaxCredit, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiLocalMinMaxCredit__MaxCredit,
      "CfgRegRxsSpiLocalMinMaxCredit__MaxCredit",
      AD_CfgRegRxsSpiLocalMinMaxCredit, 31, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiLocalMinMaxCredit__MinCredit,
      "CfgRegRxsSpiLocalMinMaxCredit__MinCredit",
      AD_CfgRegRxsSpiLocalMinMaxCredit, 15, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCascadeBWMeterWin,
      "CfgRegRxsSpiCascadeBWMeterWin",
      AD_CfgRegRxsSpiCascadeBWMeterWin, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCascadeMinMaxCredit,
      "CfgRegRxsSpiCascadeMinMaxCredit",
      AD_CfgRegRxsSpiCascadeMinMaxCredit, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCascadeMinMaxCredit__MaxCredit,
      "CfgRegRxsSpiCascadeMinMaxCredit__MaxCredit",
      AD_CfgRegRxsSpiCascadeMinMaxCredit, 31, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCascadeMinMaxCredit__MinCredit,
      "CfgRegRxsSpiCascadeMinMaxCredit__MinCredit",
      AD_CfgRegRxsSpiCascadeMinMaxCredit, 15, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiAddressMap,
      "CfgRegRxsSpiAddressMap",
      AD_CfgRegRxsSpiAddressMap, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxsSpiAlpha,
      "CfgRegRxsSpiAlpha",
      AD_CfgRegRxsSpiAlpha, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDataMaxTLsb,
      "CfgRegRxsSpiDataMaxTLsb",
      AD_CfgRegRxsSpiDataMaxTLsb, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDataMaxTMsb,
      "CfgRegRxsSpiDataMaxTMsb",
      AD_CfgRegRxsSpiDataMaxTMsb, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiThr,
      "CfgRegRxsSpiThr",
      AD_CfgRegRxsSpiThr, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxsSpiThr__IntFifoFullThr,
      "CfgRegRxsSpiThr__IntFifoFullThr",
      AD_CfgRegRxsSpiThr, 7, 4, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxsSpiThr__IntFifoEmptyThr,
      "CfgRegRxsSpiThr__IntFifoEmptyThr",
      AD_CfgRegRxsSpiThr, 3, 0, PROP_RW,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxsSpiOutFifoThr,
      "CfgRegRxsSpiOutFifoThr",
      AD_CfgRegRxsSpiOutFifoThr, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiOutFifoThr__OutFifoFullThrInTrain,
      "CfgRegRxsSpiOutFifoThr__OutFifoFullThrInTrain",
      AD_CfgRegRxsSpiOutFifoThr, 11, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiOutFifoThr__OutFifoFullThr,
      "CfgRegRxsSpiOutFifoThr__OutFifoFullThr",
      AD_CfgRegRxsSpiOutFifoThr, 5, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMinMdrrWindow,
      "CfgRegRxsSpiMinMdrrWindow",
      AD_CfgRegRxsSpiMinMdrrWindow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMinMdrrWindow__RstCreditAllSat,
      "CfgRegRxsSpiMinMdrrWindow__RstCreditAllSat",
      AD_CfgRegRxsSpiMinMdrrWindow, 25, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMinMdrrWindow__LimitCredit,
      "CfgRegRxsSpiMinMdrrWindow__LimitCredit",
      AD_CfgRegRxsSpiMinMdrrWindow, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMinMdrrWindow__WindowSize,
      "CfgRegRxsSpiMinMdrrWindow__WindowSize",
      AD_CfgRegRxsSpiMinMdrrWindow, 23, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMinMdrrCredit,
      "CfgRegRxsSpiMinMdrrCredit",
      AD_CfgRegRxsSpiMinMdrrCredit, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxsSpiMaxMdrrWindow,
      "CfgRegRxsSpiMaxMdrrWindow",
      AD_CfgRegRxsSpiMaxMdrrWindow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMaxMdrrWindow__MaxCreditSel,
      "CfgRegRxsSpiMaxMdrrWindow__MaxCreditSel",
      AD_CfgRegRxsSpiMaxMdrrWindow, 26, 26, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMaxMdrrWindow__RstCreditAllSat,
      "CfgRegRxsSpiMaxMdrrWindow__RstCreditAllSat",
      AD_CfgRegRxsSpiMaxMdrrWindow, 25, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMaxMdrrWindow__LimitCredit,
      "CfgRegRxsSpiMaxMdrrWindow__LimitCredit",
      AD_CfgRegRxsSpiMaxMdrrWindow, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMaxMdrrWindow__WindowSize,
      "CfgRegRxsSpiMaxMdrrWindow__WindowSize",
      AD_CfgRegRxsSpiMaxMdrrWindow, 23, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMaxMdrrCredit,
      "CfgRegRxsSpiMaxMdrrCredit",
      AD_CfgRegRxsSpiMaxMdrrCredit, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { CfgRegRxsSpiMaxPacketSize,
      "CfgRegRxsSpiMaxPacketSize",
      AD_CfgRegRxsSpiMaxPacketSize, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMaxPacketSize__BurstOverMb2,
      "CfgRegRxsSpiMaxPacketSize__BurstOverMb2",
      AD_CfgRegRxsSpiMaxPacketSize, 18, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiMaxPacketSize__MaxPktSize,
      "CfgRegRxsSpiMaxPacketSize__MaxPktSize",
      AD_CfgRegRxsSpiMaxPacketSize, 15, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsspiInPipeBurstCnt,
      "CfgRegRxsspiInPipeBurstCnt",
      AD_CfgRegRxsspiInPipeBurstCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsspiInPipeBurstCnt__InPipeBurstCntDis,
      "CfgRegRxsspiInPipeBurstCnt__InPipeBurstCntDis",
      AD_CfgRegRxsspiInPipeBurstCnt, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsspiInPipeBurstCnt__InPipeBurstCnt,
      "CfgRegRxsspiInPipeBurstCnt__InPipeBurstCnt",
      AD_CfgRegRxsspiInPipeBurstCnt, 4, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiHMMisc,
      "CfgRegRxsSpiHMMisc",
      AD_CfgRegRxsSpiHMMisc, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiHMMisc__RSPI_BERT_TX_EN,
      "CfgRegRxsSpiHMMisc__RSPI_BERT_TX_EN",
      AD_CfgRegRxsSpiHMMisc, 22, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiHMMisc__RSPI_BERT_RX_EN,
      "CfgRegRxsSpiHMMisc__RSPI_BERT_RX_EN",
      AD_CfgRegRxsSpiHMMisc, 21, 21, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiHMMisc__RSPI_BYPASS_EN,
      "CfgRegRxsSpiHMMisc__RSPI_BYPASS_EN",
      AD_CfgRegRxsSpiHMMisc, 20, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiHMMisc__RSPI_SFI_CLOCK_MODE,
      "CfgRegRxsSpiHMMisc__RSPI_SFI_CLOCK_MODE",
      AD_CfgRegRxsSpiHMMisc, 19, 19, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiHMMisc__RSPI_POWER_DOWN,
      "CfgRegRxsSpiHMMisc__RSPI_POWER_DOWN",
      AD_CfgRegRxsSpiHMMisc, 18, 18, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiHMMisc__RSPI_LOOPBACK,
      "CfgRegRxsSpiHMMisc__RSPI_LOOPBACK",
      AD_CfgRegRxsSpiHMMisc, 17, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWMisc,
      "CfgRegRxsSpiDESKEWMisc",
      AD_CfgRegRxsSpiDESKEWMisc, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWMisc__SpiChShift,
      "CfgRegRxsSpiDESKEWMisc__SpiChShift",
      AD_CfgRegRxsSpiDESKEWMisc, 24, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWMisc__SpiRxMode,
      "CfgRegRxsSpiDESKEWMisc__SpiRxMode",
      AD_CfgRegRxsSpiDESKEWMisc, 7, 7, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWMisc__SpiTxMode,
      "CfgRegRxsSpiDESKEWMisc__SpiTxMode",
      AD_CfgRegRxsSpiDESKEWMisc, 6, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWMisc__SpiTestMode,
      "CfgRegRxsSpiDESKEWMisc__SpiTestMode",
      AD_CfgRegRxsSpiDESKEWMisc, 5, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWMisc__SpiTrainEn,
      "CfgRegRxsSpiDESKEWMisc__SpiTrainEn",
      AD_CfgRegRxsSpiDESKEWMisc, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWMisc__OutOfRangeEn,
      "CfgRegRxsSpiDESKEWMisc__OutOfRangeEn",
      AD_CfgRegRxsSpiDESKEWMisc, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWMisc__RxClearDeskew,
      "CfgRegRxsSpiDESKEWMisc__RxClearDeskew",
      AD_CfgRegRxsSpiDESKEWMisc, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWMisc__BitAlignModeEn,
      "CfgRegRxsSpiDESKEWMisc__BitAlignModeEn",
      AD_CfgRegRxsSpiDESKEWMisc, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWMisc__TxClearDeskew,
      "CfgRegRxsSpiDESKEWMisc__TxClearDeskew",
      AD_CfgRegRxsSpiDESKEWMisc, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWTraPat0,
      "CfgRegRxsSpiDESKEWTraPat0",
      AD_CfgRegRxsSpiDESKEWTraPat0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWTraPat1,
      "CfgRegRxsSpiDESKEWTraPat1",
      AD_CfgRegRxsSpiDESKEWTraPat1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWReg0,
      "CfgRegRxsSpiDESKEWReg0",
      AD_CfgRegRxsSpiDESKEWReg0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDESKEWReg1,
      "CfgRegRxsSpiDESKEWReg1",
      AD_CfgRegRxsSpiDESKEWReg1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiIntLBFifoRdThresh,
      "CfgRegRxsSpiIntLBFifoRdThresh",
      AD_CfgRegRxsSpiIntLBFifoRdThresh, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRsSpiPLLLockDet,
      "StsRsSpiPLLLockDet",
      AD_StsRsSpiPLLLockDet, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRsSpiSkewOutofRange,
      "StsRsSpiSkewOutofRange",
      AD_StsRsSpiSkewOutofRange, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRsSpiTrainAct,
      "StsRsSpiTrainAct",
      AD_StsRsSpiTrainAct, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxsSpiInFifoEopCnt,
      "StsRegRxsSpiInFifoEopCnt",
      AD_StsRegRxsSpiInFifoEopCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxsSpiSopCount,
      "StsRegRxsSpiSopCount",
      AD_StsRegRxsSpiSopCount, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { StsRegRxsSpiEop1Count,
      "StsRegRxsSpiEop1Count",
      AD_StsRegRxsSpiEop1Count, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { StsRegRxsSpiEop2Count,
      "StsRegRxsSpiEop2Count",
      AD_StsRegRxsSpiEop2Count, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { StsRegRxsSpiEopACount,
      "StsRegRxsSpiEopACount",
      AD_StsRegRxsSpiEopACount, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { StsRegRxsSpiTrainingCount,
      "StsRegRxsSpiTrainingCount",
      AD_StsRegRxsSpiTrainingCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxsSpiMdrrCreditCntr,
      "StsRegRxsSpiMdrrCreditCntr",
      AD_StsRegRxsSpiMdrrCreditCntr, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { StsRegRxsSpiPortBurstCntr,
      "StsRegRxsSpiPortBurstCntr",
      AD_StsRegRxsSpiPortBurstCntr, 0, 0, PROP_RW_WHOLE,
      0x4, INST2, 0, 0, 0 },

    { StsRegRxsSpiDiag,
      "StsRegRxsSpiDiag",
      AD_StsRegRxsSpiDiag, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxsSpiPerFetchFifoUFlow,
      "StsRegRxsSpiPerFetchFifoUFlow",
      AD_StsRegRxsSpiPerFetchFifoUFlow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxsSpiOutputFifoUFlow,
      "StsRegRxsSpiOutputFifoUFlow",
      AD_StsRegRxsSpiOutputFifoUFlow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxsShdwCalendarAct,
      "StsRegRxsShdwCalendarAct",
      AD_StsRegRxsShdwCalendarAct, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMemRxsSpiCalPri,
      "CfgMemRxsSpiCalPri",
      AD_CfgMemRxsSpiCalPri, 0, 0, PROP_RW_WHOLE,
      0x4, INST128, 0, 0, 0 },

    { CfgMemRxsSpiCalShadow,
      "CfgMemRxsSpiCalShadow",
      AD_CfgMemRxsSpiCalShadow, 0, 0, PROP_RW_WHOLE,
      0x4, INST128, 0, 0, 0 },

    { CfgRegRxsSpiCalSetup,
      "CfgRegRxsSpiCalSetup",
      AD_CfgRegRxsSpiCalSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCalSetup__ShdwCalL,
      "CfgRegRxsSpiCalSetup__ShdwCalL",
      AD_CfgRegRxsSpiCalSetup, 21, 13, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCalSetup__ShdwCalM,
      "CfgRegRxsSpiCalSetup__ShdwCalM",
      AD_CfgRegRxsSpiCalSetup, 12, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCalSetup__CalL,
      "CfgRegRxsSpiCalSetup__CalL",
      AD_CfgRegRxsSpiCalSetup, 10, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiCalSetup__CalM,
      "CfgRegRxsSpiCalSetup__CalM",
      AD_CfgRegRxsSpiCalSetup, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDip2Thr,
      "CfgRegRxsSpiDip2Thr",
      AD_CfgRegRxsSpiDip2Thr, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDip2Thr__LOSFrmPatThr,
      "CfgRegRxsSpiDip2Thr__LOSFrmPatThr",
      AD_CfgRegRxsSpiDip2Thr, 12, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegRxsSpiDip2Thr__LOSDip2ErrThr,
      "CfgRegRxsSpiDip2Thr__LOSDip2ErrThr",
      AD_CfgRegRxsSpiDip2Thr, 7, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { StsRegRxsSpiDip2ErrCount,
      "StsRegRxsSpiDip2ErrCount",
      AD_StsRegRxsSpiDip2ErrCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxsSpiLosStatus,
      "StsRegRxsSpiLosStatus",
      AD_StsRegRxsSpiLosStatus, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxsSpiInterrupt,
      "StsRegRxsSpiInterrupt",
      AD_StsRegRxsSpiInterrupt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegRxsSpiInterruptMask,
      "StsRegRxsSpiInterruptMask",
      AD_StsRegRxsSpiInterruptMask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRxXauiXmac,
      "CfgRxXauiXmac",
      AD_CfgRxXauiXmac, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRxXauiXmacSopInCnt,
      "StsRxXauiXmacSopInCnt",
      AD_StsRxXauiXmacSopInCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRxXauiXmacEopInCnt,
      "StsRxXauiXmacEopInCnt",
      AD_StsRxXauiXmacEopInCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRxXauiXmacSopOutCnt,
      "StsRxXauiXmacSopOutCnt",
      AD_StsRxXauiXmacSopOutCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRxXauiXmacEopOutCnt,
      "StsRxXauiXmacEopOutCnt",
      AD_StsRxXauiXmacEopOutCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegLsbRxXauiXmacByteCount,
      "StsRegLsbRxXauiXmacByteCount",
      AD_StsRegLsbRxXauiXmacByteCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegMsbRxXauiXmacByteCount,
      "StsRegMsbRxXauiXmacByteCount",
      AD_StsRegMsbRxXauiXmacByteCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxXauiXmacFrames,
      "StsRegRxXauiXmacFrames",
      AD_StsRegRxXauiXmacFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxXauiXmacErroredFrames,
      "StsRegRxXauiXmacErroredFrames",
      AD_StsRegRxXauiXmacErroredFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegRxRSNoPrmbleReplace,
      "CfgRegRxRSNoPrmbleReplace",
      AD_CfgRegRxRSNoPrmbleReplace, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxRSInterrupt,
      "StsRegRxRSInterrupt",
      AD_StsRegRxRSInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegRxRSInterruptMask,
      "StsRegRxRSInterruptMask",
      AD_StsRegRxRSInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDontRemovePreAmble,
      "CfgDontRemovePreAmble",
      AD_CfgDontRemovePreAmble, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxPCSBitOrder,
      "CfgTxPCSBitOrder",
      AD_CfgTxPCSBitOrder, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxPCSLoadX58,
      "CfgTxPCSLoadX58",
      AD_CfgTxPCSLoadX58, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxPCSSeedX58_3,
      "CfgTxPCSSeedX58_3",
      AD_CfgTxPCSSeedX58_3, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxPCSSeedX58_2,
      "CfgTxPCSSeedX58_2",
      AD_CfgTxPCSSeedX58_2, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxPCSSeedX58_1,
      "CfgTxPCSSeedX58_1",
      AD_CfgTxPCSSeedX58_1, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxPCSSeedX58_0,
      "CfgTxPCSSeedX58_0",
      AD_CfgTxPCSSeedX58_0, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxXFIAlign,
      "CfgTxXFIAlign",
      AD_CfgTxXFIAlign, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxXFIAlignChar_3,
      "CfgTxXFIAlignChar_3",
      AD_CfgTxXFIAlignChar_3, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxXFIAlignChar_2,
      "CfgTxXFIAlignChar_2",
      AD_CfgTxXFIAlignChar_2, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxXFIAlignChar_1,
      "CfgTxXFIAlignChar_1",
      AD_CfgTxXFIAlignChar_1, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxXFIAlignChar_0,
      "CfgTxXFIAlignChar_0",
      AD_CfgTxXFIAlignChar_0, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxPCSBitOrder,
      "CfgRxPCSBitOrder",
      AD_CfgRxPCSBitOrder, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxPcsBerTimerVal,
      "CfgRxPcsBerTimerVal",
      AD_CfgRxPcsBerTimerVal, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxPcsRXGFifoFullThr,
      "CfgRxPcsRXGFifoFullThr",
      AD_CfgRxPcsRXGFifoFullThr, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxXFIAlign,
      "CfgRxXFIAlign",
      AD_CfgRxXFIAlign, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxXFIAlignChar_3,
      "CfgRxXFIAlignChar_3",
      AD_CfgRxXFIAlignChar_3, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxXFIAlignChar_2,
      "CfgRxXFIAlignChar_2",
      AD_CfgRxXFIAlignChar_2, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxXFIAlignChar_1,
      "CfgRxXFIAlignChar_1",
      AD_CfgRxXFIAlignChar_1, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxXFIAlignChar_0,
      "CfgRxXFIAlignChar_0",
      AD_CfgRxXFIAlignChar_0, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRxPcsAlignFailInterrupt,
      "StsRxPcsAlignFailInterrupt",
      AD_StsRxPcsAlignFailInterrupt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRxPcsAlignFailInterruptMask,
      "StsRxPcsAlignFailInterruptMask",
      AD_StsRxPcsAlignFailInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRxPcsAlignDone,
      "StsRxPcsAlignDone",
      AD_StsRxPcsAlignDone, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxPCSLoadX58,
      "CfgRxPCSLoadX58",
      AD_CfgRxPCSLoadX58, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxPCSSeedX58_3,
      "CfgRxPCSSeedX58_3",
      AD_CfgRxPCSSeedX58_3, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxPCSSeedX58_2,
      "CfgRxPCSSeedX58_2",
      AD_CfgRxPCSSeedX58_2, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxPCSSeedX58_1,
      "CfgRxPCSSeedX58_1",
      AD_CfgRxPCSSeedX58_1, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRxPCSSeedX58_0,
      "CfgRxPCSSeedX58_0",
      AD_CfgRxPCSSeedX58_0, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgXFIDataBitOrder,
      "CfgXFIDataBitOrder",
      AD_CfgXFIDataBitOrder, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgXFIDataBitOrder__TxXFIDataBitOrder,
      "CfgXFIDataBitOrder__TxXFIDataBitOrder",
      AD_CfgXFIDataBitOrder, 1, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgXFIDataBitOrder__RxXFIDataBitOrder,
      "CfgXFIDataBitOrder__RxXFIDataBitOrder",
      AD_CfgXFIDataBitOrder, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgConsiderRemoteFault,
      "CfgConsiderRemoteFault",
      AD_CfgConsiderRemoteFault, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgConsiderRemoteFault__TxConsiderRemoteFault,
      "CfgConsiderRemoteFault__TxConsiderRemoteFault",
      AD_CfgConsiderRemoteFault, 1, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgConsiderRemoteFault__RxConsiderRemoteFault,
      "CfgConsiderRemoteFault__RxConsiderRemoteFault",
      AD_CfgConsiderRemoteFault, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgRTLChanges,
      "CfgRTLChanges",
      AD_CfgRTLChanges, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRTLChanges__PRPatternGen,
      "CfgRTLChanges__PRPatternGen",
      AD_CfgRTLChanges, 5, 5, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgRTLChanges__BERStateMachine,
      "CfgRTLChanges__BERStateMachine",
      AD_CfgRTLChanges, 4, 4, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgRTLChanges__TxStateMachine,
      "CfgRTLChanges__TxStateMachine",
      AD_CfgRTLChanges, 3, 3, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgRTLChanges__RxStateMachine,
      "CfgRTLChanges__RxStateMachine",
      AD_CfgRTLChanges, 2, 2, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgRTLChanges__TxFault,
      "CfgRTLChanges__TxFault",
      AD_CfgRTLChanges, 1, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgRTLChanges__RxFault,
      "CfgRTLChanges__RxFault",
      AD_CfgRTLChanges, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { StsRxSyncStatusChangedInterrupt,
      "StsRxSyncStatusChangedInterrupt",
      AD_StsRxSyncStatusChangedInterrupt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRxSyncStatusChangedInterruptMask,
      "StsRxSyncStatusChangedInterruptMask",
      AD_StsRxSyncStatusChangedInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRegTxMACModes,
      "CfgRegTxMACModes",
      AD_CfgRegTxMACModes, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__Reserved,
      "CfgRegTxMACModes__Reserved",
      AD_CfgRegTxMACModes, 31, 20, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxDICOverWISEn,
      "CfgRegTxMACModes__TxDICOverWISEn",
      AD_CfgRegTxMACModes, 19, 19, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxLocalFaultInsertEn,
      "CfgRegTxMACModes__TxLocalFaultInsertEn",
      AD_CfgRegTxMACModes, 18, 18, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxProgIPGEn,
      "CfgRegTxMACModes__TxProgIPGEn",
      AD_CfgRegTxMACModes, 17, 17, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxRSNoSCC,
      "CfgRegTxMACModes__TxRSNoSCC",
      AD_CfgRegTxMACModes, 16, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxWISEn,
      "CfgRegTxMACModes__TxWISEn",
      AD_CfgRegTxMACModes, 15, 15, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxIpg8to11,
      "CfgRegTxMACModes__TxIpg8to11",
      AD_CfgRegTxMACModes, 14, 14, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxTransparentMode,
      "CfgRegTxMACModes__TxTransparentMode",
      AD_CfgRegTxMACModes, 13, 13, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxUCastDAPauseEn,
      "CfgRegTxMACModes__TxUCastDAPauseEn",
      AD_CfgRegTxMACModes, 12, 12, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxReXmittSPEn,
      "CfgRegTxMACModes__TxReXmittSPEn",
      AD_CfgRegTxMACModes, 11, 11, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxDeassertSPDis,
      "CfgRegTxMACModes__TxDeassertSPDis",
      AD_CfgRegTxMACModes, 10, 10, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxGenPauseFrm,
      "CfgRegTxMACModes__TxGenPauseFrm",
      AD_CfgRegTxMACModes, 9, 9, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxPauseTimerDis,
      "CfgRegTxMACModes__TxPauseTimerDis",
      AD_CfgRegTxMACModes, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxSendPauseMode,
      "CfgRegTxMACModes__TxSendPauseMode",
      AD_CfgRegTxMACModes, 7, 6, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxSAInsertEn,
      "CfgRegTxMACModes__TxSAInsertEn",
      AD_CfgRegTxMACModes, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxDAInsertEn,
      "CfgRegTxMACModes__TxDAInsertEn",
      AD_CfgRegTxMACModes, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxInsertPadEn,
      "CfgRegTxMACModes__TxInsertPadEn",
      AD_CfgRegTxMACModes, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxAppendCrcEn,
      "CfgRegTxMACModes__TxAppendCrcEn",
      AD_CfgRegTxMACModes, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxOversizeFEn,
      "CfgRegTxMACModes__TxOversizeFEn",
      AD_CfgRegTxMACModes, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMACModes__TxDicEn,
      "CfgRegTxMACModes__TxDicEn",
      AD_CfgRegTxMACModes, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxMaxFSize,
      "CfgRegTxMaxFSize",
      AD_CfgRegTxMaxFSize, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxDAValLSB,
      "CfgRegTxDAValLSB",
      AD_CfgRegTxDAValLSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxDAValMSB,
      "CfgRegTxDAValMSB",
      AD_CfgRegTxDAValMSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxSAValLSB,
      "CfgRegTxSAValLSB",
      AD_CfgRegTxSAValLSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxSAValMSB,
      "CfgRegTxSAValMSB",
      AD_CfgRegTxSAValMSB, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxPauseTimerValue,
      "CfgRegTxPauseTimerValue",
      AD_CfgRegTxPauseTimerValue, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxDebugEopCharacter,
      "CfgTxDebugEopCharacter",
      AD_CfgTxDebugEopCharacter, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSFaultTrafficBP,
      "CfgRegTxRSFaultTrafficBP",
      AD_CfgRegTxRSFaultTrafficBP, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSLocalFaultEn,
      "CfgRegTxRSLocalFaultEn",
      AD_CfgRegTxRSLocalFaultEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSLocalFaultMode,
      "CfgRegTxRSLocalFaultMode",
      AD_CfgRegTxRSLocalFaultMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSRemoteFaultEn,
      "CfgRegTxRSRemoteFaultEn",
      AD_CfgRegTxRSRemoteFaultEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSLinkFaultRecoveryMode,
      "CfgRegTxRSLinkFaultRecoveryMode",
      AD_CfgRegTxRSLinkFaultRecoveryMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSCPUFaultRecovery,
      "CfgRegTxRSCPUFaultRecovery",
      AD_CfgRegTxRSCPUFaultRecovery, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgProgIPGCount,
      "CfgProgIPGCount",
      AD_CfgProgIPGCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegLsbTxGoodByteCount,
      "StsRegLsbTxGoodByteCount",
      AD_StsRegLsbTxGoodByteCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegMsbTxGoodByteCount,
      "StsRegMsbTxGoodByteCount",
      AD_StsRegMsbTxGoodByteCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegLsbTxErrorByteCount,
      "StsRegLsbTxErrorByteCount",
      AD_StsRegLsbTxErrorByteCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegMsbTxErrorByteCount,
      "StsRegMsbTxErrorByteCount",
      AD_StsRegMsbTxErrorByteCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegGoodTxFrames,
      "StsRegGoodTxFrames",
      AD_StsRegGoodTxFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxBCASTFrames,
      "StsRegTxBCASTFrames",
      AD_StsRegTxBCASTFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxMCASTFrames,
      "StsRegTxMCASTFrames",
      AD_StsRegTxMCASTFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxControlFrames,
      "StsRegTxControlFrames",
      AD_StsRegTxControlFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxVLANFrames,
      "StsRegTxVLANFrames",
      AD_StsRegTxVLANFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxPauseFrames,
      "StsRegTxPauseFrames",
      AD_StsRegTxPauseFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTx64BFrames,
      "StsRegTx64BFrames",
      AD_StsRegTx64BFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTx65to127BFrames,
      "StsRegTx65to127BFrames",
      AD_StsRegTx65to127BFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTx128to255BFrames,
      "StsRegTx128to255BFrames",
      AD_StsRegTx128to255BFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTx256to511BFrames,
      "StsRegTx256to511BFrames",
      AD_StsRegTx256to511BFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTx512to1023BFrames,
      "StsRegTx512to1023BFrames",
      AD_StsRegTx512to1023BFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTx1024to1518BFrames,
      "StsRegTx1024to1518BFrames",
      AD_StsRegTx1024to1518BFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxOver1518BFrames,
      "StsRegTxOver1518BFrames",
      AD_StsRegTxOver1518BFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxErroredFrames,
      "StsRegTxErroredFrames",
      AD_StsRegTxErroredFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxFilterDropFrames,
      "StsRegTxFilterDropFrames",
      AD_StsRegTxFilterDropFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxMcastFilterDrop,
      "StsRegTxMcastFilterDrop",
      AD_StsRegTxMcastFilterDrop, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxBcastFilterDrop,
      "StsRegTxBcastFilterDrop",
      AD_StsRegTxBcastFilterDrop, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxTooLongFrames,
      "StsRegTxTooLongFrames",
      AD_StsRegTxTooLongFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxDroppedFrames,
      "StsRegTxDroppedFrames",
      AD_StsRegTxDroppedFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxJumboFrames,
      "StsRegTxJumboFrames",
      AD_StsRegTxJumboFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxFCSError,
      "StsRegTxFCSError",
      AD_StsRegTxFCSError, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxMACInterrupt,
      "StsRegTxMACInterrupt",
      AD_StsRegTxMACInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxMACInterruptMask,
      "StsRegTxMACInterruptMask",
      AD_StsRegTxMACInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxDiagPort,
      "StsRegTxDiagPort",
      AD_StsRegTxDiagPort, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg0,
      "CfgTxVlanCtrlEtherTypeReg0",
      AD_CfgTxVlanCtrlEtherTypeReg0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg0__CfgEtherTypeIeee802dot3,
      "CfgTxVlanCtrlEtherTypeReg0__CfgEtherTypeIeee802dot3",
      AD_CfgTxVlanCtrlEtherTypeReg0, 31, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg0__CfgEtherTypeExtremeNetworks,
      "CfgTxVlanCtrlEtherTypeReg0__CfgEtherTypeExtremeNetworks",
      AD_CfgTxVlanCtrlEtherTypeReg0, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg1,
      "CfgTxVlanCtrlEtherTypeReg1",
      AD_CfgTxVlanCtrlEtherTypeReg1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg1__CfgEtherTypeOthers1,
      "CfgTxVlanCtrlEtherTypeReg1__CfgEtherTypeOthers1",
      AD_CfgTxVlanCtrlEtherTypeReg1, 31, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg1__CfgEtherTypeOthers2,
      "CfgTxVlanCtrlEtherTypeReg1__CfgEtherTypeOthers2",
      AD_CfgTxVlanCtrlEtherTypeReg1, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg2,
      "CfgTxVlanCtrlEtherTypeReg2",
      AD_CfgTxVlanCtrlEtherTypeReg2, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg2__CfgEtherTypeOthers3,
      "CfgTxVlanCtrlEtherTypeReg2__CfgEtherTypeOthers3",
      AD_CfgTxVlanCtrlEtherTypeReg2, 31, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg2__CfgEtherTypeOthers4,
      "CfgTxVlanCtrlEtherTypeReg2__CfgEtherTypeOthers4",
      AD_CfgTxVlanCtrlEtherTypeReg2, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg3,
      "CfgTxVlanCtrlEtherTypeReg3",
      AD_CfgTxVlanCtrlEtherTypeReg3, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg3__CfgEtherTypeOthers5,
      "CfgTxVlanCtrlEtherTypeReg3__CfgEtherTypeOthers5",
      AD_CfgTxVlanCtrlEtherTypeReg3, 31, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg3__CfgEtherTypeOthers6,
      "CfgTxVlanCtrlEtherTypeReg3__CfgEtherTypeOthers6",
      AD_CfgTxVlanCtrlEtherTypeReg3, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg4,
      "CfgTxVlanCtrlEtherTypeReg4",
      AD_CfgTxVlanCtrlEtherTypeReg4, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg4__CfgEtherTypeOthers7,
      "CfgTxVlanCtrlEtherTypeReg4__CfgEtherTypeOthers7",
      AD_CfgTxVlanCtrlEtherTypeReg4, 31, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg4__CfgEtherTypeOthers8,
      "CfgTxVlanCtrlEtherTypeReg4__CfgEtherTypeOthers8",
      AD_CfgTxVlanCtrlEtherTypeReg4, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg5,
      "CfgTxVlanCtrlEtherTypeReg5",
      AD_CfgTxVlanCtrlEtherTypeReg5, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg5__CfgEtherTypeOthers9,
      "CfgTxVlanCtrlEtherTypeReg5__CfgEtherTypeOthers9",
      AD_CfgTxVlanCtrlEtherTypeReg5, 31, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg5__CfgEtherTypeOthers10,
      "CfgTxVlanCtrlEtherTypeReg5__CfgEtherTypeOthers10",
      AD_CfgTxVlanCtrlEtherTypeReg5, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg6,
      "CfgTxVlanCtrlEtherTypeReg6",
      AD_CfgTxVlanCtrlEtherTypeReg6, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg6__CfgEtherTypeOthers11,
      "CfgTxVlanCtrlEtherTypeReg6__CfgEtherTypeOthers11",
      AD_CfgTxVlanCtrlEtherTypeReg6, 31, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg6__CfgEtherTypeOthers12,
      "CfgTxVlanCtrlEtherTypeReg6__CfgEtherTypeOthers12",
      AD_CfgTxVlanCtrlEtherTypeReg6, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg7,
      "CfgTxVlanCtrlEtherTypeReg7",
      AD_CfgTxVlanCtrlEtherTypeReg7, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg7__CfgEtherTypeOthers13,
      "CfgTxVlanCtrlEtherTypeReg7__CfgEtherTypeOthers13",
      AD_CfgTxVlanCtrlEtherTypeReg7, 31, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanCtrlEtherTypeReg7__CfgEtherTypeOthers14,
      "CfgTxVlanCtrlEtherTypeReg7__CfgEtherTypeOthers14",
      AD_CfgTxVlanCtrlEtherTypeReg7, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMplsTypeReg,
      "CfgMplsTypeReg",
      AD_CfgMplsTypeReg, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMplsTypeReg__CfgMplsType0,
      "CfgMplsTypeReg__CfgMplsType0",
      AD_CfgMplsTypeReg, 31, 16, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMplsTypeReg__CfgMplsType1,
      "CfgMplsTypeReg__CfgMplsType1",
      AD_CfgMplsTypeReg, 15, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgMplsStyle,
      "CfgMplsStyle",
      AD_CfgMplsStyle, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDefaultVlanCtrlTblReg0,
      "CfgDefaultVlanCtrlTblReg0",
      AD_CfgDefaultVlanCtrlTblReg0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDefaultVlanCtrlTblReg0__CfgDefaultTagEn,
      "CfgDefaultVlanCtrlTblReg0__CfgDefaultTagEn",
      AD_CfgDefaultVlanCtrlTblReg0, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDefaultVlanCtrlTblReg0__CfgDefaultTagOperation,
      "CfgDefaultVlanCtrlTblReg0__CfgDefaultTagOperation",
      AD_CfgDefaultVlanCtrlTblReg0, 2, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgDefaultVlanCtrlTblReg1,
      "CfgDefaultVlanCtrlTblReg1",
      AD_CfgDefaultVlanCtrlTblReg1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWr4096x12TxVlanCtrlTblRam,
      "CfgWr4096x12TxVlanCtrlTblRam",
      AD_CfgWr4096x12TxVlanCtrlTblRam, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWr4096x12TxVlanCtrlTblRam__CfgWrEnTxVlanCtrlTblRam,
      "CfgWr4096x12TxVlanCtrlTblRam__CfgWrEnTxVlanCtrlTblRam",
      AD_CfgWr4096x12TxVlanCtrlTblRam, 24, 24, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWr4096x12TxVlanCtrlTblRam__CfgWrAddrTxVlanCtrlTblRam,
      "CfgWr4096x12TxVlanCtrlTblRam__CfgWrAddrTxVlanCtrlTblRam",
      AD_CfgWr4096x12TxVlanCtrlTblRam, 23, 12, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWr4096x12TxVlanCtrlTblRam__CfgWrDataTxVlanCtrlTblRam,
      "CfgWr4096x12TxVlanCtrlTblRam__CfgWrDataTxVlanCtrlTblRam",
      AD_CfgWr4096x12TxVlanCtrlTblRam, 11, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgByPassEccCheckfortxvlan4kram,
      "CfgByPassEccCheckfortxvlan4kram",
      AD_CfgByPassEccCheckfortxvlan4kram, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgInsertVplsForConflict,
      "CfgInsertVplsForConflict",
      AD_CfgInsertVplsForConflict, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDisableMplsEncoding,
      "CfgDisableMplsEncoding",
      AD_CfgDisableMplsEncoding, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRd4096x12TxVlanCtrlTblRam,
      "CfgRd4096x12TxVlanCtrlTblRam",
      AD_CfgRd4096x12TxVlanCtrlTblRam, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRd4096x12TxVlanCtrlTblRam__CfgRdEnTxVlanCtrlTblRam,
      "CfgRd4096x12TxVlanCtrlTblRam__CfgRdEnTxVlanCtrlTblRam",
      AD_CfgRd4096x12TxVlanCtrlTblRam, 12, 12, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRd4096x12TxVlanCtrlTblRam__CfgRdAddrTxVlanCtrlTblRam,
      "CfgRd4096x12TxVlanCtrlTblRam__CfgRdAddrTxVlanCtrlTblRam",
      AD_CfgRd4096x12TxVlanCtrlTblRam, 11, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { StsRdDataTxVlanCtrlTblRamReg,
      "StsRdDataTxVlanCtrlTblRamReg",
      AD_StsRdDataTxVlanCtrlTblRamReg, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWr256x32TxVlanTagRamReg0,
      "CfgWr256x32TxVlanTagRamReg0",
      AD_CfgWr256x32TxVlanTagRamReg0, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgWr256x32TxVlanTagRamReg0__CfgWrEnVlanTagRam,
      "CfgWr256x32TxVlanTagRamReg0__CfgWrEnVlanTagRam",
      AD_CfgWr256x32TxVlanTagRamReg0, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWr256x32TxVlanTagRamReg0__CfgWrAddrVlanTagRam,
      "CfgWr256x32TxVlanTagRamReg0__CfgWrAddrVlanTagRam",
      AD_CfgWr256x32TxVlanTagRamReg0, 7, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgWr256x32TxVlanTagRamReg1,
      "CfgWr256x32TxVlanTagRamReg1",
      AD_CfgWr256x32TxVlanTagRamReg1, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRd256x32TxVlanTagRamReg,
      "CfgRd256x32TxVlanTagRamReg",
      AD_CfgRd256x32TxVlanTagRamReg, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRd256x32TxVlanTagRamReg__CfgRdEnVlanTagRam,
      "CfgRd256x32TxVlanTagRamReg__CfgRdEnVlanTagRam",
      AD_CfgRd256x32TxVlanTagRamReg, 8, 8, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRd256x32TxVlanTagRamReg__CfgRdAddrVlanTagRam,
      "CfgRd256x32TxVlanTagRamReg__CfgRdAddrVlanTagRam",
      AD_CfgRd256x32TxVlanTagRamReg, 7, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { StsRdDataVlanTagRamReg,
      "StsRdDataVlanTagRamReg",
      AD_StsRdDataVlanTagRamReg, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxVlanDontStripOffEfh,
      "CfgTxVlanDontStripOffEfh",
      AD_CfgTxVlanDontStripOffEfh, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgByPassFcsErrChk,
      "CfgByPassFcsErrChk",
      AD_CfgByPassFcsErrChk, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDisableEfh,
      "CfgDisableEfh",
      AD_CfgDisableEfh, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegUnderRunIntr,
      "StsRegUnderRunIntr",
      AD_StsRegUnderRunIntr, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegUnderRunIntrMask,
      "StsRegUnderRunIntrMask",
      AD_StsRegUnderRunIntrMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTxVlanCtrlSopInCnt,
      "StsTxVlanCtrlSopInCnt",
      AD_StsTxVlanCtrlSopInCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTxVlanCtrlEopInCnt,
      "StsTxVlanCtrlEopInCnt",
      AD_StsTxVlanCtrlEopInCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTxVlanCtrlSopOutCnt,
      "StsTxVlanCtrlSopOutCnt",
      AD_StsTxVlanCtrlSopOutCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTxVlanCtrlEopOutCnt,
      "StsTxVlanCtrlEopOutCnt",
      AD_StsTxVlanCtrlEopOutCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMPLSUnicastFrameCount,
      "StsMPLSUnicastFrameCount",
      AD_StsMPLSUnicastFrameCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMPLSMulticastFrameCount,
      "StsMPLSMulticastFrameCount",
      AD_StsMPLSMulticastFrameCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsMPLSFrameOctetsEgressed,
      "StsMPLSFrameOctetsEgressed",
      AD_StsMPLSFrameOctetsEgressed, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsNoVLANTagFrameCount,
      "StsNoVLANTagFrameCount",
      AD_StsNoVLANTagFrameCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsSingleVLANTagFrameCount,
      "StsSingleVLANTagFrameCount",
      AD_StsSingleVLANTagFrameCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDoubleVLANTagFrameCount,
      "StsDoubleVLANTagFrameCount",
      AD_StsDoubleVLANTagFrameCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsVLANControlTableFrameCount,
      "StsVLANControlTableFrameCount",
      AD_StsVLANControlTableFrameCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsDefaultVLANControlTableFrameCount,
      "StsDefaultVLANControlTableFrameCount",
      AD_StsDefaultVLANControlTableFrameCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsVLANControlTableTagOperationFrameCount,
      "StsVLANControlTableTagOperationFrameCount",
      AD_StsVLANControlTableTagOperationFrameCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsEfhTagOperationFrameCount,
      "StsEfhTagOperationFrameCount",
      AD_StsEfhTagOperationFrameCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsPreservedFrameCount,
      "StsPreservedFrameCount",
      AD_StsPreservedFrameCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTxVlanEccErrorInterrupt,
      "StsTxVlanEccErrorInterrupt",
      AD_StsTxVlanEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTxVlanEccErrorInterruptMask,
      "StsTxVlanEccErrorInterruptMask",
      AD_StsTxVlanEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTxVlanEccSingleErrorInterrupt,
      "StsTxVlanEccSingleErrorInterrupt",
      AD_StsTxVlanEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTxVlanEccSingleErrorInterruptMask,
      "StsTxVlanEccSingleErrorInterruptMask",
      AD_StsTxVlanEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTxVlanEccDoubleErrorInterrupt,
      "StsTxVlanEccDoubleErrorInterrupt",
      AD_StsTxVlanEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsTxVlanEccDoubleErrorInterruptMask,
      "StsTxVlanEccDoubleErrorInterruptMask",
      AD_StsTxVlanEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxMemMgrCrcChkDis,
      "CfgTxMemMgrCrcChkDis",
      AD_CfgTxMemMgrCrcChkDis, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrRdDis,
      "CfgTxMemMgrRdDis",
      AD_CfgTxMemMgrRdDis, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrECCChkDis,
      "CfgTxMemMgrECCChkDis",
      AD_CfgTxMemMgrECCChkDis, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrTailDropEn,
      "CfgTxMemMgrTailDropEn",
      AD_CfgTxMemMgrTailDropEn, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCrcErrPktDropDis,
      "CfgTxMemMgrCrcErrPktDropDis",
      AD_CfgTxMemMgrCrcErrPktDropDis, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrAEopErrPktDropDis,
      "CfgTxMemMgrAEopErrPktDropDis",
      AD_CfgTxMemMgrAEopErrPktDropDis, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrNonPktModeONThrsh,
      "CfgTxMemMgrNonPktModeONThrsh",
      AD_CfgTxMemMgrNonPktModeONThrsh, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrNonPktModeOFFThrsh,
      "CfgTxMemMgrNonPktModeOFFThrsh",
      AD_CfgTxMemMgrNonPktModeOFFThrsh, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrReadTimerValue,
      "CfgTxMemMgrReadTimerValue",
      AD_CfgTxMemMgrReadTimerValue, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEgrPktCnt,
      "StsTxMemMgrEgrPktCnt",
      AD_StsTxMemMgrEgrPktCnt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrDropPktCnt,
      "StsTxMemMgrDropPktCnt",
      AD_StsTxMemMgrDropPktCnt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxVlanCtrlPktCrcErrCnt,
      "StsTxVlanCtrlPktCrcErrCnt",
      AD_StsTxVlanCtrlPktCrcErrCnt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsEgressSpiErrDropCnt,
      "StsEgressSpiErrDropCnt",
      AD_StsEgressSpiErrDropCnt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrOneLinePktsDropedCnt,
      "StsTxMemMgrOneLinePktsDropedCnt",
      AD_StsTxMemMgrOneLinePktsDropedCnt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxVlanCtrlEfhFcsErrCnt,
      "StsTxVlanCtrlEfhFcsErrCnt",
      AD_StsTxVlanCtrlEfhFcsErrCnt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgDontDropRedIdMisMatchPkts,
      "CfgDontDropRedIdMisMatchPkts",
      AD_CfgDontDropRedIdMisMatchPkts, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgRedHawkIdMatchReg,
      "CfgRedHawkIdMatchReg",
      AD_CfgRedHawkIdMatchReg, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsRedHawkIdMisMatchCnt,
      "StsRedHawkIdMisMatchCnt",
      AD_StsRedHawkIdMisMatchCnt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEccErrorInterrupt,
      "StsTxMemMgrEccErrorInterrupt",
      AD_StsTxMemMgrEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEccErrorInterruptMask,
      "StsTxMemMgrEccErrorInterruptMask",
      AD_StsTxMemMgrEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEccSingleErrorInterrupt,
      "StsTxMemMgrEccSingleErrorInterrupt",
      AD_StsTxMemMgrEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEccSingleErrorInterruptMask,
      "StsTxMemMgrEccSingleErrorInterruptMask",
      AD_StsTxMemMgrEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEccDoubleErrorInterrupt,
      "StsTxMemMgrEccDoubleErrorInterrupt",
      AD_StsTxMemMgrEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEccDoubleErrorInterruptMask,
      "StsTxMemMgrEccDoubleErrorInterruptMask",
      AD_StsTxMemMgrEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrWritePointer,
      "StsTxMemMgrWritePointer",
      AD_StsTxMemMgrWritePointer, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrReadPointer,
      "StsTxMemMgrReadPointer",
      AD_StsTxMemMgrReadPointer, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrCommitPointer,
      "StsTxMemMgrCommitPointer",
      AD_StsTxMemMgrCommitPointer, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUAccess,
      "CfgTxMemMgrCPUAccess",
      AD_CfgTxMemMgrCPUAccess, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUAccess__CPUCommitPtrSet,
      "CfgTxMemMgrCPUAccess__CPUCommitPtrSet",
      AD_CfgTxMemMgrCPUAccess, 3, 3, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUAccess__CPURead,
      "CfgTxMemMgrCPUAccess__CPURead",
      AD_CfgTxMemMgrCPUAccess, 2, 2, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUAccess__CPUWrite,
      "CfgTxMemMgrCPUAccess__CPUWrite",
      AD_CfgTxMemMgrCPUAccess, 1, 1, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUAccess__CPUAccessEn,
      "CfgTxMemMgrCPUAccess__CPUAccessEn",
      AD_CfgTxMemMgrCPUAccess, 0, 0, PROP_RW,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUWriteAddress,
      "CfgTxMemMgrCPUWriteAddress",
      AD_CfgTxMemMgrCPUWriteAddress, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUReadAddress,
      "CfgTxMemMgrCPUReadAddress",
      AD_CfgTxMemMgrCPUReadAddress, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUCommitPointer,
      "CfgTxMemMgrCPUCommitPointer",
      AD_CfgTxMemMgrCPUCommitPointer, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUWriteData_0,
      "CfgTxMemMgrCPUWriteData_0",
      AD_CfgTxMemMgrCPUWriteData_0, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUWriteData_1,
      "CfgTxMemMgrCPUWriteData_1",
      AD_CfgTxMemMgrCPUWriteData_1, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUWriteData_2,
      "CfgTxMemMgrCPUWriteData_2",
      AD_CfgTxMemMgrCPUWriteData_2, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUWriteData_3,
      "CfgTxMemMgrCPUWriteData_3",
      AD_CfgTxMemMgrCPUWriteData_3, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrCPUWriteData_4,
      "CfgTxMemMgrCPUWriteData_4",
      AD_CfgTxMemMgrCPUWriteData_4, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrCPUReadData_0,
      "StsTxMemMgrCPUReadData_0",
      AD_StsTxMemMgrCPUReadData_0, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrCPUReadData_1,
      "StsTxMemMgrCPUReadData_1",
      AD_StsTxMemMgrCPUReadData_1, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrCPUReadData_2,
      "StsTxMemMgrCPUReadData_2",
      AD_StsTxMemMgrCPUReadData_2, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrCPUReadData_3,
      "StsTxMemMgrCPUReadData_3",
      AD_StsTxMemMgrCPUReadData_3, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrCPUReadData_4,
      "StsTxMemMgrCPUReadData_4",
      AD_StsTxMemMgrCPUReadData_4, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgTxMemMgrBypassFcsChk,
      "CfgTxMemMgrBypassFcsChk",
      AD_CfgTxMemMgrBypassFcsChk, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrMTUFifoOverflowInterrupt,
      "StsTxMemMgrMTUFifoOverflowInterrupt",
      AD_StsTxMemMgrMTUFifoOverflowInterrupt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrMTUFifoOverflowInterruptMask,
      "StsTxMemMgrMTUFifoOverflowInterruptMask",
      AD_StsTxMemMgrMTUFifoOverflowInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrMTUFifoUnderflowInterrupt,
      "StsTxMemMgrMTUFifoUnderflowInterrupt",
      AD_StsTxMemMgrMTUFifoUnderflowInterrupt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrMTUFifoUnderflowInterruptMask,
      "StsTxMemMgrMTUFifoUnderflowInterruptMask",
      AD_StsTxMemMgrMTUFifoUnderflowInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEFHFifoOverflowInterrupt,
      "StsTxMemMgrEFHFifoOverflowInterrupt",
      AD_StsTxMemMgrEFHFifoOverflowInterrupt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEFHFifoOverflowInterruptMask,
      "StsTxMemMgrEFHFifoOverflowInterruptMask",
      AD_StsTxMemMgrEFHFifoOverflowInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEFHFifoUnderflowInterrupt,
      "StsTxMemMgrEFHFifoUnderflowInterrupt",
      AD_StsTxMemMgrEFHFifoUnderflowInterrupt, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { StsTxMemMgrEFHFifoUnderflowInterruptMask,
      "StsTxMemMgrEFHFifoUnderflowInterruptMask",
      AD_StsTxMemMgrEFHFifoUnderflowInterruptMask, 0, 0, PROP_RW_WHOLE,
      0x400, INST2, 0, 0, 0 },

    { CfgEgressHeaderBigEndian_P0,
      "CfgEgressHeaderBigEndian_P0",
      AD_CfgEgressHeaderBigEndian_P0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgEgressHeaderBigEndian_P1,
      "CfgEgressHeaderBigEndian_P1",
      AD_CfgEgressHeaderBigEndian_P1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemInsertHdr_P0,
      "CfgTxMemInsertHdr_P0",
      AD_CfgTxMemInsertHdr_P0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemHdrValMSB_P0,
      "CfgTxMemHdrValMSB_P0",
      AD_CfgTxMemHdrValMSB_P0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemHdrValLSB_P0,
      "CfgTxMemHdrValLSB_P0",
      AD_CfgTxMemHdrValLSB_P0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemInsertHdr_P1,
      "CfgTxMemInsertHdr_P1",
      AD_CfgTxMemInsertHdr_P1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgInputFrmNpuIsPED_P0,
      "CfgInputFrmNpuIsPED_P0",
      AD_CfgInputFrmNpuIsPED_P0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgInputFrmNpuIsPED_P1,
      "CfgInputFrmNpuIsPED_P1",
      AD_CfgInputFrmNpuIsPED_P1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemHdrValMSB_P1,
      "CfgTxMemHdrValMSB_P1",
      AD_CfgTxMemHdrValMSB_P1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemHdrValLSB_P1,
      "CfgTxMemHdrValLSB_P1",
      AD_CfgTxMemHdrValLSB_P1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemMgrMaxPktSzPrt0,
      "CfgTxMemMgrMaxPktSzPrt0",
      AD_CfgTxMemMgrMaxPktSzPrt0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemMgrMaxPktSzPrt1,
      "CfgTxMemMgrMaxPktSzPrt1",
      AD_CfgTxMemMgrMaxPktSzPrt1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemMgrMinPktSzPrt0,
      "CfgTxMemMgrMinPktSzPrt0",
      AD_CfgTxMemMgrMinPktSzPrt0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemMgrMinPktSzPrt1,
      "CfgTxMemMgrMinPktSzPrt1",
      AD_CfgTxMemMgrMinPktSzPrt1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemMgrDisMaxPktSzFilterPrt0,
      "CfgTxMemMgrDisMaxPktSzFilterPrt0",
      AD_CfgTxMemMgrDisMaxPktSzFilterPrt0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemMgrDisMaxPktSzFilterPrt1,
      "CfgTxMemMgrDisMaxPktSzFilterPrt1",
      AD_CfgTxMemMgrDisMaxPktSzFilterPrt1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemMgrDisMinPktSzFilterPrt0,
      "CfgTxMemMgrDisMinPktSzFilterPrt0",
      AD_CfgTxMemMgrDisMinPktSzFilterPrt0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxMemMgrDisMinPktSzFilterPrt1,
      "CfgTxMemMgrDisMinPktSzFilterPrt1",
      AD_CfgTxMemMgrDisMinPktSzFilterPrt1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsWidConSopEopSameLineDropCntP0,
      "StsWidConSopEopSameLineDropCntP0",
      AD_StsWidConSopEopSameLineDropCntP0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsWidConSopEopSameLineDropCntP1,
      "StsWidConSopEopSameLineDropCntP1",
      AD_StsWidConSopEopSameLineDropCntP1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxMemMgrSPIMaxSzPktDrpCntPrt0,
      "StsTxMemMgrSPIMaxSzPktDrpCntPrt0",
      AD_StsTxMemMgrSPIMaxSzPktDrpCntPrt0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxMemMgrSPIMaxSzPktDrpCntPrt1,
      "StsTxMemMgrSPIMaxSzPktDrpCntPrt1",
      AD_StsTxMemMgrSPIMaxSzPktDrpCntPrt1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxMemMgrSPIMinSzPktDrpCntPrt0,
      "StsTxMemMgrSPIMinSzPktDrpCntPrt0",
      AD_StsTxMemMgrSPIMinSzPktDrpCntPrt0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxMemMgrSPIMinSzPktDrpCntPrt1,
      "StsTxMemMgrSPIMinSzPktDrpCntPrt1",
      AD_StsTxMemMgrSPIMinSzPktDrpCntPrt1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgCpuToLineEccChkDis,
      "CfgCpuToLineEccChkDis",
      AD_CfgCpuToLineEccChkDis, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineBusEn,
      "CfgCpuToLineBusEn",
      AD_CfgCpuToLineBusEn, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineFullPacketMode,
      "CfgCpuToLineFullPacketMode",
      AD_CfgCpuToLineFullPacketMode, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineDisableRead,
      "CfgCpuToLineDisableRead",
      AD_CfgCpuToLineDisableRead, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineCpuWrData0,
      "CfgCpuToLineCpuWrData0",
      AD_CfgCpuToLineCpuWrData0, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineCpuWrData1,
      "CfgCpuToLineCpuWrData1",
      AD_CfgCpuToLineCpuWrData1, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineCpuWrData2,
      "CfgCpuToLineCpuWrData2",
      AD_CfgCpuToLineCpuWrData2, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineCpuWrDataDone,
      "CfgCpuToLineCpuWrDataDone",
      AD_CfgCpuToLineCpuWrDataDone, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineCpuDataRd,
      "StsCpuToLineCpuDataRd",
      AD_StsCpuToLineCpuDataRd, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineCpuRxFifoFull,
      "StsCpuToLineCpuRxFifoFull",
      AD_StsCpuToLineCpuRxFifoFull, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineCpuRxFifoEmpty,
      "StsCpuToLineCpuRxFifoEmpty",
      AD_StsCpuToLineCpuRxFifoEmpty, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineReadOnThresh,
      "CfgCpuToLineReadOnThresh",
      AD_CfgCpuToLineReadOnThresh, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineReadOffThresh,
      "CfgCpuToLineReadOffThresh",
      AD_CfgCpuToLineReadOffThresh, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineEccErrorInterrupt,
      "StsCpuToLineEccErrorInterrupt",
      AD_StsCpuToLineEccErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineEccErrorInterruptMask,
      "StsCpuToLineEccErrorInterruptMask",
      AD_StsCpuToLineEccErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineEccSingleErrorInterrupt,
      "StsCpuToLineEccSingleErrorInterrupt",
      AD_StsCpuToLineEccSingleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineEccSingleErrorInterruptMask,
      "StsCpuToLineEccSingleErrorInterruptMask",
      AD_StsCpuToLineEccSingleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineEccDoubleErrorInterrupt,
      "StsCpuToLineEccDoubleErrorInterrupt",
      AD_StsCpuToLineEccDoubleErrorInterrupt, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineEccDoubleErrorInterruptMask,
      "StsCpuToLineEccDoubleErrorInterruptMask",
      AD_StsCpuToLineEccDoubleErrorInterruptMask, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLinePktDropEn,
      "CfgCpuToLinePktDropEn",
      AD_CfgCpuToLinePktDropEn, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineFifoTailDropEn,
      "CfgCpuToLineFifoTailDropEn",
      AD_CfgCpuToLineFifoTailDropEn, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgCpuToLineReadTimerValue,
      "CfgCpuToLineReadTimerValue",
      AD_CfgCpuToLineReadTimerValue, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineDropPktCnt,
      "StsCpuToLineDropPktCnt",
      AD_StsCpuToLineDropPktCnt, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineWritePointer,
      "StsCpuToLineWritePointer",
      AD_StsCpuToLineWritePointer, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineReadPointer,
      "StsCpuToLineReadPointer",
      AD_StsCpuToLineReadPointer, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { StsCpuToLineCommitPointer,
      "StsCpuToLineCommitPointer",
      AD_StsCpuToLineCommitPointer, 0, 0, PROP_RW_WHOLE,
      0xCC00, INST2, 0, 0, 0 },

    { CfgRegTSpiSetup,
      "CfgRegTSpiSetup",
      AD_CfgRegTSpiSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSetup__EnableDeskew,
      "CfgRegTSpiSetup__EnableDeskew",
      AD_CfgRegTSpiSetup, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSetup__FlipB4Core,
      "CfgRegTSpiSetup__FlipB4Core",
      AD_CfgRegTSpiSetup, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSetup__ReadDisable,
      "CfgRegTSpiSetup__ReadDisable",
      AD_CfgRegTSpiSetup, 8, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSetup__IgnoreAbortEop,
      "CfgRegTSpiSetup__IgnoreAbortEop",
      AD_CfgRegTSpiSetup, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSetup__FunnelModeEn,
      "CfgRegTSpiSetup__FunnelModeEn",
      AD_CfgRegTSpiSetup, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSetup__FlipInpOrder,
      "CfgRegTSpiSetup__FlipInpOrder",
      AD_CfgRegTSpiSetup, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSetup__IgnoreErrors,
      "CfgRegTSpiSetup__IgnoreErrors",
      AD_CfgRegTSpiSetup, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSetup__EnableTraining,
      "CfgRegTSpiSetup__EnableTraining",
      AD_CfgRegTSpiSetup, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiFifoId0,
      "CfgRegTSpiFifoId0",
      AD_CfgRegTSpiFifoId0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiFifoId1,
      "CfgRegTSpiFifoId1",
      AD_CfgRegTSpiFifoId1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiFifoId2,
      "CfgRegTSpiFifoId2",
      AD_CfgRegTSpiFifoId2, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiFunnelFifoId0,
      "CfgRegTSpiFunnelFifoId0",
      AD_CfgRegTSpiFunnelFifoId0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiFunnelFifoId1,
      "CfgRegTSpiFunnelFifoId1",
      AD_CfgRegTSpiFunnelFifoId1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiFunnelFifoId2,
      "CfgRegTSpiFunnelFifoId2",
      AD_CfgRegTSpiFunnelFifoId2, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiFunnelDefaultFifoId,
      "CfgRegTSpiFunnelDefaultFifoId",
      AD_CfgRegTSpiFunnelDefaultFifoId, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiDipWindow,
      "CfgRegTSpiDipWindow",
      AD_CfgRegTSpiDipWindow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiDipErrThr,
      "CfgRegTSpiDipErrThr",
      AD_CfgRegTSpiDipErrThr, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiTrainingCount,
      "StsRegTSpiTrainingCount",
      AD_StsRegTSpiTrainingCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiSopCount,
      "StsRegTSpiSopCount",
      AD_StsRegTSpiSopCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiEopCount,
      "StsRegTSpiEopCount",
      AD_StsRegTSpiEopCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiExtEopACount,
      "StsRegTSpiExtEopACount",
      AD_StsRegTSpiExtEopACount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiIntEopACount,
      "StsRegTSpiIntEopACount",
      AD_StsRegTSpiIntEopACount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiDip4ErrCount,
      "StsRegTSpiDip4ErrCount",
      AD_StsRegTSpiDip4ErrCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiProtViolCount,
      "StsRegTSpiProtViolCount",
      AD_StsRegTSpiProtViolCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiLossOfSync,
      "StsRegTSpiLossOfSync",
      AD_StsRegTSpiLossOfSync, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiInterrupt,
      "StsRegTSpiInterrupt",
      AD_StsRegTSpiInterrupt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiInterruptMask,
      "StsRegTSpiInterruptMask",
      AD_StsRegTSpiInterruptMask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiFifoOverFlow,
      "StsRegTSpiFifoOverFlow",
      AD_StsRegTSpiFifoOverFlow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTSpiDiag,
      "StsRegTSpiDiag",
      AD_StsRegTSpiDiag, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { VarRegTxPSpiDPGEnable,
      "VarRegTxPSpiDPGEnable",
      AD_VarRegTxPSpiDPGEnable, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGMode,
      "CfgRegTxPSpiDPGMode",
      AD_CfgRegTxPSpiDPGMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGMode__CRCMode,
      "CfgRegTxPSpiDPGMode__CRCMode",
      AD_CfgRegTxPSpiDPGMode, 23, 23, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGMode__ErrorMode,
      "CfgRegTxPSpiDPGMode__ErrorMode",
      AD_CfgRegTxPSpiDPGMode, 22, 21, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGMode__PortId,
      "CfgRegTxPSpiDPGMode__PortId",
      AD_CfgRegTxPSpiDPGMode, 20, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGMode__HeaderMode,
      "CfgRegTxPSpiDPGMode__HeaderMode",
      AD_CfgRegTxPSpiDPGMode, 15, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGMode__Broadcast,
      "CfgRegTxPSpiDPGMode__Broadcast",
      AD_CfgRegTxPSpiDPGMode, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGMode__ContinuousMode,
      "CfgRegTxPSpiDPGMode__ContinuousMode",
      AD_CfgRegTxPSpiDPGMode, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGMode__GapSizeMode,
      "CfgRegTxPSpiDPGMode__GapSizeMode",
      AD_CfgRegTxPSpiDPGMode, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGMode__PatternMode,
      "CfgRegTxPSpiDPGMode__PatternMode",
      AD_CfgRegTxPSpiDPGMode, 6, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGMode__PacketSizeMode,
      "CfgRegTxPSpiDPGMode__PacketSizeMode",
      AD_CfgRegTxPSpiDPGMode, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGCRCValue,
      "CfgRegTxPSpiDPGCRCValue",
      AD_CfgRegTxPSpiDPGCRCValue, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGPacketFixed,
      "CfgRegTxPSpiDPGPacketFixed",
      AD_CfgRegTxPSpiDPGPacketFixed, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGPacketNumber,
      "CfgRegTxPSpiDPGPacketNumber",
      AD_CfgRegTxPSpiDPGPacketNumber, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGGap,
      "CfgRegTxPSpiDPGGap",
      AD_CfgRegTxPSpiDPGGap, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGPatternFixed,
      "CfgRegTxPSpiDPGPatternFixed",
      AD_CfgRegTxPSpiDPGPatternFixed, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiPrbsSeed,
      "CfgRegTxPSpiPrbsSeed",
      AD_CfgRegTxPSpiPrbsSeed, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGSrcL,
      "CfgRegTxPSpiDPGSrcL",
      AD_CfgRegTxPSpiDPGSrcL, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGSrcH,
      "CfgRegTxPSpiDPGSrcH",
      AD_CfgRegTxPSpiDPGSrcH, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGDestL,
      "CfgRegTxPSpiDPGDestL",
      AD_CfgRegTxPSpiDPGDestL, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGDestH,
      "CfgRegTxPSpiDPGDestH",
      AD_CfgRegTxPSpiDPGDestH, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGVLanTag,
      "CfgRegTxPSpiDPGVLanTag",
      AD_CfgRegTxPSpiDPGVLanTag, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGPreambleL,
      "CfgRegTxPSpiDPGPreambleL",
      AD_CfgRegTxPSpiDPGPreambleL, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPGPreambleH,
      "CfgRegTxPSpiDPGPreambleH",
      AD_CfgRegTxPSpiDPGPreambleH, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { VarRegTxPSpiDPVEnable,
      "VarRegTxPSpiDPVEnable",
      AD_VarRegTxPSpiDPVEnable, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPVMode,
      "CfgRegTxPSpiDPVMode",
      AD_CfgRegTxPSpiDPVMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiDPVHdrCtrl,
      "CfgRegTxPSpiDPVHdrCtrl",
      AD_CfgRegTxPSpiDPVHdrCtrl, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiCRRLoopBWReg0,
      "CfgRegTxPSpiCRRLoopBWReg0",
      AD_CfgRegTxPSpiCRRLoopBWReg0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiCRRLoopBWReg1,
      "CfgRegTxPSpiCRRLoopBWReg1",
      AD_CfgRegTxPSpiCRRLoopBWReg1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc,
      "CfgRegTxPSpiHMMisc",
      AD_CfgRegTxPSpiHMMisc, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__tspi_sfi_enable,
      "CfgRegTxPSpiHMMisc__tspi_sfi_enable",
      AD_CfgRegTxPSpiHMMisc, 31, 31, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__tspi_supdate_ena,
      "CfgRegTxPSpiHMMisc__tspi_supdate_ena",
      AD_CfgRegTxPSpiHMMisc, 30, 30, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__tspi_new_sw_det,
      "CfgRegTxPSpiHMMisc__tspi_new_sw_det",
      AD_CfgRegTxPSpiHMMisc, 29, 29, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__TSPI_CRR_BYPASS,
      "CfgRegTxPSpiHMMisc__TSPI_CRR_BYPASS",
      AD_CfgRegTxPSpiHMMisc, 28, 28, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__TSPI_BERT_TX_EN,
      "CfgRegTxPSpiHMMisc__TSPI_BERT_TX_EN",
      AD_CfgRegTxPSpiHMMisc, 27, 27, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__TSPI_BERT_RX_EN,
      "CfgRegTxPSpiHMMisc__TSPI_BERT_RX_EN",
      AD_CfgRegTxPSpiHMMisc, 26, 26, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__TSPI_POWER_DOWN_PPD,
      "CfgRegTxPSpiHMMisc__TSPI_POWER_DOWN_PPD",
      AD_CfgRegTxPSpiHMMisc, 25, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__TSPI_POWER_DOWN,
      "CfgRegTxPSpiHMMisc__TSPI_POWER_DOWN",
      AD_CfgRegTxPSpiHMMisc, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__TSPI_LOOPBACK,
      "CfgRegTxPSpiHMMisc__TSPI_LOOPBACK",
      AD_CfgRegTxPSpiHMMisc, 20, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__TSPI_RATE_MODE,
      "CfgRegTxPSpiHMMisc__TSPI_RATE_MODE",
      AD_CfgRegTxPSpiHMMisc, 2, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSpiHMMisc__TSPI_BYPASS_EN,
      "CfgRegTxPSpiHMMisc__TSPI_BYPASS_EN",
      AD_CfgRegTxPSpiHMMisc, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxPSPIHMPhaseShift,
      "CfgRegTxPSPIHMPhaseShift",
      AD_CfgRegTxPSPIHMPhaseShift, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiDPGStatus,
      "StsTxPSpiDPGStatus",
      AD_StsTxPSpiDPGStatus, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiDPVBitCnt,
      "StsTxPSpiDPVBitCnt",
      AD_StsTxPSpiDPVBitCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiDPVErrorCnt,
      "StsTxPSpiDPVErrorCnt",
      AD_StsTxPSpiDPVErrorCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiDPVCRCErrorCnt,
      "StsTxPSpiDPVCRCErrorCnt",
      AD_StsTxPSpiDPVCRCErrorCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiDPVGoodPktCnt,
      "StsTxPSpiDPVGoodPktCnt",
      AD_StsTxPSpiDPVGoodPktCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiDPVSyncOnCnt,
      "StsTxPSpiDPVSyncOnCnt",
      AD_StsTxPSpiDPVSyncOnCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiDPVEopCnt,
      "StsTxPSpiDPVEopCnt",
      AD_StsTxPSpiDPVEopCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiThr,
      "CfgRegTSpiThr",
      AD_CfgRegTSpiThr, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiThr__MemMgrHungryThr,
      "CfgRegTSpiThr__MemMgrHungryThr",
      AD_CfgRegTSpiThr, 31, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiThr__MemMgrThr,
      "CfgRegTSpiThr__MemMgrThr",
      AD_CfgRegTSpiThr, 21, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiThr__HungryThr,
      "CfgRegTSpiThr__HungryThr",
      AD_CfgRegTSpiThr, 11, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiThr__StarvingThr,
      "CfgRegTSpiThr__StarvingThr",
      AD_CfgRegTSpiThr, 5, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegEnXAUIFlowCtrl,
      "CfgRegEnXAUIFlowCtrl",
      AD_CfgRegEnXAUIFlowCtrl, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiCh0DropCount,
      "StsTxPSpiCh0DropCount",
      AD_StsTxPSpiCh0DropCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiCh1DropCount,
      "StsTxPSpiCh1DropCount",
      AD_StsTxPSpiCh1DropCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiLpbkPktDropCount,
      "StsTxPSpiLpbkPktDropCount",
      AD_StsTxPSpiLpbkPktDropCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiXauiPktDropCount,
      "StsTxPSpiXauiPktDropCount",
      AD_StsTxPSpiXauiPktDropCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiEopCountCh0,
      "StsTxPSpiEopCountCh0",
      AD_StsTxPSpiEopCountCh0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiEopCountCh1,
      "StsTxPSpiEopCountCh1",
      AD_StsTxPSpiEopCountCh1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiEopCountCh2,
      "StsTxPSpiEopCountCh2",
      AD_StsTxPSpiEopCountCh2, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxPSpiEopCountCh3,
      "StsTxPSpiEopCountCh3",
      AD_StsTxPSpiEopCountCh3, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMemTSpiCal,
      "CfgMemTSpiCal",
      AD_CfgMemTSpiCal, 0, 0, PROP_RW_WHOLE,
      0x4, INST128, 0, 0, 0 },

    { CfgMemTxpSpiCalShadow,
      "CfgMemTxpSpiCalShadow",
      AD_CfgMemTxpSpiCalShadow, 0, 0, PROP_RW_WHOLE,
      0x4, INST128, 0, 0, 0 },

    { CfgRegTSpiCalSetup,
      "CfgRegTSpiCalSetup",
      AD_CfgRegTSpiCalSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiCalSetup__ShCalL,
      "CfgRegTSpiCalSetup__ShCalL",
      AD_CfgRegTSpiCalSetup, 19, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiCalSetup__ShCalM,
      "CfgRegTSpiCalSetup__ShCalM",
      AD_CfgRegTSpiCalSetup, 11, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiCalSetup__CalL,
      "CfgRegTSpiCalSetup__CalL",
      AD_CfgRegTSpiCalSetup, 9, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiCalSetup__CalM,
      "CfgRegTSpiCalSetup__CalM",
      AD_CfgRegTSpiCalSetup, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiStatusMode,
      "CfgRegTSpiStatusMode",
      AD_CfgRegTSpiStatusMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiStatusMode__Reserved,
      "CfgRegTSpiStatusMode__Reserved",
      AD_CfgRegTSpiStatusMode, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiStatusMode__FunnelStatusMergeEn,
      "CfgRegTSpiStatusMode__FunnelStatusMergeEn",
      AD_CfgRegTSpiStatusMode, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiStatusMode__EnShdwCalmode,
      "CfgRegTSpiStatusMode__EnShdwCalmode",
      AD_CfgRegTSpiStatusMode, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSwitchPattern,
      "CfgRegTSpiSwitchPattern",
      AD_CfgRegTSpiSwitchPattern, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSwitchPattern__ShPattern,
      "CfgRegTSpiSwitchPattern__ShPattern",
      AD_CfgRegTSpiSwitchPattern, 23, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSwitchPattern__PriPattern,
      "CfgRegTSpiSwitchPattern__PriPattern",
      AD_CfgRegTSpiSwitchPattern, 21, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSwitchPattern__ShdSwitchPattern,
      "CfgRegTSpiSwitchPattern__ShdSwitchPattern",
      AD_CfgRegTSpiSwitchPattern, 19, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTSpiSwitchPattern__PriSwitchPattern,
      "CfgRegTSpiSwitchPattern__PriSwitchPattern",
      AD_CfgRegTSpiSwitchPattern, 9, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSetup,
      "CfgRegTxSSpiSetup",
      AD_CfgRegTxSSpiSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSetup__EnableDeskew,
      "CfgRegTxSSpiSetup__EnableDeskew",
      AD_CfgRegTxSSpiSetup, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSetup__FlipB4Core,
      "CfgRegTxSSpiSetup__FlipB4Core",
      AD_CfgRegTxSSpiSetup, 8, 8, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSetup__ReadDisable,
      "CfgRegTxSSpiSetup__ReadDisable",
      AD_CfgRegTxSSpiSetup, 7, 5, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSetup__IgnoreAbortEop,
      "CfgRegTxSSpiSetup__IgnoreAbortEop",
      AD_CfgRegTxSSpiSetup, 4, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSetup__FunnelModeEn,
      "CfgRegTxSSpiSetup__FunnelModeEn",
      AD_CfgRegTxSSpiSetup, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSetup__FlipInpOrder,
      "CfgRegTxSSpiSetup__FlipInpOrder",
      AD_CfgRegTxSSpiSetup, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSetup__IgnoreErrors,
      "CfgRegTxSSpiSetup__IgnoreErrors",
      AD_CfgRegTxSSpiSetup, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSetup__EnableTraining,
      "CfgRegTxSSpiSetup__EnableTraining",
      AD_CfgRegTxSSpiSetup, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiFifoId0,
      "CfgRegTxSSpiFifoId0",
      AD_CfgRegTxSSpiFifoId0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiFifoId1,
      "CfgRegTxSSpiFifoId1",
      AD_CfgRegTxSSpiFifoId1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiFifoId2,
      "CfgRegTxSSpiFifoId2",
      AD_CfgRegTxSSpiFifoId2, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiFunnelFifoId0,
      "CfgRegTxSSpiFunnelFifoId0",
      AD_CfgRegTxSSpiFunnelFifoId0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiFunnelFifoId1,
      "CfgRegTxSSpiFunnelFifoId1",
      AD_CfgRegTxSSpiFunnelFifoId1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiFunnelFifoId2,
      "CfgRegTxSSpiFunnelFifoId2",
      AD_CfgRegTxSSpiFunnelFifoId2, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiFunnelDefaultFifoId,
      "CfgRegTxSSpiFunnelDefaultFifoId",
      AD_CfgRegTxSSpiFunnelDefaultFifoId, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDipWindow,
      "CfgRegTxSSpiDipWindow",
      AD_CfgRegTxSSpiDipWindow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDipErrThr,
      "CfgRegTxSSpiDipErrThr",
      AD_CfgRegTxSSpiDipErrThr, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiCRRLoopBWReg0,
      "CfgRegTxSSpiCRRLoopBWReg0",
      AD_CfgRegTxSSpiCRRLoopBWReg0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiCRRLoopBWReg1,
      "CfgRegTxSSpiCRRLoopBWReg1",
      AD_CfgRegTxSSpiCRRLoopBWReg1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc,
      "CfgRegTxSSpiHMMisc",
      AD_CfgRegTxSSpiHMMisc, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__tspi_sfi_enable,
      "CfgRegTxSSpiHMMisc__tspi_sfi_enable",
      AD_CfgRegTxSSpiHMMisc, 31, 31, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__tspi_supdate_ena,
      "CfgRegTxSSpiHMMisc__tspi_supdate_ena",
      AD_CfgRegTxSSpiHMMisc, 30, 30, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__tspi_new_sw_det,
      "CfgRegTxSSpiHMMisc__tspi_new_sw_det",
      AD_CfgRegTxSSpiHMMisc, 29, 29, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__TSPI_CRR_BYPASS,
      "CfgRegTxSSpiHMMisc__TSPI_CRR_BYPASS",
      AD_CfgRegTxSSpiHMMisc, 28, 28, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__TSPI_BERT_TX_EN,
      "CfgRegTxSSpiHMMisc__TSPI_BERT_TX_EN",
      AD_CfgRegTxSSpiHMMisc, 27, 27, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__TSPI_BERT_RX_EN,
      "CfgRegTxSSpiHMMisc__TSPI_BERT_RX_EN",
      AD_CfgRegTxSSpiHMMisc, 26, 26, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__TSPI_POWER_DOWN_PPD,
      "CfgRegTxSSpiHMMisc__TSPI_POWER_DOWN_PPD",
      AD_CfgRegTxSSpiHMMisc, 25, 25, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__TSPI_POWER_DOWN,
      "CfgRegTxSSpiHMMisc__TSPI_POWER_DOWN",
      AD_CfgRegTxSSpiHMMisc, 24, 24, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__TSPI_LOOPBACK,
      "CfgRegTxSSpiHMMisc__TSPI_LOOPBACK",
      AD_CfgRegTxSSpiHMMisc, 20, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__TSPI_RATE_MODE,
      "CfgRegTxSSpiHMMisc__TSPI_RATE_MODE",
      AD_CfgRegTxSSpiHMMisc, 2, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiHMMisc__TSPI_BYPASS_EN,
      "CfgRegTxSSpiHMMisc__TSPI_BYPASS_EN",
      AD_CfgRegTxSSpiHMMisc, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSPIHMPhaseShift,
      "CfgRegTxSSPIHMPhaseShift",
      AD_CfgRegTxSSPIHMPhaseShift, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiTrainingCount,
      "StsRegTxSSpiTrainingCount",
      AD_StsRegTxSSpiTrainingCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiSopCount,
      "StsRegTxSSpiSopCount",
      AD_StsRegTxSSpiSopCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiEopCount,
      "StsRegTxSSpiEopCount",
      AD_StsRegTxSSpiEopCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiExtEopACount,
      "StsRegTxSSpiExtEopACount",
      AD_StsRegTxSSpiExtEopACount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiIntEopACount,
      "StsRegTxSSpiIntEopACount",
      AD_StsRegTxSSpiIntEopACount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiDip4ErrCount,
      "StsRegTxSSpiDip4ErrCount",
      AD_StsRegTxSSpiDip4ErrCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiProtViolCount,
      "StsRegTxSSpiProtViolCount",
      AD_StsRegTxSSpiProtViolCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiLossOfSync,
      "StsRegTxSSpiLossOfSync",
      AD_StsRegTxSSpiLossOfSync, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiInterrupt,
      "StsRegTxSSpiInterrupt",
      AD_StsRegTxSSpiInterrupt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiInterruptMask,
      "StsRegTxSSpiInterruptMask",
      AD_StsRegTxSSpiInterruptMask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiFifoOverFlow,
      "StsRegTxSSpiFifoOverFlow",
      AD_StsRegTxSSpiFifoOverFlow, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsRegTxSSpiDiag,
      "StsRegTxSSpiDiag",
      AD_StsRegTxSSpiDiag, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { VarRegTxSSpiDPGEnable,
      "VarRegTxSSpiDPGEnable",
      AD_VarRegTxSSpiDPGEnable, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGMode,
      "CfgRegTxSSpiDPGMode",
      AD_CfgRegTxSSpiDPGMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGMode__CRCMode,
      "CfgRegTxSSpiDPGMode__CRCMode",
      AD_CfgRegTxSSpiDPGMode, 23, 23, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGMode__ErrorMode,
      "CfgRegTxSSpiDPGMode__ErrorMode",
      AD_CfgRegTxSSpiDPGMode, 22, 21, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGMode__PortId,
      "CfgRegTxSSpiDPGMode__PortId",
      AD_CfgRegTxSSpiDPGMode, 20, 16, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGMode__HeaderMode,
      "CfgRegTxSSpiDPGMode__HeaderMode",
      AD_CfgRegTxSSpiDPGMode, 15, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGMode__Broadcast,
      "CfgRegTxSSpiDPGMode__Broadcast",
      AD_CfgRegTxSSpiDPGMode, 11, 11, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGMode__ContinuousMode,
      "CfgRegTxSSpiDPGMode__ContinuousMode",
      AD_CfgRegTxSSpiDPGMode, 10, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGMode__GapSizeMode,
      "CfgRegTxSSpiDPGMode__GapSizeMode",
      AD_CfgRegTxSSpiDPGMode, 9, 9, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGMode__PatternMode,
      "CfgRegTxSSpiDPGMode__PatternMode",
      AD_CfgRegTxSSpiDPGMode, 6, 4, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGMode__PacketSizeMode,
      "CfgRegTxSSpiDPGMode__PacketSizeMode",
      AD_CfgRegTxSSpiDPGMode, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGCRCValue,
      "CfgRegTxSSpiDPGCRCValue",
      AD_CfgRegTxSSpiDPGCRCValue, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGPacketFixed,
      "CfgRegTxSSpiDPGPacketFixed",
      AD_CfgRegTxSSpiDPGPacketFixed, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGPacketNumber,
      "CfgRegTxSSpiDPGPacketNumber",
      AD_CfgRegTxSSpiDPGPacketNumber, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGGap,
      "CfgRegTxSSpiDPGGap",
      AD_CfgRegTxSSpiDPGGap, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGPatternFixed,
      "CfgRegTxSSpiDPGPatternFixed",
      AD_CfgRegTxSSpiDPGPatternFixed, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiPrbsSeed,
      "CfgRegTxSSpiPrbsSeed",
      AD_CfgRegTxSSpiPrbsSeed, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGSrcL,
      "CfgRegTxSSpiDPGSrcL",
      AD_CfgRegTxSSpiDPGSrcL, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGSrcH,
      "CfgRegTxSSpiDPGSrcH",
      AD_CfgRegTxSSpiDPGSrcH, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGDestL,
      "CfgRegTxSSpiDPGDestL",
      AD_CfgRegTxSSpiDPGDestL, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGDestH,
      "CfgRegTxSSpiDPGDestH",
      AD_CfgRegTxSSpiDPGDestH, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGVLanTag,
      "CfgRegTxSSpiDPGVLanTag",
      AD_CfgRegTxSSpiDPGVLanTag, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGPreambleL,
      "CfgRegTxSSpiDPGPreambleL",
      AD_CfgRegTxSSpiDPGPreambleL, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPGPreambleH,
      "CfgRegTxSSpiDPGPreambleH",
      AD_CfgRegTxSSpiDPGPreambleH, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { VarRegTxSSpiDPVEnable,
      "VarRegTxSSpiDPVEnable",
      AD_VarRegTxSSpiDPVEnable, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPVMode,
      "CfgRegTxSSpiDPVMode",
      AD_CfgRegTxSSpiDPVMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiDPVHdrCtrl,
      "CfgRegTxSSpiDPVHdrCtrl",
      AD_CfgRegTxSSpiDPVHdrCtrl, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiDPGStatus,
      "StsTxSSpiDPGStatus",
      AD_StsTxSSpiDPGStatus, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiDPVBitCnt,
      "StsTxSSpiDPVBitCnt",
      AD_StsTxSSpiDPVBitCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiDPVErrorCnt,
      "StsTxSSpiDPVErrorCnt",
      AD_StsTxSSpiDPVErrorCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiDPVCRCErrorCnt,
      "StsTxSSpiDPVCRCErrorCnt",
      AD_StsTxSSpiDPVCRCErrorCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiDPVGoodPktCnt,
      "StsTxSSpiDPVGoodPktCnt",
      AD_StsTxSSpiDPVGoodPktCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiDPVSyncOnCnt,
      "StsTxSSpiDPVSyncOnCnt",
      AD_StsTxSSpiDPVSyncOnCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiDPVEopCnt,
      "StsTxSSpiDPVEopCnt",
      AD_StsTxSSpiDPVEopCnt, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiThr,
      "CfgRegTxSSpiThr",
      AD_CfgRegTxSSpiThr, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiThr__MTUHungryThr,
      "CfgRegTxSSpiThr__MTUHungryThr",
      AD_CfgRegTxSSpiThr, 31, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiThr__MTUStarvingThr,
      "CfgRegTxSSpiThr__MTUStarvingThr",
      AD_CfgRegTxSSpiThr, 21, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiThr__HungryThr,
      "CfgRegTxSSpiThr__HungryThr",
      AD_CfgRegTxSSpiThr, 11, 6, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiThr__StarvingThr,
      "CfgRegTxSSpiThr__StarvingThr",
      AD_CfgRegTxSSpiThr, 5, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiMemMgrThr,
      "CfgRegTxSSpiMemMgrThr",
      AD_CfgRegTxSSpiMemMgrThr, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiMemMgrThr__MemHungryThr,
      "CfgRegTxSSpiMemMgrThr__MemHungryThr",
      AD_CfgRegTxSSpiMemMgrThr, 19, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiMemMgrThr__MemStarvingThr,
      "CfgRegTxSSpiMemMgrThr__MemStarvingThr",
      AD_CfgRegTxSSpiMemMgrThr, 9, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiCh0PktDropCount,
      "StsTxSSpiCh0PktDropCount",
      AD_StsTxSSpiCh0PktDropCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiCh1PktDropCount,
      "StsTxSSpiCh1PktDropCount",
      AD_StsTxSSpiCh1PktDropCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiLpbkPktDropCount,
      "StsTxSSpiLpbkPktDropCount",
      AD_StsTxSSpiLpbkPktDropCount, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiEopCountCh0,
      "StsTxSSpiEopCountCh0",
      AD_StsTxSSpiEopCountCh0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiEopCountCh1,
      "StsTxSSpiEopCountCh1",
      AD_StsTxSSpiEopCountCh1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsTxSSpiEopCountCh2,
      "StsTxSSpiEopCountCh2",
      AD_StsTxSSpiEopCountCh2, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMemTxSSpiCal,
      "CfgMemTxSSpiCal",
      AD_CfgMemTxSSpiCal, 0, 0, PROP_RW_WHOLE,
      0x4, INST128, 0, 0, 0 },

    { CfgMemTxsSpiCalShadow,
      "CfgMemTxsSpiCalShadow",
      AD_CfgMemTxsSpiCalShadow, 0, 0, PROP_RW_WHOLE,
      0x4, INST128, 0, 0, 0 },

    { CfgRegTxSSpiCalSetup,
      "CfgRegTxSSpiCalSetup",
      AD_CfgRegTxSSpiCalSetup, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiCalSetup__ShCalL,
      "CfgRegTxSSpiCalSetup__ShCalL",
      AD_CfgRegTxSSpiCalSetup, 19, 12, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiCalSetup__ShCalM,
      "CfgRegTxSSpiCalSetup__ShCalM",
      AD_CfgRegTxSSpiCalSetup, 11, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiCalSetup__CalL,
      "CfgRegTxSSpiCalSetup__CalL",
      AD_CfgRegTxSSpiCalSetup, 9, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiCalSetup__CalM,
      "CfgRegTxSSpiCalSetup__CalM",
      AD_CfgRegTxSSpiCalSetup, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiStatusMode,
      "CfgRegTxSSpiStatusMode",
      AD_CfgRegTxSSpiStatusMode, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiStatusMode__Reserved,
      "CfgRegTxSSpiStatusMode__Reserved",
      AD_CfgRegTxSSpiStatusMode, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiStatusMode__FunnelStatusMergeEn,
      "CfgRegTxSSpiStatusMode__FunnelStatusMergeEn",
      AD_CfgRegTxSSpiStatusMode, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiStatusMode__EnShdwCalmode,
      "CfgRegTxSSpiStatusMode__EnShdwCalmode",
      AD_CfgRegTxSSpiStatusMode, 1, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSwitchPattern,
      "CfgRegTxSSpiSwitchPattern",
      AD_CfgRegTxSSpiSwitchPattern, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSwitchPattern__ShPattern,
      "CfgRegTxSSpiSwitchPattern__ShPattern",
      AD_CfgRegTxSSpiSwitchPattern, 23, 22, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSwitchPattern__PriPattern,
      "CfgRegTxSSpiSwitchPattern__PriPattern",
      AD_CfgRegTxSSpiSwitchPattern, 21, 20, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSwitchPattern__ShdSwitchPattern,
      "CfgRegTxSSpiSwitchPattern__ShdSwitchPattern",
      AD_CfgRegTxSSpiSwitchPattern, 19, 10, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgRegTxSSpiSwitchPattern__PriSwitchPattern,
      "CfgRegTxSSpiSwitchPattern__PriSwitchPattern",
      AD_CfgRegTxSSpiSwitchPattern, 9, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgTxXauiXmacModes,
      "CfgTxXauiXmacModes",
      AD_CfgTxXauiXmacModes, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxXauiXmacModes__CfgRemoveInCrc,
      "CfgTxXauiXmacModes__CfgRemoveInCrc",
      AD_CfgTxXauiXmacModes, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxXauiXmacModes__CfgTxXauiXmacMode,
      "CfgTxXauiXmacModes__CfgTxXauiXmacMode",
      AD_CfgTxXauiXmacModes, 1, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxXauiXmacSopInCnt,
      "StsRegTxXauiXmacSopInCnt",
      AD_StsRegTxXauiXmacSopInCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxXauiXmacEopInCnt,
      "StsRegTxXauiXmacEopInCnt",
      AD_StsRegTxXauiXmacEopInCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxXauiXmacSopOutCnt,
      "StsRegTxXauiXmacSopOutCnt",
      AD_StsRegTxXauiXmacSopOutCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxXauiXmacEopOutCnt,
      "StsRegTxXauiXmacEopOutCnt",
      AD_StsRegTxXauiXmacEopOutCnt, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegLsbTxXauiXmacByteCount,
      "StsRegLsbTxXauiXmacByteCount",
      AD_StsRegLsbTxXauiXmacByteCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegMsbTxXauiXmacByteCount,
      "StsRegMsbTxXauiXmacByteCount",
      AD_StsRegMsbTxXauiXmacByteCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxXauiXmacFrames,
      "StsRegTxXauiXmacFrames",
      AD_StsRegTxXauiXmacFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { StsRegTxXauiXmacErroredFrames,
      "StsRegTxXauiXmacErroredFrames",
      AD_StsRegTxXauiXmacErroredFrames, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSModes,
      "CfgRegTxRSModes",
      AD_CfgRegTxRSModes, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSModes__TxDICOverWISEn,
      "CfgRegTxRSModes__TxDICOverWISEn",
      AD_CfgRegTxRSModes, 5, 5, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSModes__TxLocalFaultInsertEn,
      "CfgRegTxRSModes__TxLocalFaultInsertEn",
      AD_CfgRegTxRSModes, 4, 4, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSModes__TxProgIPGEn,
      "CfgRegTxRSModes__TxProgIPGEn",
      AD_CfgRegTxRSModes, 3, 3, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSModes__TxWISEn,
      "CfgRegTxRSModes__TxWISEn",
      AD_CfgRegTxRSModes, 2, 2, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSModes__TxIpg8to11,
      "CfgRegTxRSModes__TxIpg8to11",
      AD_CfgRegTxRSModes, 1, 1, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgRegTxRSModes__TxDicEn,
      "CfgRegTxRSModes__TxDicEn",
      AD_CfgRegTxRSModes, 0, 0, PROP_RW,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxXauiDebugEopCharacter,
      "CfgTxXauiDebugEopCharacter",
      AD_CfgTxXauiDebugEopCharacter, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxXauiProgIPGCount,
      "CfgTxXauiProgIPGCount",
      AD_CfgTxXauiProgIPGCount, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxXauiRegTxRSFaultTrafficBP,
      "CfgTxXauiRegTxRSFaultTrafficBP",
      AD_CfgTxXauiRegTxRSFaultTrafficBP, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxXauiRegTxRSLocalFaultEn,
      "CfgTxXauiRegTxRSLocalFaultEn",
      AD_CfgTxXauiRegTxRSLocalFaultEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxXauiRegTxRSLocalFaultMode,
      "CfgTxXauiRegTxRSLocalFaultMode",
      AD_CfgTxXauiRegTxRSLocalFaultMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxXauiRegTxRSRemoteFaultEn,
      "CfgTxXauiRegTxRSRemoteFaultEn",
      AD_CfgTxXauiRegTxRSRemoteFaultEn, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxXauiRegTxRSLinkFaultRecoveryMode,
      "CfgTxXauiRegTxRSLinkFaultRecoveryMode",
      AD_CfgTxXauiRegTxRSLinkFaultRecoveryMode, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgTxXauiRegTxRSCPUFaultRecovery,
      "CfgTxXauiRegTxRSCPUFaultRecovery",
      AD_CfgTxXauiRegTxRSCPUFaultRecovery, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgDontAddPreAmble,
      "CfgDontAddPreAmble",
      AD_CfgDontAddPreAmble, 0, 0, PROP_RW_WHOLE,
      0x4000, INST2, 0, 0, 0 },

    { CfgMiscFullPacketMode0,
      "CfgMiscFullPacketMode0",
      AD_CfgMiscFullPacketMode0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscTailDropEn0,
      "CfgMiscTailDropEn0",
      AD_CfgMiscTailDropEn0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscDisableEcc0,
      "CfgMiscDisableEcc0",
      AD_CfgMiscDisableEcc0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscDisableRead0,
      "CfgMiscDisableRead0",
      AD_CfgMiscDisableRead0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscReadOnThreshold0,
      "CfgMiscReadOnThreshold0",
      AD_CfgMiscReadOnThreshold0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscReadOffThreshold0,
      "CfgMiscReadOffThreshold0",
      AD_CfgMiscReadOffThreshold0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscReadTimerValue0,
      "CfgMiscReadTimerValue0",
      AD_CfgMiscReadTimerValue0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccErrorInterrupt0,
      "StsMiscEccErrorInterrupt0",
      AD_StsMiscEccErrorInterrupt0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccErrorInterrupt0Mask,
      "StsMiscEccErrorInterrupt0Mask",
      AD_StsMiscEccErrorInterrupt0Mask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccSingleErrorInterrupt0,
      "StsMiscEccSingleErrorInterrupt0",
      AD_StsMiscEccSingleErrorInterrupt0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccSingleErrorInterrupt0Mask,
      "StsMiscEccSingleErrorInterrupt0Mask",
      AD_StsMiscEccSingleErrorInterrupt0Mask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccDoubleErrorInterrupt0,
      "StsMiscEccDoubleErrorInterrupt0",
      AD_StsMiscEccDoubleErrorInterrupt0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccDoubleErrorInterrupt0Mask,
      "StsMiscEccDoubleErrorInterrupt0Mask",
      AD_StsMiscEccDoubleErrorInterrupt0Mask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscWritePointer0,
      "StsMiscWritePointer0",
      AD_StsMiscWritePointer0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscReadPointer0,
      "StsMiscReadPointer0",
      AD_StsMiscReadPointer0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscCommitPointer0,
      "StsMiscCommitPointer0",
      AD_StsMiscCommitPointer0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUAccess0,
      "CfgMiscCPUAccess0",
      AD_CfgMiscCPUAccess0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUAccess0__CPUCommitPtrSet,
      "CfgMiscCPUAccess0__CPUCommitPtrSet",
      AD_CfgMiscCPUAccess0, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUAccess0__CPURead,
      "CfgMiscCPUAccess0__CPURead",
      AD_CfgMiscCPUAccess0, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUAccess0__CPUWrite,
      "CfgMiscCPUAccess0__CPUWrite",
      AD_CfgMiscCPUAccess0, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUAccess0__CPUAccessEn,
      "CfgMiscCPUAccess0__CPUAccessEn",
      AD_CfgMiscCPUAccess0, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUWriteAddress0,
      "CfgMiscCPUWriteAddress0",
      AD_CfgMiscCPUWriteAddress0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUReadAddress0,
      "CfgMiscCPUReadAddress0",
      AD_CfgMiscCPUReadAddress0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUCommitPointer0,
      "CfgMiscCPUCommitPointer0",
      AD_CfgMiscCPUCommitPointer0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUWriteData0,
      "CfgMiscCPUWriteData0",
      AD_CfgMiscCPUWriteData0, 0, 0, PROP_RW_WHOLE,
      0x4, INST9, 0, 0, 0 },

    { StsMiscCPUReadData0,
      "StsMiscCPUReadData0",
      AD_StsMiscCPUReadData0, 0, 0, PROP_RW_WHOLE,
      0x4, INST9, 0, 0, 0 },

    { StsRegTailDropCount0,
      "StsRegTailDropCount0",
      AD_StsRegTailDropCount0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscDisableEcc1,
      "CfgMiscDisableEcc1",
      AD_CfgMiscDisableEcc1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscDisableRead1,
      "CfgMiscDisableRead1",
      AD_CfgMiscDisableRead1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscFullPacketMode1,
      "CfgMiscFullPacketMode1",
      AD_CfgMiscFullPacketMode1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscTailDropEn1,
      "CfgMiscTailDropEn1",
      AD_CfgMiscTailDropEn1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscReadOnThreshold1,
      "CfgMiscReadOnThreshold1",
      AD_CfgMiscReadOnThreshold1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscReadOffThreshold1,
      "CfgMiscReadOffThreshold1",
      AD_CfgMiscReadOffThreshold1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscReadTimerValue1,
      "CfgMiscReadTimerValue1",
      AD_CfgMiscReadTimerValue1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccErrorInterrupt1,
      "StsMiscEccErrorInterrupt1",
      AD_StsMiscEccErrorInterrupt1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccErrorInterrupt1Mask,
      "StsMiscEccErrorInterrupt1Mask",
      AD_StsMiscEccErrorInterrupt1Mask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccSingleErrorInterrupt1,
      "StsMiscEccSingleErrorInterrupt1",
      AD_StsMiscEccSingleErrorInterrupt1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccSingleErrorInterrupt1Mask,
      "StsMiscEccSingleErrorInterrupt1Mask",
      AD_StsMiscEccSingleErrorInterrupt1Mask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccDoubleErrorInterrupt1,
      "StsMiscEccDoubleErrorInterrupt1",
      AD_StsMiscEccDoubleErrorInterrupt1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscEccDoubleErrorInterrupt1Mask,
      "StsMiscEccDoubleErrorInterrupt1Mask",
      AD_StsMiscEccDoubleErrorInterrupt1Mask, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscWritePointer1,
      "StsMiscWritePointer1",
      AD_StsMiscWritePointer1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscReadPointer1,
      "StsMiscReadPointer1",
      AD_StsMiscReadPointer1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { StsMiscCommitPointer1,
      "StsMiscCommitPointer1",
      AD_StsMiscCommitPointer1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUAccess1,
      "CfgMiscCPUAccess1",
      AD_CfgMiscCPUAccess1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUAccess1__CPUCommitPtrSet,
      "CfgMiscCPUAccess1__CPUCommitPtrSet",
      AD_CfgMiscCPUAccess1, 3, 3, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUAccess1__CPURead,
      "CfgMiscCPUAccess1__CPURead",
      AD_CfgMiscCPUAccess1, 2, 2, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUAccess1__CPUWrite,
      "CfgMiscCPUAccess1__CPUWrite",
      AD_CfgMiscCPUAccess1, 1, 1, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUAccess1__CPUAccessEn,
      "CfgMiscCPUAccess1__CPUAccessEn",
      AD_CfgMiscCPUAccess1, 0, 0, PROP_RW,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUWriteAddress1,
      "CfgMiscCPUWriteAddress1",
      AD_CfgMiscCPUWriteAddress1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUReadAddress1,
      "CfgMiscCPUReadAddress1",
      AD_CfgMiscCPUReadAddress1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUCommitPointer1,
      "CfgMiscCPUCommitPointer1",
      AD_CfgMiscCPUCommitPointer1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgMiscCPUWriteData1,
      "CfgMiscCPUWriteData1",
      AD_CfgMiscCPUWriteData1, 0, 0, PROP_RW_WHOLE,
      0x4, INST9, 0, 0, 0 },

    { StsMiscCPUReadData1,
      "StsMiscCPUReadData1",
      AD_StsMiscCPUReadData1, 0, 0, PROP_RW_WHOLE,
      0x4, INST9, 0, 0, 0 },

    { StsRegTailDropCount1,
      "StsRegTailDropCount1",
      AD_StsRegTailDropCount1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { CfgTxControl,
      "CfgTxControl",
      AD_CfgTxControl, 0, 0, PROP_RW_WHOLE,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txcalthr,
      "CfgTxControl__txcalthr",
      AD_CfgTxControl, 31, 30, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__Spare,
      "CfgTxControl__Spare",
      AD_CfgTxControl, 29, 29, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__plldiv,
      "CfgTxControl__plldiv",
      AD_CfgTxControl, 28, 27, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txamp,
      "CfgTxControl__txamp",
      AD_CfgTxControl, 26, 25, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txpllpd,
      "CfgTxControl__txpllpd",
      AD_CfgTxControl, 24, 24, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txforce,
      "CfgTxControl__txforce",
      AD_CfgTxControl, 23, 22, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__fwlpbena,
      "CfgTxControl__fwlpbena",
      AD_CfgTxControl, 21, 21, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__revclksel,
      "CfgTxControl__revclksel",
      AD_CfgTxControl, 20, 20, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__clkoutpd,
      "CfgTxControl__clkoutpd",
      AD_CfgTxControl, 19, 19, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txclk8pd,
      "CfgTxControl__txclk8pd",
      AD_CfgTxControl, 18, 18, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txocr,
      "CfgTxControl__txocr",
      AD_CfgTxControl, 17, 16, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txpllf,
      "CfgTxControl__txpllf",
      AD_CfgTxControl, 15, 13, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txpllp,
      "CfgTxControl__txpllp",
      AD_CfgTxControl, 12, 10, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txpllz,
      "CfgTxControl__txpllz",
      AD_CfgTxControl, 9, 8, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__tdws64,
      "CfgTxControl__tdws64",
      AD_CfgTxControl, 7, 7, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txvcoext,
      "CfgTxControl__txvcoext",
      AD_CfgTxControl, 6, 6, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txpllcal,
      "CfgTxControl__txpllcal",
      AD_CfgTxControl, 5, 5, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txlockdet,
      "CfgTxControl__txlockdet",
      AD_CfgTxControl, 4, 4, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txplldet,
      "CfgTxControl__txplldet",
      AD_CfgTxControl, 3, 3, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txclk66pd,
      "CfgTxControl__txclk66pd",
      AD_CfgTxControl, 2, 2, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txlockpd,
      "CfgTxControl__txlockpd",
      AD_CfgTxControl, 1, 1, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgTxControl__txpd,
      "CfgTxControl__txpd",
      AD_CfgTxControl, 0, 0, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl,
      "CfgRxControl",
      AD_CfgRxControl, 0, 0, PROP_RW_WHOLE,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rhcalthr,
      "CfgRxControl__rhcalthr",
      AD_CfgRxControl, 31, 30, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__revlpbena,
      "CfgRxControl__revlpbena",
      AD_CfgRxControl, 29, 29, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxeq,
      "CfgRxControl__rxeq",
      AD_CfgRxControl, 28, 26, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxphase,
      "CfgRxControl__rxphase",
      AD_CfgRxControl, 25, 21, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxpllg,
      "CfgRxControl__rxpllg",
      AD_CfgRxControl, 20, 17, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxocr,
      "CfgRxControl__rxocr",
      AD_CfgRxControl, 16, 16, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxpllf,
      "CfgRxControl__rxpllf",
      AD_CfgRxControl, 15, 13, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxpllp,
      "CfgRxControl__rxpllp",
      AD_CfgRxControl, 12, 10, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxpllz,
      "CfgRxControl__rxpllz",
      AD_CfgRxControl, 9, 8, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rdws64,
      "CfgRxControl__rdws64",
      AD_CfgRxControl, 7, 7, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxvcoext,
      "CfgRxControl__rxvcoext",
      AD_CfgRxControl, 6, 6, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxpllcal,
      "CfgRxControl__rxpllcal",
      AD_CfgRxControl, 5, 5, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxlockdet,
      "CfgRxControl__rxlockdet",
      AD_CfgRxControl, 4, 4, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxplldet,
      "CfgRxControl__rxplldet",
      AD_CfgRxControl, 3, 3, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxclk66pd,
      "CfgRxControl__rxclk66pd",
      AD_CfgRxControl, 2, 2, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxlockpd,
      "CfgRxControl__rxlockpd",
      AD_CfgRxControl, 1, 1, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgRxControl__rxpd,
      "CfgRxControl__rxpd",
      AD_CfgRxControl, 0, 0, PROP_RW,
      0x100, INST2, 0, 0, 0 },

    { CfgStatusControl,
      "CfgStatusControl",
      AD_CfgStatusControl, 0, 0, PROP_RW_WHOLE,
      0x100, INST2, 0, 0, 0 },

    { CfgTestCntr,
      "CfgTestCntr",
      AD_CfgTestCntr, 0, 0, PROP_RW_WHOLE,
      0x100, INST2, 0, 0, 0 },

    { StsTxCalReg,
      "StsTxCalReg",
      AD_StsTxCalReg, 0, 0, PROP_RW_WHOLE,
      0x100, INST2, 0, 0, 0 },

    { TwoWireMasterBaseAddress0,
      "TwoWireMasterBaseAddress0",
      AD_TwoWireMasterBaseAddress0, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { TwoWireMasterBaseAddress1,
      "TwoWireMasterBaseAddress1",
      AD_TwoWireMasterBaseAddress1, 0, 0, PROP_RW_WHOLE,
      0, INST1, 0, 0, 0 },

    { -1, "End of redHawk Registers",
      0, 0, 0, 0, 0, 0, 0, 0, 0 },
};

int redHawkRegSize = sizeof(redHawkRegs);
