/*
Copyright (C) 2008, 2009  GE Fanuc, Inc
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
*/
#ifndef __CONFIG_H
#define __CONFIG_H

#include "octeon_common.h"

#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
#define CONFIG_OCTEON		1
#define CONFIG_OCTEON_56XX	1
#define CFG_LATE_BOARD_INIT	1
/* CONFIG_OCTEON_W56XX set by Makefile in include/config.h */

#if !defined(__U_BOOT_HOST__) && !defined(__BYTE_ORDER)
/* Set endian macros for simple exec includes, but not for host utilities */
    #define __BYTE_ORDER __BIG_ENDIAN
#endif

/* Defaults to use if bootloader cannot autodetect settings */
#define DEFAULT_ECLK_FREQ_MHZ        500  /* Used if multiplier read fails, and for DRAM refresh rates */

#define CONFIG_OCTEON_LLM_WORKAROUND
#define CONFIG_OCTEON_PCIX_WORKAROUND

/* Used to control conditional compilation for shared code between simple
** exec and u-boot */
#define CONFIG_OCTEON_U_BOOT

/* W56xx uses configuration eeprom */
#define CONFIG_OCTEON_EEPROM_TUPLES     1

/* let the eth address be writeable */
#define CONFIG_ENV_OVERWRITE 1

/* Configuration to cause u-boot to skip DDR init, and
** run completely from L2.  Memory size is limited to allow this.
** NOTE: This config is for bringup/debug purposes, and is likely to be
** removed in the near future. */
#define CONFIG_L2_ONLY    0

#if CONFIG_L2_ONLY
#define CONFIG_NO_CLEAR_DDR 1
#endif


/* bootloader usable memory size in bytes for W56xx, hard code until autodetect */
#define OCTEON_MEM_SIZE (1*1024*1024*1024ULL)

/* POST "no error" indication */
#define NO_POST_ERROR               0xFF
#define FLASH_CHECKSUM_ERROR        0x00
#define RAM_FAILURE                 0x01
#define PHY_FAILURE                 0x02
#define RLDRAM_FAILURE				0x04
#define INTERFACE0_DIMM_NOT_DETECTED  0x05
#define INTERFACE1_DIMM_NOT_DETECTED  0x06

#define PMEM_FAILURE                0x08
#define TLBMISS_EXCEPTION           0x20
#define XTLBMISS_EXCEPTION          0x21
#define CACHE_EXCEPTION             0x22
#define GENERAL1_EXCEPTION          0x23
#define GENERAL2_EXCEPTION          0x24
#define DEBUG_EXCEPTION             0x25
#define SPI0_TSCLK_WAIT_ERROR       0x30
#define SPI1_TSCLK_WAIT_ERROR       0x31
#define SPI0_RSCLK_WAIT_ERROR       0x32
#define SPI1_RSCLK_WAIT_ERROR       0x33
#define SPI0_TRAINING_WAIT_ERROR    0x34
#define SPI1_TRAINING_WAIT_ERROR    0x35
#define SPI0_STAT_SYNC_WAIT_ERROR   0x36
#define SPI1_STAT_SYNC_WAIT_ERROR   0x37
#define RESERVED_CODE_BASE          0x80

#define TLBMISS_ADDRESS             0x200
#define XTLBMISS_ADDRESS            0x280
#define CACHE_ADDRESS               0x300
#define GENERAL1_ADDRESS            0x380
#define GENERAL2_ADDRESS            0x400
#define DEBUG_ADDRESS               0x480

/* Addresses for various things on boot bus.  These addresses
** are used to configure the boot bus mappings. */
/* Boot FLASH uses CS0 which reserves 128MB + 4MB                    : 0x17C00000 - 0x1FFFFFFF */
#define BOARD_BASE_FPGA_ADDR        0x16000000 /* CS1 reserves 16MB  : 0x26000000 - 0x26FFFFFF */
#define BOARD_BASE_PMEM_LOWER_ADDR  0x30000000 /* CS2 reserves 16MB  : 0x30000000 - 0x30FFFFFF */
#define BOARD_BASE_PMEM_UPPER_ADDR  0x31000000 /* CS3 reserves 16MB  : 0x31000000 - 0x31FFFFFF */

/* keep this defined to the base of the PMEM addresses for backwards compatiblilty */
#define BOARD_BASE_PMEM_ADDR 		BOARD_BASE_PMEM_LOWER_ADDR   
#define BOARD_BASE_PMEM_DDR_ADDR        0x410000000ull

//jeremy w5434 - I think this is WRONG. I think these are being used mistakenly for the RAM memory addresses in cmd_eeprom memtest_xxbit()
#define PMEM_START_DEFAULT     BOARD_BASE_PMEM_LOWER_ADDR
#define PMEM_SIZE_DEFAULT      (32 * 1024 * 1024) /* 32 MB */

#define BOARD_FPGA_CHIP_SEL         1
#define BOARD_PMEM_LOWER_CHIP_SEL	2
#define BOARD_PMEM_UPPER_CHIP_SEL   3

#define OCTEON_PAL_BASE_ADDR        0x1d030000

/* SPD EEPROM addresses board */
#define BOARD_MMC_RESERVED_START    0
#define BOARD_MMC_RESERVED_SIZE     (2 * 1024)
#define BOARD_POST_LOG_START        (BOARD_MMC_RESERVED_START + BOARD_MMC_RESERVED_SIZE)
#define BOARD_POST_LOG_SIZE         16
#define BOARD_EEPROM_UBOOT_START    (BOARD_POST_LOG_START + BOARD_POST_LOG_SIZE)

/******** TWSI Addresses *******/
#define BOARD_DIMM_0_SPD_TWSI_ADDR  0x50
#define BOARD_DIMM_1_SPD_TWSI_ADDR  0x51
#define BOARD_EEPROM_TWSI_ADDR      0x52
#define BOARD_SFP0_TWSI_ADDR        0x53

/* SFP+ 10G board will not have normal SFPs so this is not really a duplicate address */
#define BOARD_SFP_PLUS_TWSI_ADDR    0x53
#define BOARD_SFP1_TWSI_ADDR        0x54
#define BOARD_SFP2_TWSI_ADDR        0x55
#define BOARD_SFP3_TWSI_ADDR        0x56
#define BOARD_TEMP_SENSOR_TWSI_ADDR 0x57

#define BOARD_MCU_TWSI_ADDR         0x60

#define BOARD_TWSI_READY_WAIT       100000000
#define BOARD_TWSI_READ_CMD_WAIT    100000000
#define BOARD_TWSI_WRITE_CMD_WAIT   100000000
#define BOARD_ERROR_MAX_RETRIES     100000

/* FPGA Definitions - General */
#define BOARD_VERSION_ID_REG                  	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0000)
#define BOARD_ID_DIPSWITCH_REG                	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0001)
#define BOARD_LED_CONTROL_REG                 	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0002)
#define BOARD_INTERRUPT_CONTROL_REG           	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0003)
#define BOARD_INTERRUPT_STATUS_REG            	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0004)
#define BOARD_PAYLOAD_RESET_REG               	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0005)
#define BOARD_TX_CONTROL_REG                  	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0006)
#define BOARD_TEMP_FAN_STATUS                 	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0007)
/* FPGA Definitions - TWSI/I2C Register Addresses */
#define BOARD_TEMP_SENSOR_TWSI_CTRL_REG  	  	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0008)
#define BOARD_TEMP_SENSOR_TWSI_ADDR_UPPER_REG 	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0009)
#define BOARD_TEMP_SENSOR_TWSI_ADDR_LOWER_REG 	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000A)
#define BOARD_TEMP_SENSOR_TWSI_DATA_REG       	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000B)
#define BOARD_EEPROM_TWSI_CTRL_REG            	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000C)
#define BOARD_EEPROM_TWSI_ADDR_UPPER_REG      	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000D)
#define BOARD_EEPROM_TWSI_ADDR_LOWER_REG      	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000E)
#define BOARD_EEPROM_TWSI_DATA_REG            	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000F)

#define BOARD_SFP3_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0010)
#define BOARD_SFP3_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0011)
#define BOARD_SFP3_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0012)
#define BOARD_SFP3_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0013)
#define BOARD_SFP2_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0014)
#define BOARD_SFP2_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0015)
#define BOARD_SFP2_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0016)
#define BOARD_SFP2_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0017)
#define BOARD_SFP1_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0018)
#define BOARD_SFP1_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0019)
#define BOARD_SFP1_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001A)
#define BOARD_SFP1_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001B)
#define BOARD_SFP0_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001C)
#define BOARD_SFP0_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001D)
#define BOARD_SFP0_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001E)
#define BOARD_SFP0_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001F)

/* This is the reg to control the upper 3 address lines to the bootflash */
#define BOARD_BOOT_FLASH_UPPER_ADDR_BITS_REG	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0020)
#define BOARD_MISC_FUNCTIONS_REG            	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0021)
#define BOARD_PHY_INTERRUPT_REG             	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0022)

#define BOARD_FIT_KEY_CODE_REG              	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0040)
#define BOARD_FIT_OSCILLATOR_CTRL_REG       	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0041)

/* MDIO Address of the M88E1111 PHYs*/
#define BOARD_PHY0_MDIO_ADDR				0x40
#define BOARD_PHY1_MDIO_ADDR				0x41
#define BOARD_PHY2_MDIO_ADDR				0x42
#define BOARD_PHY3_MDIO_ADDR				0x43

/* MDIO Address of the AMCC 2025 10G PHY*/
#define BOARD_10G_PHY0_MDIO_ADDR			0x00
#define BOARD_10G_PHY1_MDIO_ADDR			0x01

#define BOARD_TWSI_RUN_BIT                  0x80
#define BOARD_TWSI_ERROR_BIT                0x40

#define BOARD_TWSI_RUN_READ_VAL             0x80
#define BOARD_TWSI_RUN_WRITE_VAL            0x81

#define BOARD_TXCR_CH0_EN                   0x01
#define BOARD_TXCR_CH1_EN                   0x02
#define BOARD_TXCR_CH2_EN                   0x04
#define BOARD_TXCR_CH3_EN                   0x08

#define BOARD_LED_GREEN                     0x08
#define BOARD_LED_YELLOW                    0x04

#define SWFB_COMMAND_MAX                    512

/* Fan controller and temperature sensor registers */
#define BOARD_TEMP_SENSOR_LOCAL_ADDR            0x0A
#define BOARD_TEMP_SENSOR_REMOTE_ADDR           0x0B

/*****************************************************************************************/
/***************************** SFP, SFP+, and PHYs STUFF *********************************/
/*****************************************************************************************/
#define MAX_NUM_SFP                                     4

#define ID                                              0
#define EXT_ID                                          1
#define CONNECTOR                                       2
#define TRANSCEIVER_3                                   3
#define TRANSCEIVER_4                                   4
#define TRANSCEIVER_5                                   5
#define TRANSCEIVER_6                                   6
#define TRANSCEIVER_7                                   7
#define TRANSCEIVER_8                                   8
#define TRANSCEIVER_9                                   9
#define TRANSCEIVER_10                                  10
#define FIBER_9_125MM_UNITS_KM                          14
#define FIBER_9_125MM_UNITS_100M                        15
#define FIBER_50_125MM_UNITS_10M                        16
#define FIBER_62P5_125MM_UNITS_10M                      17
#define COPPER_UNITS_M                                  18

#define UNSPECIFIED                                     0
#define LC                                              7
#define VACANT                                          0xFF

#define SFP_VS_BASE                                     0x600

#define CONTROL_REG                                     0
#define STATUS_REG                                      1
#define AUTONEG_ADVERTISEMENT                           4
#define CONTROL_REG_1000BASE_T                          9
#define EXTENDED_PHY_SPECIFIC_CONTROL_REG               20
#define EXTENDED_ADDRESS_REG                            22
#define LED_CONTROL_REG                                 24
#define EXTENDED_PHY_SPECIFIC_CONTROL_2_REG             26
#define EXTENDED_PHY_SPECIFIC_STATUS_REG                27

#define CLAUSE22_NOT_USED           0x1F /* all 5 bits set to 1's */
#define AMCC_HEARTBEAT_THRESHOLD    2      /* used to check if the phy is alive */

#define AMCC_DEV_ADDR_PMA_PMD           1
#define AMCC_DEV_ADDR_WIS               2
#define AMCC_DEV_ADDR_PCS               3
#define AMCC_DEV_ADDR_XGXS              4

#define QT2025_PCS_REG_UC_STATUS        0xD7FD /* returns boot status, SFP status, and link status */
#define QT2025_PCS_REG_FW_HEARTB        0xD7EE /* heartbeat register, if the phy is booted this register will increment from 0x00 to 0xff*/
#define QT2025_PCS_REG_PHASE_REG        0xD653 /* heartbeat register, if the phy is booted this register will increment from 0x00 to 0xff*/
#define QT2025_PMA_PMD_CTRL1_REG        0x0000
#define QT2025_PMA_MDIO_RESETS_REG      0xC300
#define QT2025_PMA_UC8051_CFG_REG       0xC302
#define QT2025_PMA_I2C_SLAVE_ADDR_REG   0xC318
#define QT2025_PMA_UC8051_SPARE_2_REG   0xC319
#define QT2025_PMA_UC8051_SPARE_3_REG   0xC31A
#define QT2025_PCS_10G_R_SEED_B0_REG    0x0026
#define QT2025_PCS_10G_R_SEED_B1_REG    0x0027
#define QT2025_PCS_10G_R_SEED_B2_REG    0x0028
#define QT2025_PMA_PMD_MODE_REG         0xC301
#define QT2025_XDRV_CTRL_5_REG          0xC05A
#define QT2025_PMA_PMD_PAD_IN_STATUS_REG 0xD002
#define QT2025_PMA_PMD_PAD_IN_INV_REG    0xD003
#define QT2025_GPIO_LED1_REG            0xD006
#define QT2025_GPIO_LED2_REG            0xD007
#define QT2025_PCS_FW_VERSION1_REG      0xD7F3
#define QT2025_PCS_FW_VERSION2_REG      0xD7F4
#define QT2025_PCS_FW_VERSION3_REG      0xD7F5
#define QT2025_PCS_FW_BUILD1_REG        0xD7F6
#define QT2025_PCS_FW_BUILD2_REG        0xD7F7
#define QT2025_PCS_FW_BUILD3_REG        0xD7F8

/**
 * Used to determine what type of I/O is on the front of the 
 * card. 
 */

#define SFP_COPPER			0x00
#define SFP_DIRECT_ATTACHED	0x04
#define SFP_FIBER			0x07

#define SFP_TYPE( x )								\
	(( x == 0xFF || x < 0 ) ? VACANT :			\
	( x & 0x8 ) ? SFP_COPPER :						\
	( (x & 0xF) == 0x4 ) ? SFP_DIRECT_ATTACHED : SFP_FIBER )
#define SFP_STRING( x )								\
	(( x == SFP_FIBER ) ? "F " :					\
	 ( x == SFP_COPPER ) ? "C " :				\
	 ( x == SFP_DIRECT_ATTACHED ) ? "DA " : "V " )

#define  PHY_PRESENT            0x00
#define  SFP_PRESENT            0x02
#define  SFP_10G_PRESENT        0x04
#define  SFP_10G_DUAL_PRESENT   0x06

#define IS_SFP_PRESENT              ((*BOARD_ID_DIPSWITCH_REG & 0x0E) == SFP_PRESENT)
/* flag to check if there is a 10G phy on the board. It detects both 56511 and 56512(dual port) cards. */
#define IS_10G_PHY_PRESENT          (((*BOARD_ID_DIPSWITCH_REG & 0x0E) == SFP_10G_PRESENT) || IS_10G_DUAL_PHY_PRESENT)
/* flag to check if we have a 56512 dual port card. It only detects dual port cards */
#define IS_10G_DUAL_PHY_PRESENT     ((*BOARD_ID_DIPSWITCH_REG & 0x0E) == SFP_10G_DUAL_PRESENT)

/*****************************************************************************************/
/************************** END SFP, SFP+, and PHYs STUFF ********************************/
/*****************************************************************************************/


#define CFG_64BIT_VSPRINTF  1
#define CFG_64BIT_STRTOUL   1

/* Set bootdelay to 0 for immediate boot */
#define CONFIG_BOOTDELAY	0	/* autoboot after X seconds	*/

#define CONFIG_BAUDRATE					115200
#define CONFIG_DOWNLOAD_BAUDRATE		115200

/* valid baudrates */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
#undef	CONFIG_BOOTARGS


#define CFG_LOAD_ADDR       0x100000
#define CFG_BOOTOCT_ADDR    0x100000

#define CONFIG_MII

/*
** Define CONFIG_PCI only if the system is known to provide a PCI
** clock to Octeon.  A bus error exception will occur if the inactive
** Octeon PCI core is accessed.  U-boot is not currently configured to
** recover when a exception occurs.
*/
#if CONFIG_OCTEON_PCI_UBOOT
    #define CONFIG_PCI
#endif
/*-----------------------------------------------------------------------
 * PCI Configuration
 */
#if defined(CONFIG_PCI)

    #define PCI_CONFIG_COMMANDS (CFG_CMD_PCI)

/*
** Define CONFIG_OCTEON_PCI_HOST = 1 to map the pci devices on the
** bus.  Define CONFIG_OCTEON_PCI_HOST = 0 for target mode when the
** host system performs the pci bus mapping instead.  Note that pci
** commands are enabled to allow access to configuration space for
** both modes.
*/
    #ifndef CONFIG_OCTEON_PCI_HOST
        #define CONFIG_OCTEON_PCI_HOST	0
    #endif

    #if (CONFIG_OCTEON_PCI_HOST)
        #define CONFIG_PCI_PNP
    #endif /* CONFIG_OCTEON_PCI_HOST */
#else  /* CONFIG_PCI */
    #define PCI_CONFIG_COMMANDS 0
#endif /* CONFIG_PCI */

/*
** The W3860 does not use the internal arbiter in Octeon.
** Enable this for boards that do.
*/
#undef USE_OCTEON_INTERNAL_ARBITER

/* Support for Intel 8254x gigabit chips. */
#undef CONFIG_E1000

/* Define this to enable built-in octeon ethernet support */
#define OCTEON_RGMII_ENET
/* Define this to enable spi4000 support */
#undef OCTEON_SPI4000_ENET

/* Enable Octeon built-in networking if either SPI or RGMII support is enabled */
#if defined(OCTEON_RGMII_ENET) || defined(OCTEON_SPI4000_ENET)
    #define OCTEON_INTERNAL_ENET
#endif

#if CONFIG_OCTEON_PCI_HOST
    #define EXTRA_INCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | PCI_CONFIG_COMMANDS )
    #define EXTRA_EXCLUDE_COMMANDS   (0)
#elif  defined(OCTEON_INTERNAL_ENET)
    #define EXTRA_INCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII)
    #define EXTRA_EXCLUDE_COMMANDS   (0)
#else
    #define EXTRA_INCLUDE_COMMANDS   (0)
    #define EXTRA_EXCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | PCI_CONFIG_COMMANDS )
#endif

/*-----------------------------------------------------------------------
 * U-boot Commands Configuration
 */
/* Srecord loading seems to be busted - checking for ctrl-c eats bytes */
#define CONFIG_COMMANDS         ((CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_OCTEON | CFG_CMD_LOADB | CFG_CMD_FLASH \
                                  | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2 | CFG_CMD_RUN \
                                  | CFG_CMD_EEPROM | CFG_CMD_I2C \
                                  | USB_COMMAND | CFG_CMD_ASKENV \
                                  | CFG_CMD_OCTEON_BOOTLOADER_UPDATE | EXTRA_INCLUDE_COMMANDS)\
                                  & ~(FAILSAFE_EXCLUDE_COMMANDS | CFG_CMD_FPGA | CFG_CMD_BDI \
                                   | CFG_CMD_BEDBUG | CFG_CMD_BOOTD | CFG_CMD_LOADS \
                                   | CFG_CMD_NFS | EXTRA_EXCLUDE_COMMANDS))

#include <cmd_confdefs.h>

/*-----------------------------------------------------------------------
 * Networking Configuration
 */
#if (CONFIG_COMMANDS & CFG_CMD_NET)
    #define CONFIG_NET_MULTI

    #ifdef CONFIG_PCI_PNP
/*
** Enable PCI networking devices if PCI is auto configured by u-boot.
*/
        #define CONFIG_NATSEMI
    #endif /* CONFIG_PCI_PNP */

    #define CONFIG_BOOTP_DEFAULT		(CONFIG_BOOTP_SUBNETMASK | \
					CONFIG_BOOTP_GATEWAY	 | \
					CONFIG_BOOTP_HOSTNAME	 | \
					CONFIG_BOOTP_BOOTPATH)

    #define CONFIG_BOOTP_MASK		CONFIG_BOOTP_DEFAULT
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */


#define CONFIG_NET_RETRY_COUNT 5

#define CONFIG_AUTO_COMPLETE 1
#define CFG_CONSOLE_INFO_QUIET 1
#define CFG_DEVICE_NULLDEV
#define CFG_CONSOLE_IS_IN_ENV

#define CONFIG_DOS_PARTITION 1

#define CFG_IDE_MAXBUS 1
#define CFG_IDE_MAXDEVICE 1

#ifdef CFG_CMD_EEPROM
    #define CFG_I2C_EEPROM_ADDR_LEN 2
    #define CFG_I2C_EEPROM_ADDR     BOARD_EEPROM_TWSI_ADDR
#endif

/* Base address of Common memory for Compact flash */
#define CFG_ATA_BASE_ADDR  OCTEON_CF_COMMON_BASE_ADDR

/* Offset from base at which data is repeated so that it can be
** read as a block */
#define CFG_ATA_DATA_OFFSET     0x400

/* Not sure what this does, probably offset from base
** of the command registers */
#define CFG_ATA_REG_OFFSET      0

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory      */
#ifdef CONFIG_OCTEON_FAILSAFE
#define	CFG_PROMPT		"Octeon w56xx Failsafe bootloader# "	/* Monitor Command Prompt    */
#else
#if CONFIG_RAM_RESIDENT
#define	CFG_PROMPT		"Octeon w56xx(ram)# "	/* Monitor Command Prompt    */
#else
#define	CFG_PROMPT		"Octeon w56xx# "	/* Monitor Command Prompt    */
#endif
#endif

#define CFG_MAX_PROMPT_SIZE 50

#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
#define	CFG_PBSIZE (CFG_CBSIZE+CFG_MAX_PROMPT_SIZE+16)  /* Print Buffer Size */
#define	CFG_MAXARGS		64		/* max number of command args*/

#define CFG_MALLOC_LEN		64*1024

#define CFG_BOOTPARAMS_LEN	16*1024

#define CFG_HZ			500000000ull      /* FIXME causes overflow in net.c */

#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */


#define CFG_MEMTEST_START	(CFG_SDRAM_BASE + 0x100000)
#define CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0xffffff)

#if CONFIG_L2_ONLY
#define L2_ONLY_ENV "octeon_reserved_mem_load_size=0xc0000\0""octeon_reserved_mem_linux_size=0\0"
#else
#define L2_ONLY_ENV
#endif

/**********************************/
/* define other ENV settings here */
/**********************************/
#if defined( UBOOT_LEGACY_NORMAL )
    #define CONFIG_SWFB_FLASH_ADDR "swfb_flash_addr=b7fe0000\0"
#else
    #define CONFIG_SWFB_FLASH_ADDR "swfb_flash_addr=b8000000\0"
#endif /*UBOOT_LEGACY_NORMAL*/


#if defined(CONFIG_OCTEON_FAILSAFE)
    #define CONFIG_BOOTLOADER_UPDATE_ENV_SETTING 	\
	"bootloader_flash_update_failsafe=protect off 0xb7c00000 0xb7cfffff;erase 0xb7c00000 0xb7cfffff;cp.b $(fileaddr) 0xb7c00000 0xf0000\0"	\
	"bootloader_flash_update_normal=protect off 0xb7e00000 0xb7efffff;erase 0xb7e00000 0xb7efffff;cp.b $(fileaddr) 0xb7e00000 0xf0000; validatenfi\0"
#else                              
    #if defined( UBOOT_LEGACY_NORMAL ) 
        #define CONFIG_BOOTLOADER_UPDATE_ENV_SETTING 	\
	"bootloader_flash_update=protect off 0xb7c00000 0xb7cfffff;erase 0xb7c00000 0xb7cfffff;cp.b $(fileaddr) 0xb7c00000 0xf0000\0"
    #else                              
        #define CONFIG_BOOTLOADER_UPDATE_ENV_SETTING 	\
	"bootloader_flash_update=protect off 0xb7e00000 0xb7efffff;erase 0xb7e00000 0xb7efffff;cp.b $(fileaddr) 0xb7e00000 0xf0000; validatenfi\0"
    #endif /* UBOOT_LEGACY_NORMAL */   
#endif /* CONFIG_OCTEON_FAILSAFE */

#define CONFIG_EXTRA_ENV_SETTINGS                                       \
        CONFIG_BOOTLOADER_UPDATE_ENV_SETTING    \
        "autoload=yes\0"                                        \
        "swfb_cmd=bootoctlinux\0"               \
        CONFIG_SWFB_FLASH_ADDR  \
        "swfb_ram_addr=$(loadaddr)\0"           \
        "swfb_image_size=1800000\0"             \
        "pmem_ddr=n\0" \
        L2_ONLY_ENV             \
        ""

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* These enable PCI console */
#define CFG_PCI_CONSOLE 1
#define CFG_CONSOLE_IS_IN_ENV

#define	CFG_ENV_IS_IN_FLASH	1

#define CFG_FLASH_SIZE	(128*1024*1024)	/* Flash size (Mbytes) */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	(1024)	/* max number of sectors on one chip */

/* Remapped base of flash for entire flash access */
/* Without remapping there would be a 4Meg limit */
/* The entire flash size is subtacted to preserve pc continuity */
#define CFG_FLASH_BASE		(0xbfc00000 -  CFG_FLASH_SIZE)
#define CFG_FLASH_PROTECT_LEN   0x80000  /* protect low 512K */

/* The following #defines are needed to get flash environment right */
#define	CFG_MONITOR_BASE	TEXT_BASE
#define	CFG_MONITOR_LEN		(192 << 10)

#define CFG_INIT_SP_OFFSET	0x400000

#define CFG_FLASH_CFI   1
#define CFG_FLASH_CFI_DRIVER   1

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */

#define CFG_FLASH_SECTOR_SIZE             (128 * 1024) /* 128 KBytes */
/* PRE-CS0 remapping */
#define CFG_ENV_SIZE                      CFG_FLASH_SECTOR_SIZE

#if defined( UBOOT_LEGACY_NORMAL )

    #define CFG_UBOOT_SIZE                    (1536 * 1024) /* 1536 KBytes */
    #define CFG_NFI_SIZE                      0
    #define CFG_NFI_SECTOR                    0
    #define CFG_NFI_FASTBOOT_KEY              0

#else /* UBOOT_LEGACY_NORMAL */

    #define CFG_UBOOT_SIZE                    (2 * 1024 * 1024) /* 2MBytes */
    #define CFG_NFI_SIZE                      CFG_FLASH_SECTOR_SIZE
    #define CFG_NFI_SECTOR                    15
    #define CFG_NFI_FASTBOOT_KEY              0x0f1e2d3c

#endif /* UBOOT_LEGACY_NORMAL */

#define CFG_FAILSAFE_BOOTLOADER_BASE      0xbfc00000
#define CFG_NORMAL_BOOTLOADER_BASE        (CFG_FAILSAFE_BOOTLOADER_BASE + CFG_UBOOT_SIZE)

#define CFG_IMAGE_SIZE_MAX                (CFG_UBOOT_SIZE - (CFG_ENV_SIZE + CFG_NFI_SIZE))

/* POST-CS0 remapping */
/* FLASH address map */
#define CFG_FS_BOOTLOADER_BASE            0xb7c00000
#define CFG_NORM_BOOTLOADER_BASE          (CFG_FS_BOOTLOADER_BASE + CFG_UBOOT_SIZE)

#if defined( UBOOT_LEGACY_NORMAL )

    #define CFG_NFI_ADDR                      0
    #define CFG_NFI_FASTBOOT_KEY_ADDR         0
    #define CFG_NFI_IMAGE_SIZE_ADDR           0
    #define CFG_NFI_IMAGE_CHECKSUM_ADDR       0

#else /* UBOOT_LEGACY_NORMAL */                            

    #define CFG_NFI_ADDR                      (CFG_FS_BOOTLOADER_BASE + (CFG_NFI_SECTOR * CFG_FLASH_SECTOR_SIZE))
    #define CFG_NFI_FASTBOOT_KEY_ADDR         (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 8))
    #define CFG_NFI_IMAGE_SIZE_ADDR           (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 16))
    #define CFG_NFI_IMAGE_CHECKSUM_ADDR       (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 24))

#endif /* UBOOT_LEGACY_NORMAL */

#if defined( UBOOT_LEGACY_NORMAL ) || defined( CONFIG_OCTEON_FAILSAFE )
    #define CFG_ENV_ADDR                      ((CFG_FS_BOOTLOADER_BASE + CFG_UBOOT_SIZE)-\
										   (CFG_NFI_SIZE + CFG_ENV_SIZE))
#else
    #define CFG_ENV_ADDR                      ((CFG_NORM_BOOTLOADER_BASE + CFG_UBOOT_SIZE)-\
										   (CFG_NFI_SIZE + CFG_ENV_SIZE))
#endif

#define CFG_IMAGE_NOT_PRESENT             0xFFFFFFFFFFFFFFFF

#define CFG_SWFB_BASE                     (CFG_ENV_ADDR + CFG_ENV_SIZE)


#define CONFIG_FLASH_8BIT

#define CONFIG_NR_DRAM_BANKS	2

#define CONFIG_MEMSIZE_IN_BYTES

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		( 8 * 1024)
#define CFG_ICACHE_SIZE		(32 * 1024)
#define CFG_CACHELINE_SIZE	128

/*-----------------------------------------------------------------------
 * BOARD ID Information
 */
#define DDR2_512MB          0x00
#define DDR2_1GB            0x01
#define DDR2_2GB            0x02
#define DDR2_4GB            0x03

#define EGRESS_IO_VIA_RTM   0x08

/*-----------------------------------------------------------------------
 * DRAM Module Organization
 *
 * Octeon can be configured to use two pairs of DIMM's, lower and
 * upper, providing a 128/144-bit interface or one to four DIMM's
 * providing a 64/72-bit interface.  This structure contains the TWSI
 * addresses used to access the DIMM's Serial Presence Detect (SPD)
 * EPROMS and it also implies which DIMM socket organization is used
 * on the board.  Software uses this to detect the presence of DIMM's
 * plugged into the sockets, compute the total memory capacity, and
 * configure DRAM controller.  All DIMM's must be identical.
 */

#include "octeon_w56xx_shared.h"

#define DRAM_SOCKET_CONFIGURATION		OCTEON_W56XX_DRAM_SOCKET_CONFIGURATION0
#define DRAM_SOCKET_CONFIGURATION_INTERFACE1	OCTEON_W56XX_DRAM_SOCKET_CONFIGURATION1

#if 0  /* Example: Enable for designs that don't use DIMMs with SPD */
/*
** For memory configurations that don't incorporate Serial Presence
** Detect (SPD) the SPD EEPROM can be simulated using a static table
** in memory.  This capability is enabled by defining
** STATIC_DRAM_CONFIG_TABLE to point to the array that contains the
** simulated SPD data.  In this case the DRAM_SOCKET_CONFIGURATION
** table takes on a slightly different function.  Instead of providing
** the TWSII address of each SPD EEPROM a non-zero value indicates
** that the STATIC_DRAM_CONFIG_TABLE should be applied for that DIMM
** interface.  A zero value indicates that no DRAM is present on that
** DIMM interface.
*/
    #define STATIC_512MB_DRAM_CONFIG_TABLE static_512MB_ddr2_spd_data
    #define STATIC_1GB_DRAM_CONFIG_TABLE static_1GB_ddr2_spd_data
    #define STATIC_2GB_DRAM_CONFIG_TABLE static_2GB_ddr2_spd_data
    #define STATIC_4GB_DRAM_CONFIG_TABLE static_4GB_ddr2_spd_data
#endif

/* Board delay in picoseconds */
//#define DDR_BOARD_DELAY		4000 /* ~2500 - ~4500 work so use 3500 */

#endif	/* __CONFIG_H_ */
