/***********************license start************************************
 * Copyright (c) 2005-2007 Cavium Networks (support@cavium.com). All rights
 * reserved.
 *
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *
 *     * Redistributions in binary form must reproduce the above
 *       copyright notice, this list of conditions and the following
 *       disclaimer in the documentation and/or other materials provided
 *       with the distribution.
 *
 *     * Neither the name of Cavium Networks nor the names of
 *       its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written
 *       permission.
 *
 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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 ***********************license end**************************************/

#ifndef __OCTEON_EEPROM_TYPES_H__
#define __OCTEON_EEPROM_TYPES_H__

#include <cvmx-app-init.h>


enum eeprom_types_enum {
    EEPROM_NULL_TYPE = 0,
    EEPROM_CLOCK_DESC_TYPE,
    EEPROM_BOARD_DESC_TYPE,
    EEPROM_CHIP_CAPABILITY_TYPE,
    EEPROM_MAC_ADDR_TYPE,
    EEPROM_VOLT_MULT_TYPE,  /* Not used on 6XXX boards */
    EEPROM_RLDRAM_DESC_TYPE,
#if defined(CONFIG_OCTEON_GEF_BOARD_GENERAL) || defined(CONFIG_OCTEON_GEF_56XX_BOARD_GENERAL) || defined(CONFIG_OCTEON_GEF_63XX_BOARD_GENERAL)
    /* Source IP Information */
    EEPROM_SIPI0_TYPE = 7,
    EEPROM_SIPI1_TYPE,
    EEPROM_SIPI2_TYPE,
    EEPROM_SIPI3_TYPE,
    EEPROM_SIPI4_TYPE,
    EEPROM_SIPI5_TYPE,
    EEPROM_SIPI6_TYPE,
    EEPROM_SIPI7_TYPE,
    EEPROM_SIPI8_TYPE,
    EEPROM_SIPI9_TYPE,
    /* Primary File Information */
    EEPROM_PFI0_IMAGE_TYPE,
    EEPROM_PFI1_IMAGE_TYPE,
    EEPROM_PFI2_IMAGE_TYPE,
    EEPROM_PFI3_IMAGE_TYPE,
    EEPROM_PFI4_IMAGE_TYPE,
    EEPROM_PFI5_IMAGE_TYPE,
    EEPROM_PFI6_IMAGE_TYPE,
    EEPROM_PFI7_IMAGE_TYPE,
    EEPROM_PFI8_IMAGE_TYPE,
    EEPROM_PFI9_IMAGE_TYPE,
    EEPROM_PFI10_IMAGE_TYPE,
    EEPROM_PFI11_IMAGE_TYPE,
    EEPROM_PFI12_IMAGE_TYPE,
    EEPROM_PFI13_IMAGE_TYPE,
    EEPROM_PFI14_IMAGE_TYPE,
    EEPROM_PFI15_IMAGE_TYPE,
    /* Secondary File Information */
    EEPROM_SFI0_IMAGE_TYPE,
    EEPROM_SFI1_IMAGE_TYPE,
    EEPROM_SFI2_IMAGE_TYPE,
    EEPROM_SFI3_IMAGE_TYPE,
    EEPROM_SFI4_IMAGE_TYPE,
    EEPROM_SFI5_IMAGE_TYPE,
    EEPROM_SFI6_IMAGE_TYPE,
    EEPROM_SFI7_IMAGE_TYPE,
    EEPROM_SFI8_IMAGE_TYPE,
    EEPROM_SFI9_IMAGE_TYPE,
    EEPROM_SFI10_IMAGE_TYPE,
    EEPROM_SFI11_IMAGE_TYPE,
    EEPROM_SFI12_IMAGE_TYPE,
    EEPROM_SFI13_IMAGE_TYPE,
    EEPROM_SFI14_IMAGE_TYPE,
    EEPROM_SFI15_IMAGE_TYPE,
    /* Load And Boot Information */
    EEPROM_LABI0_IMAGE_TYPE,
    EEPROM_LABI1_IMAGE_TYPE,
    EEPROM_LABI2_IMAGE_TYPE,
    EEPROM_LABI3_IMAGE_TYPE,
    EEPROM_LABI4_IMAGE_TYPE,
    EEPROM_LABI5_IMAGE_TYPE,
    EEPROM_LABI6_IMAGE_TYPE,
    EEPROM_LABI7_IMAGE_TYPE,
    EEPROM_LABI8_IMAGE_TYPE,
    EEPROM_LABI9_IMAGE_TYPE,
    EEPROM_LABI10_IMAGE_TYPE,
    EEPROM_LABI11_IMAGE_TYPE,
    EEPROM_LABI12_IMAGE_TYPE,
    EEPROM_LABI13_IMAGE_TYPE,
    EEPROM_LABI14_IMAGE_TYPE,
    EEPROM_LABI15_IMAGE_TYPE,
    /* Script ID Active */
    EEPROM_SCRIPT_ID_ACTIVE_TYPE, /* Script ID Active */
    /* Script 0 */
    EEPROM_SCRIPT0_TYPE, /* Script */
    /* Script 1 */
    EEPROM_SCRIPT1_TYPE, /* Script */
    /* Script 2 */
    EEPROM_SCRIPT2_TYPE, /* Script */
    /* Script 3 */
    EEPROM_SCRIPT3_TYPE, /* Script */
    /* POST Information */
    EEPROM_CSUMTESTI0_TYPE,
    EEPROM_CSUMTESTI1_TYPE,
    EEPROM_CSUMTESTI2_TYPE,
    EEPROM_CSUMTESTI3_TYPE,
    EEPROM_MEMTESTI0_TYPE,
    EEPROM_MEMTESTI1_TYPE,
    EEPROM_MEMTESTI2_TYPE,
    EEPROM_MEMTESTI3_TYPE,
    EEPROM_PHYTESTI_TYPE,
    EEPROM_PMEMTESTI_TYPE,
    /* UART-Console Information */
    EEPROM_UARTCONI_TYPE,
    /* UART-MMC Information */
    EEPROM_UARTMMCI_TYPE,
	EEPROM_UBOOT_FAILSAFE_INFO_TYPE,
    EEPROM_UBOOT_NORMAL_INFO_TYPE,
	EEPROM_RLDRAM_TEST_TYPE,
    EEPROM_RTM_MAC_ADDR_TYPE,
#endif /* CONFIG_OCTEON_TNPA3804 || CONFIG_OCTEON_AT5810 || CONFIG_OCTEON_TNPA5804 */
    EEPROM_DDR_CLOCK_DESC_TYPE,
    EEPROM_MODULE_CAPABILITY_TYPE,
    EEPROM_VOLTAGE_TYPE,     /* New for 6XXX boards */
    EEPROM_MULTIPLIER_TYPE,  /* New for 6XXX boards */
    EEPROM_DEFAULT_MODULE_CAPABILITY_TYPE, /* New for 6XXX boards */
    EEPROM_DELETE_ME,  /* TLV marked for deletetion - MCU will skip over, U-BOOT can clean house */
    EEPROM_MAX_TYPE,         
    EEPROM_CUSTOMER_RESERVED_START = 0xf000,  /* Start of range (inclusive) for customer use */
    EEPROM_CUSTOMER_RESERVED_END = 0xff00,    /* End of range (inclusive) for customer use */
    EEPROM_END_TYPE = 0xffff
};

#define ENUM_TYPE_CASE(x)   case x: return(#x + 7);   /* Skip EEPROM_ */
static inline char *eeprom_type_to_string(enum eeprom_types_enum type)
{
    if (type >= EEPROM_CUSTOMER_RESERVED_START && type <= EEPROM_CUSTOMER_RESERVED_END)
        return("Unknown customer tuple type");
    if (type >= EEPROM_MAX_TYPE)
        return("Unknown tuple type");

    switch (type)
    {
        ENUM_TYPE_CASE(EEPROM_NULL_TYPE)
        ENUM_TYPE_CASE(EEPROM_CLOCK_DESC_TYPE)
        ENUM_TYPE_CASE(EEPROM_BOARD_DESC_TYPE)
        ENUM_TYPE_CASE(EEPROM_CHIP_CAPABILITY_TYPE)
        ENUM_TYPE_CASE(EEPROM_MAC_ADDR_TYPE)
        ENUM_TYPE_CASE(EEPROM_VOLT_MULT_TYPE)
        ENUM_TYPE_CASE(EEPROM_RLDRAM_DESC_TYPE)
        ENUM_TYPE_CASE(EEPROM_DDR_CLOCK_DESC_TYPE)
        ENUM_TYPE_CASE(EEPROM_MODULE_CAPABILITY_TYPE)
        ENUM_TYPE_CASE(EEPROM_VOLTAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_MULTIPLIER_TYPE)
        ENUM_TYPE_CASE(EEPROM_DEFAULT_MODULE_CAPABILITY_TYPE)
        ENUM_TYPE_CASE(EEPROM_DELETE_ME)
#if defined(CONFIG_OCTEON_GEF_BOARD_GENERAL) || defined(CONFIG_OCTEON_GEF_56XX_BOARD_GENERAL) || defined(CONFIG_OCTEON_GEF_63XX_BOARD_GENERAL)
        /* Source IP Information */
        ENUM_TYPE_CASE(EEPROM_SIPI0_TYPE)
        ENUM_TYPE_CASE(EEPROM_SIPI1_TYPE)
        ENUM_TYPE_CASE(EEPROM_SIPI2_TYPE)
        ENUM_TYPE_CASE(EEPROM_SIPI3_TYPE)
        ENUM_TYPE_CASE(EEPROM_SIPI4_TYPE)
        ENUM_TYPE_CASE(EEPROM_SIPI5_TYPE)
        ENUM_TYPE_CASE(EEPROM_SIPI6_TYPE)
        ENUM_TYPE_CASE(EEPROM_SIPI7_TYPE)
        ENUM_TYPE_CASE(EEPROM_SIPI8_TYPE)
        ENUM_TYPE_CASE(EEPROM_SIPI9_TYPE)
        /* Primary File Information */
        ENUM_TYPE_CASE(EEPROM_PFI0_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI1_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI2_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI3_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI4_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI5_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI6_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI7_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI8_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI9_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI10_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI11_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI12_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI13_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI14_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_PFI15_IMAGE_TYPE)
        /* Secondary File Information */
        ENUM_TYPE_CASE(EEPROM_SFI0_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI1_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI2_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI3_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI4_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI5_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI6_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI7_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI8_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI9_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI10_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI11_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI12_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI13_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI14_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_SFI15_IMAGE_TYPE)
        /* Load And Boot Information */
        ENUM_TYPE_CASE(EEPROM_LABI0_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI1_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI2_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI3_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI4_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI5_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI6_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI7_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI8_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI9_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI10_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI11_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI12_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI13_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI14_IMAGE_TYPE)
        ENUM_TYPE_CASE(EEPROM_LABI15_IMAGE_TYPE)
        /* Script ID Active */
        ENUM_TYPE_CASE(EEPROM_SCRIPT_ID_ACTIVE_TYPE) /* Script ID Active */
        /* Script 0 */
        ENUM_TYPE_CASE(EEPROM_SCRIPT0_TYPE) /* Script */
        /* Script 1 */
        ENUM_TYPE_CASE(EEPROM_SCRIPT1_TYPE) /* Script */
        /* Script 2 */
        ENUM_TYPE_CASE(EEPROM_SCRIPT2_TYPE) /* Script */
        /* Script 3 */
        ENUM_TYPE_CASE(EEPROM_SCRIPT3_TYPE) /* Script */
        /* POST Information-Checksum Test */
        ENUM_TYPE_CASE(EEPROM_CSUMTESTI0_TYPE)
        ENUM_TYPE_CASE(EEPROM_CSUMTESTI1_TYPE)
        ENUM_TYPE_CASE(EEPROM_CSUMTESTI2_TYPE)
        ENUM_TYPE_CASE(EEPROM_CSUMTESTI3_TYPE)
        /* POST Information-Memory Test */
        ENUM_TYPE_CASE(EEPROM_MEMTESTI0_TYPE)
        ENUM_TYPE_CASE(EEPROM_MEMTESTI1_TYPE)
        ENUM_TYPE_CASE(EEPROM_MEMTESTI2_TYPE)
        ENUM_TYPE_CASE(EEPROM_MEMTESTI3_TYPE)
        /* POST Information-PHY Test */
        ENUM_TYPE_CASE(EEPROM_PHYTESTI_TYPE)
        /* POST Information-PMEM Test */
        ENUM_TYPE_CASE(EEPROM_PMEMTESTI_TYPE)
        /* UART-Console Information */
        ENUM_TYPE_CASE(EEPROM_UARTCONI_TYPE)
        /* UART-MMC Information */
        ENUM_TYPE_CASE(EEPROM_UARTMMCI_TYPE)
		/* UBOOT Failsafe Information */
        ENUM_TYPE_CASE(EEPROM_UBOOT_FAILSAFE_INFO_TYPE)
        /* UBOOT Normal Information */
        ENUM_TYPE_CASE(EEPROM_UBOOT_NORMAL_INFO_TYPE)
		/* POST RLDRAM Information */
        ENUM_TYPE_CASE(EEPROM_RLDRAM_TEST_TYPE)
		/* RTM MAC Address Information */
        ENUM_TYPE_CASE(EEPROM_RTM_MAC_ADDR_TYPE)

#endif /* CONFIG_OCTEON_TNPA3804 || CONFIG_OCTEON_AT5810 || CONFIG_OCTEON_TNPA5804 */

        ENUM_TYPE_CASE(EEPROM_MAX_TYPE)
        ENUM_TYPE_CASE(EEPROM_CUSTOMER_RESERVED_START)
        ENUM_TYPE_CASE(EEPROM_CUSTOMER_RESERVED_END)
        ENUM_TYPE_CASE(EEPROM_END_TYPE)
        default:
            return("Unknown tuple type");
    }
    return("Unknown tuple type");
}

/* Header used by all blocks in the EEPROM.  Checksum covers
** the header (excluding the checksum) and all payload bytes.
*/
typedef  struct {
    uint16_t type;
    uint16_t length;
    uint8_t minor_version;  /* Minor version increment indicates backward compatible change */
    uint8_t major_version;  /* Major version must be changed if incompatible change made */
    uint16_t checksum;
} octeon_eeprom_header_t;



/*
** There is a structure defined for each major revision of each tuple type, with
** the generic (non-versioned) name referring to the current version.
** The current version (major/minor) for each tuple type is defined for
** each tuple as well.
**
*/



/* Maximum length allowed for a tuple.  This is used for simple
** header validity checks.
*/
#define OCTEON_EEPROM_MAX_TUPLE_LENGTH   256

/********************************************************************/
/*
** NOTE: The clock descriptor is used by the MCU, so any changes made to the
** structure/type definitions must be made there as well.
*/

struct octeon_eeprom_clock_desc_v1 {
    octeon_eeprom_header_t header;
    uint16_t    ddr_clock_mhz;           /* May be overridden by ddr_clock_desc tuple */
    uint16_t    cpu_ref_clock_mhz_x_8;   /* Ref clock Mhz * 8 */
    uint16_t    spi_clock_mhz;
};

/* Unused fields should be set to 0 */
struct octeon_eeprom_clock_desc_v2 {
    octeon_eeprom_header_t header;
    uint16_t    ddr_clock_mhz;
    uint16_t    cpu_ref_clock_mhz_x_8;  /* Ref clock Mhz * 8 */
    uint16_t    dfa_ref_clock_mhz_x_8;  /* Ref clock Mhz * 8 */
    uint16_t    spi_clock_mhz;
};

/* We'll need to change this based on chip type, as Octeon uses version 1, and newer 
** chips use version 2 */
/* This define always corresponds to the latest structure version, and the 
** latest structure version always has the generic name */
#define OCTEON_EEPROM_CLOCK_DESC_MAJOR_VER    2
#define OCTEON_EEPROM_CLOCK_DESC_MINOR_VER    0
typedef struct octeon_eeprom_clock_desc_v2 octeon_eeprom_clock_desc_t;

struct octeon_eeprom_cpu_mul_vol_desc_v1 {
     octeon_eeprom_header_t header;
     uint16_t    cpu_voltage_millivolts; /* voltage in millivolts */
     uint16_t    cpu_multiplier;         /* Raw value */
};
#define OCTEON_EEPROM_CPU_MUL_VOL_DESC_VER    1
typedef struct octeon_eeprom_cpu_mul_vol_desc_v1 octeon_eeprom_cpu_mul_vol_desc_t;
/********************************************************************/




/********************************************************************/
#ifndef OCTEON_SERIAL_LEN
#define OCTEON_SERIAL_LEN 20
#endif
struct octeon_eeprom_board_desc_v1 {
    octeon_eeprom_header_t header;
    uint16_t    board_type;
    uint8_t     rev_major;
    uint8_t     rev_minor;
    uint16_t    chip_type;  /* Deprecated */
    uint8_t     chip_rev_major;  /* Deprecated */
    uint8_t     chip_rev_minor;  /* Deprecated */
    uint8_t     serial_str[OCTEON_SERIAL_LEN];  /* Must be nul terminated */
};
#define OCTEON_EEPROM_BOARD_DESC_MAJOR_VER    1
#define OCTEON_EEPROM_BOARD_DESC_MINOR_VER    0
typedef struct octeon_eeprom_board_desc_v1 octeon_eeprom_board_desc_t;
/********************************************************************/



/********************************************************************/
struct octeon_eeprom_chip_capability_v1 {
    octeon_eeprom_header_t header;
    uint16_t coremask;
    uint16_t voltage_x100;
    uint16_t cpu_freq_mhz;
};
#define OCTEON_EEPROM_CHIP_CAPABILITY_MAJOR_VER    1
#define OCTEON_EEPROM_CHIP_CAPABILITY_MINOR_VER    0
typedef struct octeon_eeprom_chip_capability_v1 octeon_eeprom_chip_capability_t;
/********************************************************************/

/********************************************************************/
struct octeon_eeprom_module_capability_v1 {
    octeon_eeprom_header_t header;
    uint16_t protocol;
    uint16_t speed;
    uint16_t cfg_flags;  /* Reserved for future use (added in rev 1.1)   */
  /************************************************************************/
  /*  Flags Definition                                                    */
  /*  bit 0 - Reverse Lanes (added in 1.1)                                */
  /*  bit 1 - Use Common Ref Clock (added in 1.1)                         */
  /*  bit 2 - SRIO End Point Mode (SRIO is normally host) (added in 1.2)  */
  /*  bits [3-13] - Reserved for future use, set to 0 when programming    */
  /*  bit 14 - invalid config (used internally by MCU only)(added in 1.3) */
  /*  bit 15 - ignore TLV if set to 1 (added in 1.1)                      */
  /************************************************************************/
};
#define OCTEON_EEPROM_MODULE_CAPABILITY_MAJOR_VER    1
#define OCTEON_EEPROM_MODULE_CAPABILITY_MINOR_VER    3
typedef struct octeon_eeprom_module_capability_v1 octeon_eeprom_module_capability_t;
/********************************************************************/


/********************************************************************/
struct octeon_eeprom_default_module_capability_v1 {
    octeon_eeprom_header_t header;
    uint16_t qlm_number;
    uint16_t protocol;
    uint16_t speed;
    uint16_t cfg_flags;  /* Reserved for future use (added in rev 1.0)   */
  /************************************************************************/
  /*  Flags Definition                                                    */
  /*  bit 0 - Reverse Lanes (added in 1.0)                                */
  /*  bit 1 - Use Common Ref Clock (added in 1.0)                         */
  /*  bit 2 - SRIO End Point Mode (SRIO is normally host) (added in 1.1)  */
  /*  bits [3-12] - Reserved for future use, set to 0 when programming    */
  /*  bit 14 - invalid config (used internally by MCU only)(added in 1.2) */
  /*  bit 15 - ignore TLV if set to 1                                     */
  /************************************************************************/
  uint16_t raw_cfg;  //used to set a specific setting on the cfg switches - keep 0xFFFF to not use
  uint16_t raw_speed;  //used to set a specific setting on the speed switches - keep 0xFFFF to not use
};
#define OCTEON_EEPROM_DEFAULT_MODULE_CAPABILITY_MAJOR_VER    1
#define OCTEON_EEPROM_DEFAULT_MODULE_CAPABILITY_MINOR_VER    2
typedef struct octeon_eeprom_default_module_capability_v1 octeon_eeprom_default_module_capability_t;
/********************************************************************/



/********************************************************************/
struct octeon_eeprom_mac_addr_v1 {
    octeon_eeprom_header_t header;
    uint8_t mac_addr_base[6];
    uint8_t count;
};
struct octeon_eeprom_mac_addr_v2 {
    octeon_eeprom_header_t header;
    uint8_t fabric_int0[6];
    uint8_t fabric_int1[6];
    uint8_t fabric_int2[6];
    uint8_t fabric_int3[6];
    uint8_t fp_int0[6];
    uint8_t fp_int1[6];
    uint8_t fp_int2[6];
    uint8_t fp_int3[6];
    uint8_t base_int0[6];
    uint8_t base_int1[6];
    uint8_t count;
};

struct octeon_eeprom_mac_addr_v3 {
    octeon_eeprom_header_t header;
    uint8_t qlm1_port[6];
    uint8_t qlm3_port[6];
    uint8_t amc_port0[6];
    uint8_t amc_port1[6];	
    uint8_t count;
};


#ifdef CONFIG_OCTEON_TNPA5651X
#define OCTEON_NUM_MACS                     4
#define OCTEON_EEPROM_MAC_ADDR_MAJOR_VER    3
#else
#define OCTEON_NUM_MACS                     10
#define OCTEON_EEPROM_MAC_ADDR_MAJOR_VER    2
#endif

#define OCTEON_EEPROM_MAC_ADDR_MINOR_VER    0

#ifdef CONFIG_OCTEON_TNPA5854
typedef struct octeon_eeprom_mac_addr_v1 octeon_eeprom_mac_addr_old;
typedef struct octeon_eeprom_mac_addr_v2 octeon_eeprom_mac_addr_t;
#else
#ifdef CONFIG_OCTEON_TNPA5651X
typedef struct octeon_eeprom_mac_addr_v1 octeon_eeprom_mac_addr_old;
typedef struct octeon_eeprom_mac_addr_v3 octeon_eeprom_mac_addr_t;
#else
typedef struct octeon_eeprom_mac_addr_v1 octeon_eeprom_mac_addr_t;
#endif
#endif

/********************************************************************/



/********************************************************************/
struct octeon_eeprom_voltage_multiplier_v1 {
    octeon_eeprom_header_t header;
    uint16_t voltage_millivolts;
    uint16_t cpu_multiplier;
};
#define OCTEON_EEPROM_VOLT_MULT_MAJOR_VER    1
#define OCTEON_EEPROM_VOLT_MULT_MINOR_VER    0
typedef struct octeon_eeprom_voltage_multiplier_v1 octeon_eeprom_voltage_multiplier_t;
/********************************************************************/



/********************************************************************/
/* This tuple specifies options for RLDRAM on CN38XX/CN58XX boards.
** Only stuffing related options are stored here - the address swizzle
** is specified in the initialization code for each board type. */
struct octeon_eeprom_rldram_desc_v1 {
    octeon_eeprom_header_t header;
    uint16_t rld0_mbytes;
    uint16_t rld1_mbytes;
    uint8_t rld0_bunks;
    uint8_t rld1_bunks;
    uint16_t max_rld_clock_mhz; 
};
#define OCTEON_EEPROM_RLDRAM_DESC_MAJOR_VER    1
#define OCTEON_EEPROM_RLDRAM_DESC_MINOR_VER    0
typedef struct octeon_eeprom_rldram_desc_v1 octeon_eeprom_rldram_desc_t;
/********************************************************************/


/********************************************************************/
/* If present, this tuple overrides any ddr clock specified in the
** the clock descriptor tuple.
** If ddr_ref_hz is 0, then the CPU reference frequency is used.
*/
struct octeon_eeprom_ddr_clock_desc_v1 {
    octeon_eeprom_header_t header;
    uint32_t ddr_ref_hz;        /* Reference clock input in Hz */
                                /* NOTE: ddr_ref_hz is often ignored,
                                ** as many Octeon chips only support a 50 MHz
                                ** reference clock. */
    uint32_t ddr_clock_hz;      /* Desired DDR clock output in Hz */
};
#define OCTEON_EEPROM_DDR_CLOCK_DESC_MAJOR_VER    1
#define OCTEON_EEPROM_DDR_CLOCK_DESC_MINOR_VER    0
typedef struct octeon_eeprom_ddr_clock_desc_v1 octeon_eeprom_ddr_clock_desc_t;
/********************************************************************/

#if defined(CONFIG_OCTEON_GEF_BOARD_GENERAL) || defined(CONFIG_OCTEON_GEF_56XX_BOARD_GENERAL) || defined(CONFIG_OCTEON_GEF_63XX_BOARD_GENERAL)
#define IP_ADDR_MAX_LEN 16
#define SIPI_ID_MAX 9
#define SIPI_ETH_PORT_ID_MAX_LEN    16
/****** Source IP Information ******/
#define SIPI_SETENV_ETHACT_CMD    "setenv ethact "
#define SIPI_DHCP_CMD             "dhcp"
#define SIPI_SETENV_IPADDR_CMD    "setenv ipaddr "
#define SIPI_SETENV_NETMASK_CMD   "setenv netmask "
#define SIPI_SETENV_GATEWAYIP_CMD "setenv gatewayip "
struct octeon_eeprom_source_ip_info_v1 {
    octeon_eeprom_header_t header;
    uint8_t eth_port_id[SIPI_ETH_PORT_ID_MAX_LEN]; /* Ethernet Port ID */
    uint8_t dhcp_enable; /* DHCP Enable */
    uint16_t dhcp_num_retries; /* DHCP Number Retries */
    uint8_t ip_addr[IP_ADDR_MAX_LEN]; /* IP Address */
    uint8_t subnet_mask[IP_ADDR_MAX_LEN]; /* Subnet Mask */
    uint8_t default_gateway[IP_ADDR_MAX_LEN]; /* Default Gateway */
};
#define OCTEON_EEPROM_SOURCE_IP_INFO_VER    1
typedef struct octeon_eeprom_source_ip_info_v1 octeon_eeprom_source_ip_info_t;

#define IMAGE_ID_MAX 15
/****** File Information ******/
#define FI_SETENV_SERVERIP_CMD "setenv serverip "
#define FI_TFTPBOOT_CMD        "tftpboot "
#define FI_CPB_CMD             "cp.b "
#define FI_FFL_MAX_LEN         16
#define FI_FFTS_MAX_LEN        8
#define FI_FN_MAX_LEN          32
#define FI_BOOTLINUX           0
#define FI_BOOTOCT             1
#define FI_BOOTELF             2
struct octeon_eeprom_file_info_v1 {
    octeon_eeprom_header_t header;
    uint8_t flash_file_location[FI_FFL_MAX_LEN]; /* "-" implies Network-TFTP otherwise FLASH based */
    uint8_t flash_file_transfer_size[FI_FFTS_MAX_LEN]; /* "-" implies no load from FLASH to RAM */
    uint8_t sipi_id; /* SIPI ID */
    uint8_t tftp_file_name[FI_FN_MAX_LEN]; /* TFTP filename  */
    uint8_t tftp_server[IP_ADDR_MAX_LEN]; /* TFTP Server IP Address */
    uint16_t tftp_num_retries; /* TFTP Number Retries */
};
#define OCTEON_EEPROM_FILE_INFO_VER    1
typedef struct octeon_eeprom_file_info_v1 octeon_eeprom_file_info_t;

/****** Load And Boot Information ******/
#define BOOT_COMMAND_MAX_LEN     32
#define IMAGE_ADDR_MAX_LEN       20
#define CMD_ARG_MAX_LEN          192
struct octeon_eeprom_load_and_boot_info_v1 {
    octeon_eeprom_header_t header;
    uint8_t boot_command[BOOT_COMMAND_MAX_LEN]; /* Boot Command */
    uint8_t image_addr[IMAGE_ADDR_MAX_LEN]; /* Image Address */
    uint8_t cmd_arg[CMD_ARG_MAX_LEN]; /* Command Arg */
};
#define OCTEON_EEPROM_LOAD_AND_BOOT_INFO_VER    1
typedef struct octeon_eeprom_load_and_boot_info_v1 octeon_eeprom_load_and_boot_info_t;

/****** Script ID Active ******/
struct octeon_eeprom_script_id_active_v1 {
    octeon_eeprom_header_t header;
    uint8_t id; /* Script ID (0...n) */
};
#define OCTEON_EEPROM_SCRIPT_ID_ACTIVE_VER    1
typedef struct octeon_eeprom_script_id_active_v1 octeon_eeprom_script_id_active_t;

/****** Script ******/
#define SCRIPT_ID_MAX 3
#define SCRIPT_DATA_MAX_LEN (OCTEON_EEPROM_MAX_TUPLE_LENGTH - sizeof(octeon_eeprom_header_t))
struct octeon_eeprom_script_v1 {
    octeon_eeprom_header_t header;
    uint8_t script_data[SCRIPT_DATA_MAX_LEN]; /* Script Data */
};
#define OCTEON_EEPROM_SCRIPT_VER    1
typedef struct octeon_eeprom_script_v1 octeon_eeprom_script_t;

/****** UART ******/
#define UARTI_SETENV_BAUDRATE_CMD "setenv baudrate "
#define UARTI_SETENV_BAUDRATE2_CMD "setenv baudrate2 "
#define BAUDRATE_MAX_LEN 16
struct octeon_eeprom_uart_info_v1 {
    octeon_eeprom_header_t header;
    uint8_t baudrate[BAUDRATE_MAX_LEN]; /* Baudrate */
};
#define OCTEON_EEPROM_UART_INFO_VER    1
typedef struct octeon_eeprom_uart_info_v1 octeon_eeprom_uart_info_t;

/****** POST Information-Checksum Test ******/
#define CSUMTEST_8BIT_ONES_COMP  0
#define CSUMTEST_16BIT_ONES_COMP 1
#define CSUMTEST_32BIT_ONES_COMP 2
#define CSUMTEST_64BIT_ONES_COMP 3

#define CSUMTEST_FAILURE_THEN_CONT 0
#define CSUMTEST_FAILURE_THEN_HANG 1

#define CSUMTEST_PD_FREQ 0x0000FFFF

#define CSUMTEST_MAX 3
struct octeon_eeprom_csumtest_info_v1 {
    octeon_eeprom_header_t header;
    uint32_t start; /* Start */
    uint32_t end; /* End */
    uint32_t csum_loc; /* Checksum Location */
    uint8_t algorithm; /* Algorithm */
    uint8_t failure_action; /* Failure Action */
};
#define OCTEON_EEPROM_CSUMTEST_INFO_VER    1
typedef struct octeon_eeprom_csumtest_info_v1 octeon_eeprom_csumtest_info_t;

/****** POST Information-Memory Test ******/
#define MEMTEST_MOUT  128
#define MEMTEST_8BIT  0
#define MEMTEST_16BIT 1
#define MEMTEST_32BIT 2
#define MEMTEST_64BIT 3

#define MEMTEST_FAILURE_THEN_CONT 0
#define MEMTEST_FAILURE_THEN_HANG 1

#define MEMTEST_PD_FREQ (64 * 1024 * 1024)

#define MEMTEST_MAX 3
struct octeon_eeprom_memtest_info_v1 {
    octeon_eeprom_header_t header;
    uint64_t start; /* Start */
    uint64_t end; /* End */
    uint64_t pattern1; /* Pattern to use */
    uint64_t pattern2; /* Pattern to use */
    uint32_t step; /* Testing Step */
    uint8_t algorithm; /* Algorithm */
    uint8_t failure_action; /* Failure Action */
    uint8_t verbose; /* Verbose */
};
#define OCTEON_EEPROM_MEMTEST_INFO_VER    1
typedef struct octeon_eeprom_memtest_info_v1 octeon_eeprom_memtest_info_t;

#define MEMPOST_START         0x20000000
#if defined(CONFIG_OCTEON_AT5810)
/*4 GB */
#define MEMPOST_END           0xFFFFFFF8
#else
/* default to 1GB */
#define MEMPOST_END           0x40000000
#endif/*CONFIG_OCTEON_AT5810*/
#define MEMPOST_PATTERN1      0x5555555555555555ull
#define MEMPOST_PATTERN2      0xAAAAAAAAAAAAAAAAull
#define MEMPOST_STEP_SHORT    0x200000
#define MEMPOST_STEP_LONG     0x40000
#define MEMPOST_FAIL_HANG     -1
#define MEMPOST_FAIL_CONTINUE 0
#define MEMPOST_8BIT          0
#define MEMPOST_16BIT         1
#define MEMPOST_32BIT         2
#define MEMPOST_64BIT         3

#if defined(CONFIG_OCTEON_TNPA5854)
#define MEMTEST_START          0x0000000001000000ull
#else
#define MEMTEST_START         0x20000000
#endif /* CONFIG_OCTEON_TNPA5854 */

#define MEMTEST_END           0xFFFFFFF8
#define MEMTEST_ALGORITHM     3
#define MEMTEST_PATTERN1      0x5555555555555555ull
#define MEMTEST_PATTERN2      0xAAAAAAAAAAAAAAAAull
#define MEMTEST_STEP          0x80000


/****** POST Information-PHY Test ******/
#define PHY_DEFAULT_VAL 0x1140

#define PHYTEST_FAILURE_THEN_CONT 0
#define PHYTEST_FAILURE_THEN_HANG 1
struct octeon_eeprom_phytest_info_v1 {
    octeon_eeprom_header_t header;
    uint8_t algorithm; /* Algorithm */
    uint16_t dev_sel_map; /* Device Selection MAP */
    uint8_t failure_action; /* Failure Action */
};
#define OCTEON_EEPROM_PHYTEST_INFO_VER    1
typedef struct octeon_eeprom_phytest_info_v1 octeon_eeprom_phytest_info_t;

/****** POST Information-PMEM Test ******/
struct octeon_eeprom_pmemtest_info_v1 {
    octeon_eeprom_header_t header;
    uint8_t algorithm; /* Algorithm */
    uint8_t failure_action; /* Failure Action */
    uint8_t verbose; /* Verbose */
};

#define OCTEON_EEPROM_PMEMTEST_INFO_MAJOR_VER   1
#define OCTEON_EEPROM_PMEMTEST_INFO_MINOR_VER   0
typedef struct octeon_eeprom_pmemtest_info_v1 octeon_eeprom_pmemtest_info_t;


/****** POST RLDRAM Information Test ******/
struct octeon_eeprom_rldramtest_info {
    octeon_eeprom_header_t header;
    uint32_t addr;
    uint32_t size;
	int replType;
	int display;
};

#define OCTEON_EEPROM_RLDRAMTEST_INFO_MAJOR_VER   1
#define OCTEON_EEPROM_RLDRAMTEST_INFO_MINOR_VER   0
typedef struct octeon_eeprom_rldramtest_info octeon_eeprom_rldramtest_info_t;

/****** UBOOT Information (Version Number, Active and Partitioning) ******/
#define OCTEON_EEPROM_UBOOT_VERSION_NUM_SIZE 32

#define UBOOT_IS_INACTIVE  0
#define UBOOT_IS_ACTIVE    1

#define UBOOT_PARTITION    0
#define ENV_PARTITION      1
#define NFI_PARTITION      2

struct octeon_eeprom_uboot_info_v2 {
    octeon_eeprom_header_t header;
    uint8_t version_num[OCTEON_EEPROM_UBOOT_VERSION_NUM_SIZE]; /* Version Number */
    uint32_t active; /* currently active U-Boot indicator */
    uint32_t uboot_partition_type;
    uint32_t uboot_partition_offset;
    uint32_t uboot_partition_length;
    uint32_t env_partition_type;
    uint32_t env_partition_offset;
    uint32_t env_partition_length;
    uint32_t nfi_partition_type;
    uint32_t nfi_partition_offset;
    uint32_t nfi_partition_length;
};
typedef struct octeon_eeprom_uboot_info_v2 octeon_eeprom_uboot_info_t;

typedef struct octeon_eeprom_mac_addr_v1 octeon_eeprom_rtm_mac_addr_t;

#define TFTP_INFINITE_RETRY_THRESH 1024
#endif /* CONFIG_OCTEON_TNPA3804 || CONFIG_OCTEON_AT5810 || CONFIG_OCTEON_TNPA5804 */

/********************************************************************/
/* Specifies the voltage for Octeon (New for 6XXX)
*/
struct octeon_eeprom_voltage_desc_v1 {
    octeon_eeprom_header_t header;
    uint16_t octeon_core_voltage_mv;        /* Octeon core voltage in millivolts */
};
#define OCTEON_EEPROM_VOLTAGE_MAJOR_VER    1
#define OCTEON_EEPROM_VOLTAGE_MINOR_VER    0
typedef struct octeon_eeprom_voltage_desc_v1 octeon_eeprom_voltage_desc_t;
/********************************************************************/


/********************************************************************/
/* Specifies the multipliers for Octeon. (New for 6XXX)
*/
struct octeon_eeprom_multiplier_desc_v1 {
    octeon_eeprom_header_t header;
    uint16_t octeon_core_mult;        /* Octeon core multiplier */
    uint16_t octeon_io_mult;          /* Octeon core multiplier */
};
#define OCTEON_EEPROM_MULTIPLIER_MAJOR_VER    1
#define OCTEON_EEPROM_MULTIPLIER_MINOR_VER    0
typedef struct octeon_eeprom_multiplier_desc_v1 octeon_eeprom_multiplier_desc_t;
/********************************************************************/

#endif /* __OCTEON_EEPROM_TYPES_H__ */
