#ifndef __OCTEON_TNPA5651X_SHARED_H__
#define __OCTEON_TNPA5651X_SHARED_H__

/*
** CN56xx Registered configuration
*/
#define OCTEON_CN56XX_TNPA5651X_DDR_BOARD_DELAY	4000
#define OCTEON_CN56XX_TNPA5651X_LMC_DELAY_CLK		0
#define OCTEON_CN56XX_TNPA5651X_LMC_DELAY_CMD		0
#define OCTEON_CN56XX_TNPA5651X_LMC_DELAY_DQ		0

/*
** CN56xx Unbuffered configuration
*/
#define OCTEON_CN56XX_TNPA5651X_UNB_DDR_BOARD_DELAY	2000
#define OCTEON_CN56XX_TNPA5651X_UNB_LMC_DELAY_CLK		0x4 
#define OCTEON_CN56XX_TNPA5651X_UNB_LMC_DELAY_CMD  	0
#define OCTEON_CN56XX_TNPA5651X_UNB_LMC_DELAY_DQ		0x7 

#define OCTEON_TNPA5651X_1GB_667_DDR2_SPD_DATA      \
0x80,0x07,0x08,0x0e,0x0a,0x00,0x48,0x00,0x05,0x30,0x45,0x02,0x82,0x08,0x08,0x00, \
0x0c,0x08,0x38,0x00,0x00,0x00,0x03,0x3d,0x45,0x50,0x45,0x3c,0x1e,0x3c,0x28,0x01, \
0x20,0x27,0x10,0x17,0x3c,0x1e,0x1e,0x00,0x00,0x37,0x7f,0x80,0x18,0x22,0x00,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xb1, \
0x7f,0x61,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00

#define OCTEON_TNPA5651X_DRAM_SOCKET_CONFIGURATION0 \
    {{0x00, 0x00}, {tnpa5651x_spd_values, NULL}},{{0x00, 0x0}, {NULL, NULL}}

#define OCTEON_TNPA5651X_DRAM_SOCKET_CONFIGURATION1 \
    {{0x00, 0x00}, {tnpa5651x_spd_values, NULL}},{{0x00, 0x0}, {NULL, NULL}}

#define OCTEON_TNPA5651X_BOARD_EEPROM_TWSI_ADDR 0x52

#define TNPA56XX_DRAM_ODT_1RANK_CONFIGURATION \
    /* DIMMS   RODT_ENA  WODT_CTL0     WODT_CTL1   QS_DIC RODT_CTL DIC */ \
    /* =====   ======== ============ ============= ====== ======== === */ \
    /*   1 */ {   2,     0x00000001,   {.u64=0x00000000},    3,   0x0000,  1  },  \
    /*   2 */ {   2,     0x00000001,   {.u64=0x00000000},    3,   0x0000,  1  },  \
    /*   3 */ {   2,     0x00000001,   {.u64=0x00000400},    3,   0x0000,  1  },  \
    /*   4 */ {   2,     0x00000001,   {.u64=0x04000400},    3,   0x0000,  1  }

/* Note: CN56XX RODT_ENA 0 = disabled, 1 = Weak Read ODT, 2 = Strong Read ODT */
#define TNPA56XX_DRAM_ODT_2RANK_CONFIGURATION \
    /* DIMMS   RODT_ENA  WODT_CTL0     WODT_CTL1   QS_DIC RODT_CTL DIC */ \
    /* =====   ======== ============ ============= ====== ======== === */ \
    /*   1 */ {   2,     0x00000001,   {.u64=0x00000000},    3,   0x0000,  1  },  \
    /*   2 */ {   2,     0x00000001,   {.u64=0x00000000},    3,   0x0000,  1  },  \
    /*   3 */ {   2,     0x00000001,   {.u64=0x00000404},    3,   0x0000,  1  },  \
    /*   4 */ {   2,     0x00000001,   {.u64=0x04040404},    3,   0x0000,  1  }




/* Construct a static initializer for the ddr_configuration_t variable that holds
** (almost) all of the information required for DDR initialization.
*/
#define OCTEON_TNPA5651X_DDR_CONFIGURATION   \
/* Interface 0 */   \
{   \
    .dimm_config_table = {OCTEON_TNPA5651X_DRAM_SOCKET_CONFIGURATION0, DIMM_CONFIG_TERMINATOR},   \
    .unbuffered = {   \
        .ddr_board_delay = OCTEON_CN56XX_TNPA5651X_UNB_DDR_BOARD_DELAY,   \
        .lmc_delay_clk = OCTEON_CN56XX_TNPA5651X_UNB_LMC_DELAY_CLK,   \
        .lmc_delay_cmd = OCTEON_CN56XX_TNPA5651X_UNB_LMC_DELAY_CMD,   \
        .lmc_delay_dq = OCTEON_CN56XX_TNPA5651X_UNB_LMC_DELAY_DQ,   \
        },    \
    .registered = {   \
        .ddr_board_delay = OCTEON_CN56XX_TNPA5651X_DDR_BOARD_DELAY,   \
        .lmc_delay_clk = OCTEON_CN56XX_TNPA5651X_LMC_DELAY_CLK,   \
        .lmc_delay_cmd = OCTEON_CN56XX_TNPA5651X_LMC_DELAY_CMD,   \
        .lmc_delay_dq = OCTEON_CN56XX_TNPA5651X_LMC_DELAY_DQ,   \
        },   \
    .odt_1rank_config = {   \
        TNPA56XX_DRAM_ODT_1RANK_CONFIGURATION, \
        },   \
    .odt_2rank_config = {   \
        TNPA56XX_DRAM_ODT_2RANK_CONFIGURATION, \
        },   \
},   \
/* Interface 1 */   \
{   \
    .dimm_config_table = {OCTEON_TNPA5651X_DRAM_SOCKET_CONFIGURATION1, DIMM_CONFIG_TERMINATOR},   \
    .unbuffered = {   \
        .ddr_board_delay = OCTEON_CN56XX_TNPA5651X_UNB_DDR_BOARD_DELAY,   \
        .lmc_delay_clk = OCTEON_CN56XX_TNPA5651X_UNB_LMC_DELAY_CLK,   \
        .lmc_delay_cmd = OCTEON_CN56XX_TNPA5651X_UNB_LMC_DELAY_CMD,   \
        .lmc_delay_dq = OCTEON_CN56XX_TNPA5651X_UNB_LMC_DELAY_DQ,   \
        },    \
    .registered = {   \
        .ddr_board_delay = OCTEON_CN56XX_TNPA5651X_DDR_BOARD_DELAY,   \
        .lmc_delay_clk = OCTEON_CN56XX_TNPA5651X_LMC_DELAY_CLK,   \
        .lmc_delay_cmd = OCTEON_CN56XX_TNPA5651X_LMC_DELAY_CMD,   \
        .lmc_delay_dq = OCTEON_CN56XX_TNPA5651X_LMC_DELAY_DQ,   \
        },   \
    .odt_1rank_config = {   \
        TNPA56XX_DRAM_ODT_1RANK_CONFIGURATION, \
        },   \
    .odt_2rank_config = {   \
        TNPA56XX_DRAM_ODT_2RANK_CONFIGURATION, \
        },   \
}   \

#endif   /* __OCTEON_TNPA5651X_SHARED_H__ */
