/**     ll_npa_5651x_bist.h
 **
 **   This file contains all the definitions used by the low level
 ** BIST/POST code for the NPA-5651x AMC platform.
 **
 ** Author: Ted Schmitz
 **
 ** Created: June 29, 2009
 **
 **/

#define RESTART_VECTOR 0xFFFFFFFFBFC00000   /* abs adrs of restart vector */
#define BOOTPROM_CSUM_ADRS 0xFFF800F8       /* loc of csum & length in PROM */
#define BOOTPROM_CSUM_LENGTH_ADRS 0xFFF800FC /* loc of the number of bytes 
                                                included in the csum calc */
#define BOOTPROM_CSUM_LENGTH_OFFSET 0x000000FC /* offset of check sum length 
                                                  field from beg of csum 
                                                  calculation */
#define SEEPROM_SIZE 0x10000             /* length, in bytes, of SEEPROM on this
                                             board */

/**   The following symbols define the variables used in scratch RAM (define by
 ** setting up the "CvmMemCtl" coprocessor 0 register) space before
 ** SDRAM is tested and enabled.
 **
 **   These symbols start at the hard-coded location defined by the register 
 ** specified above which is: 0xFFFFFFFFFFFF8000.   This address is set up in
 ** the "start.S" module just after label "core_0_cont1:".
 **
 ** NOTE: Unless otherwise specified, all variables are 4 bytes long and start on
 **       a 4-byte boundary.
 **/
#define BEG_SCRATCH_VARS 0xFFFFFFFFFFFF8000ull     /* beg of vars scratch ram */
#define DCACHE_NEXT_WHEEL_POS (BEG_SCRATCH_VARS+0) /* position of next spinning
                                                   wheel char displayed to the
                                                   screen */
#define CUR_TEST_MODES (DCACHE_NEXT_WHEEL_POS+4) /* temp storage for current 
                                                    test modes */
#define RET_SDRAM_LENGTH (CUR_TEST_MODES+4) /* length of SDRAM calculated and
                                               returned by Uboot function
                                               "spd_sdram()". */
#define LOCAL_DIAG_DATA     (RET_SDRAM_LENGTH+4) /* (64 bytes) Start of copy of 
                                                    diag data from SEEPROM */
/* End SDRAM Data cache variables */

/**    The following definition forces the BIST code to include the 
 ** "Auto Disable" option of the "Test Modes" BIST command.  Not all platforms
 ** use this feature.
 **
 ** Defining the symbol below includes the "Auto Disable" option in the code.
 **/
//#define INCL_AUTO_DISABLE_TM

#define     DATA_NOT_READ       0x00                /* Diag data not read yet */
#define     DATA_READ_OKAY      0x01                /* Diag data read okay */
#define     DATA_READ_ERROR     0xFF                /* Error reading diag data */

/**   The "DESAVE" register is used to determine if this is a power up or warm
 ** reset.  On power up, the "DESAVE" register contains garbage.  Once BIST has
 ** started it sets the "DESAVE" to the value of this symbol.  The "DESAVE" 
 ** register retains its contents on a warm reset but not on a power up.
 **/
#define PU_FLAG_WARM_RESET_VAL 0x1234567887654321ull

/**  This section defines all the symbols involved with sending data to/from
 ** the H8 over the FPGA message FIFO's.
 **/
#define BIST_MB_TYPE            0x10    /* mailbox message type indicating a
                                           BIST message */
#define FPGA_MB_MAX_BYTES        512     /* max bytes in FPGA maibox */
#define BIST_MSG_HDR_LEN        0x06  /* length of TX bist msg header (in bytes) */
#define BIST_RX_MSG_HDR_LEN     0x08  /* length of RX bist msg header (in bytes) */

#define BIST_MB_MSG_VER         0x00  /* original BIST message format version */
#define MAX_WAIT_FOR_H8_RESP  1000  /* max milliseconds for response from H8 */

#define FPGA_INT_STAT_RX_MB_NOT_EMPTY 0x01 /* RX mailbox NOT empty bit */
#define FPGA_INT_STAT_RX_MB_EMPTY 0x02 /* RX mailbox empty bit */
#define FPGA_RX_DB_REG_1_USR      0x40 /* rx db 1, user bit */
#define FPGA_FLUSH_RX_MSG_VAL     0x6B /* value to flush rx msg from H8 */

/**     - - - FORMAT FOR MESSAGES TRANSMITTED TO THE H8 - - -
 **   The following symbols define the format of the BIST messages sent to
 ** the H8 through the FPGA mailboxes.
 **
 **   All these symbols are the offsets of the data in the messsage as 
 ** described below:
 ** Offset Size Description
 ** ------ ----- -------------------------------------------------------------
 **  0x00   01   Message type.  This is a value the H8 will recognize as 
 **              a BIST message from the master Octeon BIST processor.  This
 **              valu is defined in "BIST_MB_TYPE".
 **  0x01   01   BIST Message format version.  This value will start at 0x00
 **              and get incremented every time the format of the BIST message
 **              is changed in a way that will effect how the H8 has to 
 **              interpret the message.  For instance if a field is added,
 **              deleted, or modified.
 **  0x02   02   16-bit BIST Command to H8.
 **  0x04   02   16-bit message length.  This value represents the total number
 **              of bytes in the message including the "message type" field all
 **              the way through, and including, the last byte of the payload.
 **  0x06 varies Beginning of data payload.  This area contains sub-commands
 **              and/or any associated data.
 **
 **/
#define BIST_MB_MSG_TYPE       0x00      /* message type in 1st byte */
#define BIST_MB_VER (BIST_MB_MSG_TYPE+1) /* message format version (0x00) */
#define BIST_MB_CMD (BIST_MB_VER+1)      /* 2-byte command to H8 */
#define BIST_MB_MSG_LEN (BIST_MB_CMD+2)  /* 2-byte message length */
#define BIST_MB_PAYLOAD (BIST_MB_MSG_LEN+2) /* beg of data payload */

/* commands sent in BIST messages */
#define BIST_CMD_NOP           0x0000 /* NOP - test H8 is responding */
#define BIST_CMD_SEEPROM_WRITE 0x0001 /* write data to comm SEEPROM */
 /* payload data offsets for "BIST_CMD_SEEPROM_WRITE" cmd */
 #define BC_SW_OFFSET 0x00            /* 2-byt offset of data to be written */
 #define BC_SW_LENGTH 0x02            /* 2-byt number of bytes to be written */
 #define BC_SW_DATA   0x04            /* beg of data to be written to SEEPROM */
#define BIST_CMD_ERR_LOGIC_TEST 0x0002 /* Force failure to test error logic */
#define BIST_CMD_FPGA_RAM_TEST 0x0003 /* Test FPAG dual-port RAM */
#define BIST_CMD_RST_OCTEON     0x0004 /* reset the octeon processor */
#define BIST_CMD_MUX_DIAG       0x0005 /* re-initialize the muxes for diagnostics */
 /* payload data offsets for "BIST_CMD_MUX_DIAG" cmd */
 #define BC_MD_SEL 0x00            /* 1-byte mux mode selection */
 #define BC_MD_LEN 0x01            /* cmd data length (1-byte) */
  /**  The following symbols define all the valid selection modes that can be
   ** sent in the payload of the "BIST_CMD_MUX_DIAG" command above:
   ** Value  Description
   ** -----  --------------------------------------------------------------
   ** 0x00   Configure mux according to current switch settings (normal mode)
   ** 0x01   Connect QLM1 & QLM3 to AMC connector.
   ** 0x02   Connect QLM1 & QLM3 to Front panel PHYs.
   ** 0x04   Loop data coming in from the AMC connector back to the AMC 
   **        connector.
   ** 0x08   Loop data from QLM1 & QLM3 back to QLM1 & QLM3 respectively.
   **/
  /* NOTE:  The following symbols were copied from module "app.h" in the H8 
     codebase. */
  #define DIAG_BOARD_CONFIG_PORTS_ENABLE_MASK 0x0F
  #define DIAG_BOARD_CONFIG_PORTS_LOOPQLMS    0x08
  #define DIAG_BOARD_CONFIG_PORTS_LOOPAMCS    0x04
  #define DIAG_BOARD_CONFIG_PORTS_FORCEFRONT  0x02
  #define DIAG_BOARD_CONFIG_PORTS_FORCEAMCS   0x01
  #define DIAG_BOARD_CONFIG_PORTS_INACTIVE    0x00
#define BIST_CMD_SENSOR_DIAG    0x0006 /* get sensor reading & limits */
#define BC_SR_PL_LEN_XMIT 0x01         /* length of payload data xmitted */
#define BC_SR_PL_LEN_RET 0x03          /* length of payload data returned */
 /* payload data offsets for "BIST_CMD_SENSOR_DIAG" cmd */
 #define BC_SR_SENNUM 0x00         /* 1-byte sensor number - xmitted */
 #define BC_SR_RREAD  0x00         /* 1-byte raw reading - received */
 #define BC_SR_LOWTH  0x01         /* 1-byte low threshold - received */
 #define BC_SR_HIGHTH 0x02         /* 1-byte high threshold - received */

/**     - - - FORMAT FOR MESSAGES RECEIVED FROM THE H8 - - -
 **   The following symbols define the format of the BIST messages received from
 ** the H8 through the FPGA mailboxes.
 **
 **   All these symbols are the offsets of the data in the messsage as 
 ** described below:
 ** Offset Size Description
 ** ------ ----- -------------------------------------------------------------
 **  0x00   01   Message type.  This is a value the Octeon will recognize as 
 **              a BIST message from the H8 processor.  This value is defined
 **              in "BIST_MB_TYPE".
 **  0x01   01   BIST Message format version.  This value will start at 0x00
 **              and get incremented every time the format of the BIST message
 **              is changed in a way that will effect how the Octeon has to 
 **              interpret the message.  For instance if a field is added,
 **              deleted, or modified.
 **  0x02   02   16-bit BIST Command received by the H8.  This is a reference
 **              to the command for which this response message was generated.
 **  0x04   02   16-bit message length.  This value represents the total number
 **              of bytes in the message including the "message type" field all
 **              the way through, and including, the last byte of the payload.
 **  0x06   02   Response Type byte.  This field contains bits representing the 
 **              type of response received from the H8 as shown below:
 **              Bit  Response Type
 **              ---- -------------------------------------------------------
 **               00  This is a normal completion response.  The last BIST 
 **                   command received from the Octeon has completed with no
 **                   errors detected.
 **               01  Command completed with errors detected.  Payload contains
 **                   32-bit error code.  Type of error code determines if any 
 **                   additional error data immediately follows the error code.
 **               02  Estimated time to complete command, in milliseconds, is 
 **                   available in the payload.  Milliseconds is a 32-bit 
 **                   field.
 **              15-03 Reserved
 **  0x08 varies Beginning of data payload.  This area contains sub-requests
 **              from the H8 and/or any associated data.
 **
 **/
#define BIST_RX_MB_MSG_TYPE       0x00      /* message type in 1st byte */
#define BIST_RX_MB_VER (BIST_RX_MB_MSG_TYPE+1) /* message format version (0x00) */
#define BIST_RX_MB_CMD (BIST_RX_MB_VER+1)      /* 2-byte command rcvd by H8 */
#define BIST_RX_MB_MSG_LEN (BIST_RX_MB_CMD+2)  /* 2-byte message length */
#define BIST_RX_MB_RES_TYPE (BIST_RX_MB_MSG_LEN+2) /* response type */
#define BIST_RX_MB_PAYLOAD (BIST_RX_MB_RES_TYPE+2) /* beg of data payload */

/* following symbols define bits in "response type" field */
#define RES_TYPE_CMD_COMP_NO_ERS 0x0001    /* cmd completed w/no errors */
#define RES_TYPE_CMD_COMP_W_ERS  0x0002    /* cmd completed with errors */
#define RES_TYPE_CMD_EST_TIME    0x0004    /* estimate time to complete cmd */


/* end FPGA Octeon/H8 FIFO messaging defines */
#define FPGA_BD_RST_OCT_RST_BIT 0x01  /* reset octeon bit in fpga resets reg */

/**   The following symbols define all the bits position used to select
 ** each low-level POST test.
 *                                         Test No / Test name */
#define LL_ADRS_DECODE_TEST      0x00000001 /*1 board decode test */
#define LL_DUART_TEST            0x00000002 /*2 DUART */
#define LL_BOOT_PROM_CRC_TEST    0x00000004 /*3 boot prom crc verification */
#define LL_SDRAM_DATA_LINES_TEST 0x00000008 /*4 SDRAM data lines */
#define LL_SDRAM_ADRS_LINES_TEST 0x00000010 /*5 SDRAM adrs lines */
#define LL_SDRAM_CELLS_TEST      0x00000020 /*6 SDRAM cells */
#define LL_SDRAM_ECC_TEST        0x00000040 /*7 SDRAM ecc cells */
#define LL_PH1_ERR_LOGIC_TEST    0x00000080 /*8 Phase 1 error logic test */
#define LL_SDRAM_BOUNDARY_TEST   0x00000100 /*9 SDRAM boundary access */
#define LL_IRQ_TEST              0x00000200 /*10 lo-lev IRQ test */
#define LL_FPGA_RAM_TEST         0x00000400 /*11 FPGA RAM test (Octeon Side) */
#define LL_I2C_BUS_TEST          0x00000800 /*12 I2C bus device ack check */
#define LL_I2C_MON_TEST          0x00001000 /*13 I2C sys monitor */
#define LL_PH2_ERR_LOGIC_TEST    0x00002000 /*14 Phase 2 error logic test */
#define LL_I2C_RTC_TEST          0x00004000 /*15 I2C Real time Clock */
#define LL_INTER_PROC_TEST       0x00008000 /*16 Interproc communications test*/
#define LL_I2C_TEMP_TEST         0x00010000 /*17 I2C Temp sensor */
#define LL_PCI_BUS_TEST          0x00020000 /*18 PCI device access */
#define LL_EXT_IRQ_TEST          0x00040000 /*19 External IRQ test */
#define LL_ETH_TEST              0x00080000 /*20 Ethernet controller */
#define LL_DMA_TEST              0x00100000 /*21 DMA functional */
#define LL_MSG_UNIT_TEST         0x00200000 /*22 MSG unit */
#define LL_WATCH_PT_TEST         0x00400000 /*23 Watch point facility */
#define LL_LED_TEST              0x00800000 /*24 LEDs */
#define LL_H8_SENSORS            0x01000000 /*25 H8 sensor limits */
#define LL_H8_FPGA_RAM_TEST      0x02000000 /*26 FPGA RAM test (H8 side) */
#define LL_PM_DATA_LINES_TEST    0x08000000 /*28 PM RAM data lines */
#define LL_PM_ADRS_LINES_TEST    0x10000000 /*29 PM RAM address lines */
#define LL_PM_CELLS_TEST         0x20000000 /*30 PM RAM cells */

#define MAX_LL_TESTS 32                 /* max num of lo-lev tests possible */

#if 0 /* eventually all these will be the default tests */
/* define all the default tests to be run at power up */
#define DEFAULT_LL_TESTS ( \
                          LL_ADRS_DECODE_TEST | \
                          LL_DUART_TEST | \
                          LL_BOOT_PROM_CRC_TEST | \
                          LL_SDRAM_DATA_LINES_TEST | \
                          LL_SDRAM_ADRS_LINES_TEST | \
                          LL_SDRAM_CELLS_TEST | \
                          LL_SDRAM_ECC_TEST | \
                          LL_SDRAM_BOUNDARY_TEST | \
                          LL_IRQ_TEST | \
                          LL_BIOS_PROM_CRC_TEST | \
                          LL_I2C_BUS_TEST | \
                          LL_ETH_TEST | \
                          LL_I2C_SEEPROM_CRC_TEST | \
                          LL_I2C_RTC_TEST | \
                          LL_I2C_TEMP_TEST \
                         )
#else  /* but for now these are the default tests on new units */
#define DEFAULT_LL_TESTS ( \
                          LL_SDRAM_DATA_LINES_TEST | \
                          LL_SDRAM_ADRS_LINES_TEST | \
                          LL_SDRAM_CELLS_TEST | \
                          LL_FPGA_RAM_TEST | \
                          LL_H8_SENSORS | \
                          LL_H8_FPGA_RAM_TEST | \
                          LL_PM_DATA_LINES_TEST | \
                          LL_PM_ADRS_LINES_TEST | \
                          LL_I2C_BUS_TEST | \
                          LL_ETH_TEST | \
                          LL_PM_CELLS_TEST \
                         )
#endif

/**    Mask represents all tests that require the ECC to be initialize 
 ** before test is executed.
 **/
#define LL_ECC_TESTS ( LL_SDRAM_ADRS_LINES_TEST | \
                       LL_SDRAM_CELLS_TEST | \
                       LL_SDRAM_ECC_TEST | \
                       LL_SDRAM_BOUNDARY_TEST \
                     )

/*  end of test bits definitions */

/**   The following symbols represent the tick counts in the
 ** lower time base register represeting the time described.
 **/
//#define CTF1MS 800000                /* 800 MHZ clock */
#define CTF1MS 600000                /* tnpa_56x4 - 600 MHZ clock */

#define MS_1   (CTF1MS * 1)       /* 1 millisecond */
#define MS_2   (CTF1MS * 2)       /* 2 millisecond */
#define MS_5   (CTF1MS * 5)       /* 5 milliseconds */
#define MS_10  (CTF1MS * 10)      /* 10 milliseconds */
#define MS_15  (CTF1MS * 15)      /* 15 milliseconds */
#define MS_25  (CTF1MS * 25)      /* 25 milliseconds */
#define MS_50  (CTF1MS * 50)      /* 50 milliseconds */
#define MS_75  (CTF1MS * 75)      /* 75 milliseconds */
#define MS_100 (CTF1MS * 100)     /* 100 milliseconds */
#define MS_200 (CTF1MS * 200)     /* 200 milliseconds */
#define MS_500 (CTF1MS * 500)     /* 500 milliseconds */
#define MS_800 (CTF1MS * 800)     /* 800 milliseconds */
#define MS_900 (CTF1MS * 900)     /* 900 milliseconds */
#define SEC_1  (CTF1MS * 1000)    /* 1 second */
#define SEC_1_1  (CTF1MS * 1100)  /* 1.1 seconds */
#define SEC_1_5 (CTF1MS * 1500)   /* 1.5 seconds */
#define SECS_2  (CTF1MS * 2000)   /* 2 seconds */
#define SECS_3  (CTF1MS * 3000)   /* 3 seconds */
#define SECS_4  (CTF1MS * 4000)   /* 4 seconds */
#define SECS_5 (CTF1MS * 5000)    /* 5 seconds */

/* some larger values need to be defined as unsigned for some uses */
#define SECS_3U  ((unsigned long) CTF1MS * 3000)   /* 3 seconds */
#define SECS_4U  ((unsigned long) CTF1MS * 4000)   /* 4 seconds */
#define SECS_5U  ((unsigned long) CTF1MS * 5000)   /* 5 seconds */

/* this is how to specify 64-bit constants */
#define FIVE_SECONDS 0x00000000ee6B2800ull

//#define TIME_TO_SPIN_WHEEL MS_50        /* lapsed time between spinning wheel */
#define TIME_TO_SPIN_WHEEL MS_100        /* lapsed time between spinning wheel */
#define MAX_TBL_COUNT 0xFFFF0000        /* count at which TBL should be clrd */

#define MAX_SEEPROM_READ_RETRIES 10     /* num of times to retry the SEEPROM
                                           read if a problem was detected
                                           during the read */

#define BOOT_PROM_ADRS_MASK 0x000FFFFF/* mask to isolate boot prom adrs lines */
#define LL_POST_END_BLINK_VAL 3         /* times to blink ll POST end seq */


#define SYS_LED_REG_ADRS     0x98000008 /* system LED's register */
#define CABLE_LED_REG_ADRS   0x98000009 /* cable link LED's register */
#define SYS_LED_REG *((volatile char *) (SYS_LED_REG_ADRS))
#define HB_LED               0x20       /* bit to turn on Heart Beat LED (1) */
#define FAULT_LED            0x08       /* bit to turn on Fault LED (2) */
#define POWER_LED            0x02       /* bit to turn on Power LED (4) */
#define GOOD_LED             0x01       /* bit to turn on Good LED (3) */
#define ALL_SYS_LEDS_MASK    0x2B       /* mask to isolate all sys LEDs */
#define ALL_LOCAL_LEDS_MASK  0xFF       /* mask to isolate all local LEDs */
#define CABLE_LEDS_MASK      0xC0       /* mask to isolate cable link LEDs */

#define TEMP_SENSOR_I2C_ADRS 0x4C       /* MAX6658MSA temp sensor i2c adrs */
#define SEEPROM_I2C_ADRS     0x50       /* AT24C512 SEEPROM i2c adrs */
#define SDRAM_SPD_WRITE_DEV 0xA0        /* 1st DIMM SPD data write address */
#define DIMM_SPD_MAX_BYTES 128          /* max bytes to read from SDRAM spd
                                           PROM */

/**   This section defines some of the FPGA registers and bits that are not
 ** defined elsewhere in the Octeon code base.
 **/
#define FPGA_BASE_ADRS     0x16000000   /* FPGA base address */
#define FPGA_DP_RAM (FPGA_BASE_ADRS+0x80) /* beg of dual-port ram in FPGA */

/* end FPGA extensions */

/**  The following symbols define some of the bits in some of the
 ** DDR configuration/status registers.
 **/
#define LMC_MEM_CFG0_ECC_ENA 0x02ull /* ECC enable bit */
#define LMC_MEM_CFG0_DED_ERR 0x1E000000ull /* ECC double bit err */
#define LMC_MEM_CFG0_SEC_ERR 0x01E00000ull /* ECC single bit err */

/* all ecc error bits */
#define LMC_MEM_CFG0_ECC_ERRS (LMC_MEM_CFG0_DED_ERR | \
                               LMC_MEM_CFG0_SEC_ERR)


/* expected failing adrs captured in "LMC_FADR" reg after forcing
   an ECC failure */
#define EXP_FAIL_ADRS_REG 0x0000000000000000ull
/* end of DDR definitions */

/* CUI Soft reset register address used to rest the Octeon */
#define CIU_SOFT_RST_REG 0x8001070000000740
 #define CIU_SOFT_RST_BIT 0x0000000000000001 /* SOFT RESET bit */

/**   The following symbols define all the values that can be used for the
 ** "err_msg_flag" in function "read_select_data_from_i2c_dev_timed()".
 **/
#define DISABLE_ERROR_MSGS 0            /* prevent error msgs from displaying */
#define ENABLE_ERROR_MSGS 1             /* allow error msgs to display */
/* end "err_msg_flag" parameter definitions */

/**   The following symbols define the various bit position in the
 ** simulated hardware options register.  Each bit represents a different
 ** piece of available hardware that the software can check to
 ** modify the flow of execution if needed.
 **
 **   Typically, if a change in the hardware effects two or more products
 ** a bit should be defined in this register for that hardware change.  It
 ** should be noted that there are other hardware differences like how many
 ** ports are available, etc.  Some of these differences do not effect
 ** the low-level diagnostics at this point so there are no bits to define
 ** those differences at this time.
 **
 ** More that one bit can be defined for any given platform.  This is
 ** currently a 32-bit field defined as follows:
 **
 ** Bit Description
 ** --- --------------------------------------------------------------------
 **/ 
#define DEFAULT_HW          0x00000000  /* default HW = Orig HW */

/* end of simulated hardware options register definitions */

/* the following symbols define the various FPGA versions */
#define FPGA_VER_TNPA_5644 0xC8    /* this version is a 5644 board */
#define FPGA_VER_TNPA_5654 0xC9    /* this version is a 5654 board */

#define MAX_SEEPROM_WRITE_BLOCK 32 /* max bytes that can be burned in one call
                                      to the H8 SEEPROM write function */

/* Define the following symbol to disable the 2nd BIST count down message.
 * This has become the defacto standard on all new code releases.
 */
#define DISABLE_2ND_COUNT_DOWN_MSG
#undef DISABLE_2ND_COUNT_DOWN_MSG

/* define the following symbol to force a boot PROM csum failure */
#if 0 
#define FORCE_CSUM_FAILURE 
#endif

/**  The following symbol defines a 32 bit value for the NPA-5644 platform
 **  which includes:
 **  bits 31-16 = default test mode (currently disable ll post)
 **  bits 15-8  = default error mode (currently goto-nf-on-error)
 **  bits 7-0   = zero
 **/
#if 1 /* normal defaults */
#define DEFAULT_LL_TEST_PARMS ((TM_DISABLE_POST << 16) | (GTNF_ON_ERROR << 8))
#else /* DEBUG - enable POST by default */
#define DEFAULT_LL_TEST_PARMS (0x03 << 8)
#endif

/* define the following symbol to force an unknown value to be stored
  in SEEPROM for the product id */
#if 0
#define FORCE_UNKNOWN_PROD_ID
#endif

/* define the following symbol to force a "product ID not available"
   status */
#if 0
#define FORCE_NO_PROD_ID
#endif

/**  Define the following symbols to force a power up condition on every
 ** reset.  Normally these would not be defined.
 **/
#if 0 /* normally disable these symbols */
#define FORCE_P1_POWER_UP_MODE /* force power up mode for phase one code */
#define FORCE_P2_POWER_UP_MODE /* force power up mode for phase two code */
//#define FORCE_DEV_ID           /* simulate a good TLV device id entry */
#define DEFAULT_DEV_ID PROD_TYPE_NPA_5644 /* set up default TLV device ID */
#if 0
#define FORCE_REWRITE_OF_DIAG_PARAMS /* force diag parameters to be re-written
                                        to SEEPROM on every reboot */
#endif
#endif /* end normally disabled symbols */



