/**   common_mem_test.h
 **
 **   This is the header file contains common definitions that support the 
 ** memory tests for all processors.
 **
 ** Created by Ted Schmitz, October 10, 2008
 **
 **/
#include "common_mem_test_defs.h"

extern uint64_t data_test_pats_64b[];
extern void diag_flush_cache(uint64_t * read_address);
extern void report_error(char * msp, uint64_t fail_adrs, uint64_t exp_data,
                         uint64_t bad_data_rec, int length);
extern void ll_write_tlb_entry(u64 index, u64 phy_adrs, u64 vadrs, 
                               u64 page_length, u64 attrib);
extern void ll_restore_tlb_entry_0(void);
extern void ll_flush_l2c(void);
extern void ll_restore_all_tlb_entrys(void);

#define END_OF_TABLE 0x1234567890123456ull  /* table termination value */
//#define PASS 1                               /* results of last operation passed */
//#define FAIL 1                               /* results of last operation failed */

#define RAM_BOUNDARY_2GB 0x0000000080000000ull /* beg adrs for 2GB boundary */
#define RAM_TLB_LEN      0x0000000010000000ull /* 256MB length region */

#define LEN_OF_DR0_DR1_REGIONS 0x20000000 /* length of DR0 & DR1 regions */

/* location where asm code relocates itself for executon */
//#define RAM_LOGIC_REL_ADRS 0x8000000080000000ull /* works for adrs lines test */
#define ASM_CODE_REL_ADRS_L2C 0x8000000080000000ull /* works for adrs lines test */
#define ASM_CODE_REL_ADRS_RAM 0x0000000000000000ull /* works for adrs lines test */
//#define RAM_LOGIC_REL_ADRS 0xFFFFFFFF80000000ull /* debug */
#define RAM_LOGIC_REL_LENGTH 0x0000000000000400ull /* len of rel code area */

/* base adrs to be used for data lines test. MUST be on 128-bit (16-byte) 
   boundary */
#define BEG_DATA_LINES_TEST_ADDR 0x0000000000000000ull
//#define BEG_DATA_LINES_TEST_ADDR 0x0000000080040000ull
//#define BEG_DATA_LINES_TEST_ADDR 0xFFFFFFFF80040000ull
//#define BEG_DATA_LINES_TEST_ADDR 0xFFFFFFFF80000000ull

/** beginning location for address lines test. 
 **
 **  NOTE:  The Uboot code seems toa acces the DDR RAM by setting bit 63
 **         every time it accesses DDR RAM.  Setting this bit does not
 **         seem to make any difference for the RAM tests.
 **/
//#define BEG_ADRS_LINES_TEST_ADDR_DR0 0x8000000000000000ull /* DDR 0 region */
#define BEG_ADRS_LINES_TEST_ADDR_DR0 0x0000000000000000ull /* DR0 region */
#define ADRS_LINES_TEST_LENGTH_DR0   0x0000000010000000ull /* DR0 len - 256MB */
#define BEG_ADRS_LINES_TEST_ADDR_DR1 0x0000000410000000ull /* DR1 region */
//#define BEG_ADRS_LINES_TEST_ADDR_DR1 0x0000000400000000ull /* DR1 region */
#define ADRS_LINES_TEST_LENGTH_DR1   0x0000000010000000ull /* DR1 - len 256MB */
#define BEG_ADRS_LINES_TEST_ADDR_DR2 0x0000000020000000ull /* DR2 region */
#define ADRS_LINES_TEST_LENGTH_DR2   0x0000000020000000ull /* DR2 - 512&upMB */

#define MEM_4KB_LENGTH 0x0000000000001000ull        /* 4K length */
#define MEM_1MB_LENGTH 0x0000000000100000ull        /* 1M byte length */
#define MEM_2MB_LENGTH 0x0000000000200000ull        /* 2M byte length */

/* address lines test fill value */
#define ADRS_LINES_TEST_FILL_VAL 0x0000000000000000ull
//#define ADRS_LINES_TEST_FILL_VAL 0x0102030405060708ull

/* DEBUG ONLY - end of RAM */
#define DEBUG_END_OF_RAM 0xFFFFFFFF8FFFFFFFull

/* beg adrs of read to flush all data caches */
//#define CACHE_FLUSH_ADR_DATA_LINES_TEST (uint64_t *) 0x0000000010000000ull
//#define CACHE_FLUSH_ADR_DATA_LINES_TEST (uint64_t *) 0xFFFFFFFF81000000ull /* yes */
#define CACHE_FLUSH_ADR_DATA_LINES_TEST (uint64_t *) 0x800000002000000ull

/* how much data to read to fully flush Dcache (at least 2MB) */
//#define CACHE_FLUSH_READ_LENGTH 0x0000000000400000ull /* 4MB */
#define CACHE_FLUSH_READ_LENGTH 0x0000000000200000ull /* 2MB */

/**    The following symbols represent the values used to test the 
 ** persistent memory 
 **/
#define BEG_ADRS_OF_PERS_MEM_BLK_1   0x0000000013000000ull /* 1st block of PM*/
#define LENGTH_PERS_MEM_BLK_1        0x0000000001000000ull /* 1st blk - 16MB */
#define BEG_ADRS_OF_PERS_MEM_BLK_2   0x0000000014000000ull /* 2nd block of PM*/
#define LENGTH_PERS_MEM_BLK_2        0x0000000001000000ull /* 2nd blk - 16MB */

/* end of persistent memory defines */

/* This following symbols define all the TLB related constants */
#define TLB_ENTRY_HI_REG_DEF 0xFFFFFFFF90000000ull /* default valu th0 reg */
#define TLB_ENTRY_HI_INC     0x0000000000002000ull /* th reg increment value */
#define MAX_TLB_INDEX 63           /* max num of TLBs that are available */

#define MASK_REG_4K    0x0000000000000000ull /* region is 4KB long */
#define MASK_REG_256MB 0x000000001FFFE000ull /* region is 256MB long */
#define MASK_REG_128MB 0x000000000FFFE000ull /* region is 128MB long */
#define TLB_GBL_BIT 0x01                 /* Global bit in EntyrLo/Hi TLB reg */
#define TLB_VALID_BIT 0x02               /* Valid bit in EntyrLo/Hi TLB reg */
#define TLB_DIRTY_BIT 0x04               /* Dirty bit in EntyrLo/Hi TLB reg */
#define TLB_DVG_BITS (TLB_GBL_BIT | TLB_VALID_BIT | TLB_DIRTY_BIT)
/* end TLB synbols */

/* macros to force write to complete */
#define sync() asm volatile("sync")
#define syncs() asm volatile("syncs")
#define syncw() asm volatile("syncw")
#define syncws() asm volatile("syncws")
#define invalidate_L1_Dcache() asm volatile("cache 9, 0($0)")
// CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable (actually old value or zero) until
// that byte is stored to (by this or another processor. Note that the value of each byte is not only
// unpredictable, but may also change again - up until the point when one of the cores stores to the
// byte.
#define CVMX_PREPARE_FOR_STORE(address, offset) asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address) )

