#ifndef __OCTEON_W56XX_SHARED_H__
#define __OCTEON_W56XX_SHARED_H__

/*
** CN56xx Registered configuration
*/
#define OCTEON_CN56XX_EBH5600_DDR_BOARD_DELAY	4000
#define OCTEON_CN56XX_EBH5600_LMC_DELAY_CLK		5
#define OCTEON_CN56XX_EBH5600_LMC_DELAY_CMD		0
#define OCTEON_CN56XX_EBH5600_LMC_DELAY_DQ		5

/*
** CN56xx Unbuffered configuration
*/
#define OCTEON_CN56XX_EBH5600_UNB_DDR_BOARD_DELAY	2000
#define OCTEON_CN56XX_EBH5600_UNB_LMC_DELAY_CLK		5 
#define OCTEON_CN56XX_EBH5600_UNB_LMC_DELAY_CMD  	0
#define OCTEON_CN56XX_EBH5600_UNB_LMC_DELAY_DQ		5 

#define OCTEON_W56XX_DRAM_SOCKET_CONFIGURATION0 \
    {{0x50, 0x0}, {NULL, NULL}}

#define OCTEON_W56XX_DRAM_SOCKET_CONFIGURATION1 \
    {{0x51, 0x0}, {NULL, NULL}}

#define OCTEON_W56XX_BOARD_EEPROM_TWSI_ADDR 0x52

/* Construct a static initializer for the ddr_configuration_t variable that holds
** (almost) all of the information required for DDR initialization.
*/
#define OCTEON_W56XX_DDR_CONFIGURATION   \
/* Interface 0 */   \
{   \
    .dimm_config_table = {OCTEON_W56XX_DRAM_SOCKET_CONFIGURATION0, DIMM_CONFIG_TERMINATOR},   \
    .unbuffered = {   \
        .ddr_board_delay = OCTEON_CN56XX_EBH5600_UNB_DDR_BOARD_DELAY,   \
        .lmc_delay_clk = OCTEON_CN56XX_EBH5600_UNB_LMC_DELAY_CLK,   \
        .lmc_delay_cmd = OCTEON_CN56XX_EBH5600_UNB_LMC_DELAY_CMD,   \
        .lmc_delay_dq = OCTEON_CN56XX_EBH5600_UNB_LMC_DELAY_DQ,   \
        },    \
    .registered = {   \
        .ddr_board_delay = OCTEON_CN56XX_EBH5600_DDR_BOARD_DELAY,   \
        .lmc_delay_clk = OCTEON_CN56XX_EBH5600_LMC_DELAY_CLK,   \
        .lmc_delay_cmd = OCTEON_CN56XX_EBH5600_LMC_DELAY_CMD,   \
        .lmc_delay_dq = OCTEON_CN56XX_EBH5600_LMC_DELAY_DQ,   \
        },   \
    .odt_1rank_config = {   \
        CN56XX_DRAM_ODT_1RANK_CONFIGURATION,   \
        },   \
    .odt_2rank_config = {   \
        CN56XX_DRAM_ODT_2RANK_CONFIGURATION,   \
        },   \
},   \
/* Interface 1 */   \
{   \
    .dimm_config_table = {OCTEON_W56XX_DRAM_SOCKET_CONFIGURATION1, DIMM_CONFIG_TERMINATOR},   \
    .unbuffered = {   \
        .ddr_board_delay = OCTEON_CN56XX_EBH5600_UNB_DDR_BOARD_DELAY,   \
        .lmc_delay_clk = OCTEON_CN56XX_EBH5600_UNB_LMC_DELAY_CLK,   \
        .lmc_delay_cmd = OCTEON_CN56XX_EBH5600_UNB_LMC_DELAY_CMD,   \
        .lmc_delay_dq = OCTEON_CN56XX_EBH5600_UNB_LMC_DELAY_DQ,   \
        },    \
    .registered = {   \
        .ddr_board_delay = OCTEON_CN56XX_EBH5600_DDR_BOARD_DELAY,   \
        .lmc_delay_clk = OCTEON_CN56XX_EBH5600_LMC_DELAY_CLK,   \
        .lmc_delay_cmd = OCTEON_CN56XX_EBH5600_LMC_DELAY_CMD,   \
        .lmc_delay_dq = OCTEON_CN56XX_EBH5600_LMC_DELAY_DQ,   \
        },   \
    .odt_1rank_config = {   \
        CN56XX_DRAM_ODT_1RANK_CONFIGURATION,   \
        },   \
    .odt_2rank_config = {   \
        CN56XX_DRAM_ODT_2RANK_CONFIGURATION,   \
        },   \
}   \

#endif   /* __OCTEON_W56XX_SHARED_H__ */
