/**     ll_bist.h
 **
 **   This file contains all the common definitions used by all the low level
 ** BIST/POST code.
 **
 ** Author: Ted Schmitz
 **
 ** Created: December 10, 2008
 **
 **
 **   Date   INTLS Comments
 ** -------- ----- --------------------------------------------
 ** 06-29-09  TMS  Added support for TNPA-5651x board.
 **
 **/

#ifndef __LL_BIST_H__
#define __LL_BIST_H__

/**
 ** Include the proper unique definitions for this compile here.
 **/

/* compile for NPA-56x4 AMC board */
#ifdef octeon_tnpa56x4
#include "diag_mon/errhand_defs.h" /* get some of the common err hand defs */
#include "ll_npa_56x4_bist.h"
#endif

/* compile for NPA-5651x AMC board */
#ifdef octeon_tnpa5651x
#include "diag_mon/errhand_defs.h" /* get some of the common err hand defs */
#include "ll_npa_5651x_bist.h"
#endif

/**
 **  The following symbols represent the offsets in the SEEPROM where the
 ** various BIST data is stored.
 **/
#define DIAG_AREA_LEN 64                  /* length of original diagostic 
                                             SEEPROM area in bytes */
#define DIAG_AREA_LEN_2 64                  /* length of 2nd diagostic 
                                             SEEPROM area in bytes */
#define DIAG_AREA_LEN_3 64                  /* length of 3rd diagostic 
                                             SEEPROM area in bytes */
#define DIAG_AREA_LEN_4 64                  /* length of 4th diagostic 
                                             SEEPROM area in bytes */
#define TOTAL_DIAG_AREA_LEN (DIAG_AREA_LEN + DIAG_AREA_LEN_2 + \
                             DIAG_AREA_LEN_3 + DIAG_AREA_LEN_4)

#define LL_NO_TEST_NUM  0x00000000       /* no test # avail for this failure */
/**
 ** NOTE: With the "Diag Data" area being copied into local
 **       memory, if any of these change, then you also
 **       need to update the in memory offsets as well. See
 **       ll_<platform>_bist.h and ll_post_<platform>.c
 **/
#ifdef STANDALONE
#define BEG_BIST_DATA_OS 0          /* start at index 0 for stand alone mode */
#else
#if 0 /* old way - only 64 bytes of data */
#define BEG_BIST_DATA_OS (SEEPROM_SIZE-DIAG_AREA_LEN)/* beg of BIST data in 
                                                        SEEPROM (64 bytes)*/
#else /* new way - put orig data area at beg of larger 256 byte area */
#define BEG_BIST_DATA_OS (SEEPROM_SIZE-TOTAL_DIAG_AREA_LEN)/* beg of BIST data in 
                                                        SEEPROM (256 bytes) */
#endif
#endif

#define CUR_SEL_TESTS_OS (BEG_BIST_DATA_OS+0)  /* beg of test selection bits */
#define CURRENT_LOOP_COUNT_OS (CUR_SEL_TESTS_OS+4) /* cur test loop count */
#define TEST_MODE_OS (CURRENT_LOOP_COUNT_OS+4) /* test mode bits */
#define ERROR_MODE_OS (TEST_MODE_OS+2)      /* error mode bits */
#define FF_TEST_NO_OS (ERROR_MODE_OS+1)     /* 1st Fail test number */
#define FF_12V_OS (FF_TEST_NO_OS+1)         /* 1st fail 12 volt reading */
#define FF_5V_OS (FF_12V_OS+1)              /* 1st fail 5 volt reading */
#define FF_3_3V_OS (FF_5V_OS+1)             /* 1st fail 3.3 volt reading */
#define FF_1_5V_OS (FF_3_3V_OS+1)           /* 1st fail 1.5 volt reading */
#define FF_TIME_OS (FF_1_5V_OS+1)           /* date & time of 1st fail */
#define FF_ERROR_CODE_OS (FF_TIME_OS+4)     /* 1st 32-bit error code */
#define FF_ERR_ADRS_OS (FF_ERROR_CODE_OS+4) /* 64-bit adrs in error */
#define FF_EXP_DATA_OS (FF_ERR_ADRS_OS+8)   /* 64 bits of expected data */
#define FF_REC_DATA_OS (FF_EXP_DATA_OS+8)   /* 64 bits of received data */
#define LF_ERROR_CODE_OS (FF_REC_DATA_OS+8) /* Last 32-bit error code */
#define START_TEST_TIME_OS (LF_ERROR_CODE_OS+4)/* date & time testing started */
#define FF_TEMP_OS (START_TEST_TIME_OS+4)    /* 1st Fail temperature */
#define ACCUM_TEST_TIME_OS (FF_TEMP_OS+1)   /* tot secs tests have run */
#define TOT_TEST_EXECS_OS (ACCUM_TEST_TIME_OS+4) /* tot test executions */
#define TOT_FAILS_OS (TOT_TEST_EXECS_OS+4)  /* tot execution failures */
#define EXEC_COUNT_OS (TOT_FAILS_OS+4)      /* programmed execution count */
#define EXT_TEST_MODES_OS (EXEC_COUNT_OS+4) /* extended test modes bits */
#define MAGIC_NUM_OS (EXT_TEST_MODES_OS+1)  /* magic number */
#define CHECKSUM_OS (MAGIC_NUM_OS+1)        /* check sum for diag data area */

/* calculate total number of diag area bytes currently being used */
#define MAX_BYTES_TO_READ ((CHECKSUM_OS - BEG_BIST_DATA_OS)+1)  

#define PROD_ID_OS START_TEST_TIME_OS       /* for now store prod id in unused
                                               loc for start test time */
#define HW_COMP_OS ACCUM_TEST_TIME_OS       /* for now store HW compatibility
                                               info in unused loc for accum 
                                               test time */

#define MAGIC_NUM 0x53                      /* magic number to indicate diag
                                               data may be valid */

#define TEST_SEL_LEN 4                      /* length of test select field */
#define TOT_TMODE_BYTES 2                   /* length of test mode field */
#define TOT_EMODE_BYTES 1                   /* length of error mode field */
#define TOT_TEST_NUM_BYTES 1                /* len of test FF TN field */
#define TOT_ERR_CODE_BYTES 4                /* len of error code field */
//#define TOT_FAIL_ADRS_BYTES 4               /* len of fail adrs field */
#define TOT_FAIL_ADRS_BYTES 8               /* len of fail adrs field */
//#define TOT_EXP_DATA_BYTES 4                /* len of exp data field */
#define TOT_EXP_DATA_BYTES 8                /* len of exp data field */
//#define TOT_REC_DATA_BYTES 4                /* len of rec data field */
#define TOT_REC_DATA_BYTES 8                /* len of rec data field */
#define TOT_DIAG_SEEPROM_BYTES 64           /* # of bytes alloc for diag use */
#define TOT_EXEC_COUNT_LEN 4                /* length of programed exec count 
                                               and total executions fields */
#define EXT_TMODES_LEN 1                    /* length of extended test modes 
                                               field */
#define TOT_FAILS_LEN 4                     /* length of tot fails field */
#define LOOP_COUNT_LEN 4                    /* length of cur loop count field */
#define PROD_ID_LEN 4                       /* length of prod id field */
#define HW_COMP_LEN 4                       /* length of HW compatibility 
                                               field */

#define TLV_HWComp 0x0136                   /* temp simple to define HW
                                               compatibility TLV entry */

/**  The global Test Mode flags are applied to all selected tests.
 ** The bits in the test mode flags variable are defined as follows:
 **
 ** NOTE: Also see "Extended Test Modes" variable below for more test options.
 **
 ** Bit  Description
 **  0   1=Disable all POST testing of all kinds.
 **  1   1=Enable extended POST test code.
 **  2   1=Enable operator intervention tests.
 **  3   1=Enable quick POST execution.
 **  4   1=Enable loop back tests.
 **  5   1=Enable manufacturing burn-in test mode.
 **  6   1=Error pending.  This bit is cleared every time POST tests begin
 **      executing.  If an error is encountered, this bit is set indicating
 **      a failure has occured during this execution of the POST code.  This
 **      is then used to decide if future tests should be skipped depending
 **      on the error mode selected.
 **  7   1=Escape key was pressed.  Skip disagnotics for this power up only.
 **      This bit is cleared just before diagnostic firmware hands
 **      control to normal firmware.
 **  8   1='m' key was pressed to go directly to diagnostic monitor.  This
 **      bit is cleared when diagnostic monitor begins to initialize.
 **  9   Last reset type: 0=Warm, 1=Cold
 **  10  1=Disable busy indicators for manufacturing test floor operation.
 **  11  Continuous test mode.  When set to one, all phase one and phase two
 **      tests will execute numher of times programmed byte the count in the
 **      "execution count" variable.
 **  12  Exit to normal firmware flag.  When set to a one, control will be 
 **      handed to normal firmware when all test paramters have been satisfied.
 **  13  "R" key was presseed at first count down message.  Pressing this key
 **      forces all selected tests to execute one time even if POST testing
 **      is disabled.
 **  14  Test mode is continuous and we already displayed 1st count down msg
 **
 **  15  Reserved
 **
 **
 **/
#define TM_DISABLE_POST 0x0001  /* disable all POST tests */
#define TM_EXT_TESTS 0x0002     /* enable extended test mode */
#define TM_OP_INTER_TESTS 0x0004/* enable op intervention tests */
#define TM_QUICK_POST_EN 0x0008 /* enable quick POST */
#define TM_EN_LB_TESTS 0x0010   /* enable loop back tests */
#define TM_EN_BURN_IN_MODE 0x0020/* enable burn in mode of testing */
#define TM_ERR_PENDING 0x0040   /* set if any test fails during POST */
#define TM_ESC_PRESSED 0x0080   /* escape key pressed right after power up */
#define TM_M_KEY_PRESSED 0x0100 /* 'm' key pressed right after power up */
#define TM_PU_RESET_TYPE 0x0200 /* last reset type: 1=Cold, 0=Warm */
#define TM_DIS_BUSY_IND  0x0400 /* disable busy indicators for mfg testing */
#define TM_CONT_TEST     0x0800 /* enable continuous testing mode */
#define TM_EXIT_TO_NF    0x1000 /* 1=exit to normal firmware when all tests 
                                   have completed execution */
#define TM_FORCE_TESTING 0x2000 /* 1="R" key pressed. force all selected tests
                                   to execute one time. */
#define TM_NO_COUNT_DOWN 0x4000 /* Don't display another countdown msg */

/* Mask of test_mode bits -- don't include TM_NO_COUNT_DOWN */
#define TM_MODE_MASK    0x1C3F

/**  The global Extended Test Mode flags are applied to all selected tests.  This
 ** variable is an extension of the "Test Modes" field above.  We needed more bits
 ** for test mode options so this formerly reserved byte is now used to flag
 ** more special test modes.
 **
 ** The bits in the extended test mode field are defined as follows:
 **
 ** NOTE: Also see "Test Modes" variable above for more test options.
 **
 ** Bit  Description
 **  0   1=Enable BIST "Auto Disable" feature.
 **  1   1=Flag to indicate we are in the middle of the "Auto Disable" feature.
 **      This bit works in conjunction with bit 0 above as described below:
 **
 **      Bit 1 Bit 0 Action taken
 **      ----- ----- --------------------------------------------------------
 **        X     0   Auto disabled mode is not active.  BIST runs normally.
 **        0     1   Auto disable mode will be active on next power up or reset.
 **        1     1   We are in the middle of BIST tests with Auto Disable mode 
 **                  active.  The following actions will be taken when both 
 **                  these bits are set:
 **                  - On reset or power up:
 **                    a - Set the "BIST Disable" bit (Turn BIST off) and
 **                        clear all other test mode bits.
 **                    b - Clear the "Auto Disable" bit (bit 0)
 **                    c - Clear the "Middle of BIST" flag (bit 1)
 **                  - When BIST exits normally after all BIST tests have
 **                    completed:
 **                    a - Set the "BIST Disable" bit (Turn BIST off) and
 **                        clear all other test mode bits.
 **                    b - Clear the "Auto Disable" bit (bit 0)
 **                    c - Clear the "Middle of BIST" flag (bit 1)
 **                  - Just before we have to reset to start Phase one tests
 **                    again because we are in the middle of a multi-pass
 **                    BIST test:
 **                    a - Clear the "Middle of BIST" flag (bit 1) (It will
 **                        get set again just after BIST Phase one code begins
 **                        to execute).
 ** 
 ** 7-2  Reserved
 **/
#define ETM_AUTO_DIS 0x0001     /* disable BIST automatically when done */
#define ETM_MIDL_OF_BIST 0x0002 /* flag to indicate we are in the middle of BIST
                                   tests while Auto disable mode is active */

/* end of Extended Test Modes definitions */

#define DEFAULT_EXEC_COUNT 1    /* default programmed execution count */

/* end of common diagnostic SEEPROM data area definitions */

#define DQUOTE_CHAR 0x22                /* double quote character */
#define ESCAPE_CHAR 0x1B                /* escape character */
#define CTRL_C_CHAR 0x03                /* ctrl-c character */
#define CTRL_X_CHAR 0x18                /* ctrl-x character */
#define ENTER_MENU_CHAR 'm'             /* char to enter BIST menu */
#define RUN_TESTS_CHAR 'r' /* char to force exec of all selected tests now */

/* the following symbols are used to test the phase 1 error logic */
#define LL_PH1_ADRS_IN_ERROR 0x05843800  /* error address */
#define LL_PH1_DATA_EXP_ERROR 0xD3D3D3D3  /* data expected */
#define LL_PH1_DATA_REC_ERROR 0xD3DDD3D3  /* data received */
/* end phase 1 error logic test definitions */

/**   The following symbols define the various standard configuration 
 ** registers required by all PCI decive designs.
 **/
#define PCI_ID                  0x00    /* device & vendor ID fields */
#define PCI_STAT_CMD            0x04    /* status & command */
#define PCI_CLASS_REV           0x08    /* class code & rev id */
#define PCI_CFG_CACHE_LINE_SIZE 0x0C    /* cache line size, latency timer */
#define PCI_BASE_ADRS_1         0x10    /* base address register 1 */
#define PCI_BASE_ADRS_2         0x14    /* base address register 2 */
#define PCI_BASE_ADRS_3         0x18    /* base address register 3 */
#define PCI_BASE_ADRS_4         0x1C    /* base address register 4 */
#define PCI_BASE_ADRS_5         0x20    /* base address register 5 */
#define PCI_BASE_ADRS_6         0x24    /* base address register 6 */
#define PCI_CIS_PTR             0x28    /* card CIS Pointer */
#define PCI_SUB_ID              0x2C    /* sub system dev & vendor id */
#define PCI_EXP_ROM_ADRS        0x30    /* Expansion ROM base adrs */
#define PCI_RES1                0x34    /* reserved area 1 */
#define PCI_RES2                0x38    /* reserved area 2 */
#define PCI_CFG_MAX_LAT         0x3C    /* max latency, min grant, etc */

#define PCI_PWR_CAP             0x40    /* power management capabilities */
#define PCI_PWR_CONT            0x44    /* power mgmt status & control */
/* end PCI configuration area definitions */

#define VALUE_FOR_ZERO_DATA 0x100       /* value added to check sum when a
                                           zero is encountered */

/**   The following symbols define the various offsets and static values
 ** required to search through and retrieve data in the TLV section of 
 ** the SEEPROM.  TLVs are maintained by the normal operating firmware but
 ** low-level POST code needs to retrieve product ID and possibly board 
 ** revision information before low-level POST can execute.
 **/
#define SEEPROM_BEG_ADRS_TLVS 0x000     /* adrs where TLVs start in SEEPROM */

#define TLV_TAG_OS 0x00                 /* offset from beg of tlv entry where
                                           TLV id tag is located */
#define TLV_LEN_OS 0x02                 /* offset from beg of tlv entry where
                                           TLV length is located */
#define TLV_HDR_ID_OS 0x04              /* offset from beg of tlv entry where
                                           TLV driver header eeprom_id field 
                                           is located */

#define TLV_DEV_HDR 0x0000              /* TLV device header entry is identified
                                           with this section id */
#define TLV_SEC1_HDR 0x0001             /* 1st TLV section header entry is 
                                           identified with this id */

#define TLV_PROD_ID_ENTRY 0x0130        /* product id TLV entry section
                                           indentifier */
#define TLV_HW_COMP_ID_ENTRY 0x0136     /* HW compatibility TLV entry section
                                           indentifier */
#define TLV_NOT_AVAIL 0x00000000        /* value used to to indicate we could
                                           not find the TLV entry we were 
                                           looking for */

#define TLV_HDR_EEPROM_ID 0x50524F4D    /* value of eeprom id field in driver
                                           header */

/**  The following symbols represent a unique value for each of the board
 ** types suported by this code.  These types are made up values used only
 ** by the BIST code.
 **/
#define PROD_TYPE_NPA_5644 10            /* NPA-5644 AMC card */
#define PROD_TYPE_NPA_5654 11            /* NPA-5654 AMC card */

#define PROD_TYPE_UNKNOWN 200               /* unknown product id */

#define INVALID_ID 0xFFFFFFFF           /* invalid product id */
/*  End TLV definitions */

/**  The following symbols represent all the definitions relating to the
 ** "product_lookup_table".
 **/
#define NUM_FIELDS_IN_PROD_TABLE 3      /* number of fields in each entry of
                                           table "product_lookup_table" */
#define PROD_TABLE_REC_LEN_IDX 0        /* offset from beginning of 
                                           "product_lookup_table" where record
                                           length is located */
#define PROD_TABLE_1ST_REC_IDX 1        /* index of 1st record in
                                           "product_lookup_table" */
#define PROD_TABLE_ID_FIELD_IDX 0       /* index of product id field in each
                                           record. */
#define PROD_TABLE_SIM_HWR_IDX 1        /* index of simulated hardware 
                                           availability register field in each
                                           record. */
#define PROD_TABLE_MSG_IDX 2            /* index of product sign-on message 
                                           offset field in each record. */
#define LOOK_UP_TABLE_TERMINATION 0     /* table termination value */

/* end of "product_lookup_table" definitions */

#define LO(VAL) (VAL & 0xFFFF)
#define HI(VAL) ((VAL >> 16) & 0xFFFF)

/**
 ** List of Field Replaceable Units (FRUs)
 **/
#define FRU_SLOT01      0x00000001
#define FRU_SLOT02      0x00000002
#define FRU_SLOT03      0x00000004
#define FRU_SLOT04      0x00000008
#define FRU_SLOT05      0x00000010
#define FRU_SLOT06      0x00000020
#define FRU_SLOT07      0x00000040
#define FRU_SLOT08      0x00000080
#define FRU_PS1         0x00000100      /* Power Supply 1 */
#define FRU_PS2         0x00000200
#define FRU_PS3         0x00000400
#define FRU_FAN1        0x00001000      /* Fan 1 */
#define FRU_FAN2        0x00002000
#define FRU_FAN3        0x00004000
#define FRU_DIMM1       0x00010000      /* DIMM 1 */
#define FRU_DIMM2       0x00020000
#define FRU_HA          0x20000000      /* High Availablity Board */
#define FRU_MB          0x40000000      /* Motherboard */
#define FRU_UNIT        0x80000000      /* Entire Unit */

#define FRU_LIST_TERM   0xFFFFFFFF      /* FRU list terminator */

/**    The following symbols define all the types of count-down messages
 ** that can be displayed by the "disp_countdown_msg()" function.
 **/
#define BIST_P1_CD_MSG 0         /* Phase I count down message */
#define BIST_P2_CD_MSG 1         /* Phase II count down message */


#endif  /* __LL_BIST_H__ */
