/*
Copyright (C) 2008, 2009  GE Fanuc, Inc
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
*/

#ifndef __CONFIG_H
#define __CONFIG_H

#include "version.h"

#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
#define CONFIG_OCTEON		1
#define CONFIG_OCTEON_38XX	1
/* CONFIG_OCTEON_AT5810 set by Makefile in include/config.h */

#if !defined(__U_BOOT_HOST__) && !defined(__BYTE_ORDER)
/* Set endian macros for simple exec includes, but not for host utilities */
#define __BYTE_ORDER __BIG_ENDIAN
#endif

/* Defaults to use if bootloader cannot autodetect settings */
#define DEFAULT_ECLK_FREQ_MHZ        600  /* Used if multiplier read fails, and for DRAM refresh rates */
/* Set this for 533 memory, as this config will work with 400 Mhz memory,
** albeit with poor performance.  This at least prevents a dead board.*/
#define AT5810_REV1_DEF_DRAM_FREQ    667

#define CONFIG_OCTEON_LLM_WORKAROUND
#define CONFIG_OCTEON_PCIX_WORKAROUND

/* Used to control conditional compilation for shared code between simple
** exec and u-boot */
#define CONFIG_OCTEON_U_BOOT

/* AT5810 uses configuration eeprom */
#define CONFIG_OCTEON_EEPROM_TUPLES     1

/* let the eth address be writeable */
#define CONFIG_ENV_OVERWRITE 1

/* bootloader usable memory size in bytes for at5810, hard code until autodetect */
#define OCTEON_MEM_SIZE (1*1024*1024*1024ULL)

/* POST "no error" indication */
#define NO_POST_ERROR               0xFF
#define FLASH_CHECKSUM_ERROR        0x00
#define RAM_FAILURE                 0x01
#define PHY_FAILURE                 0x02
#define RLDRAM_FAILURE				0x04
#define INTERFACE0_DIMM_NOT_DETECTED  0x05
#define INTERFACE1_DIMM_NOT_DETECTED  0x06

#define PMEM_FAILURE                0x08
#define TLBMISS_EXCEPTION           0x20
#define XTLBMISS_EXCEPTION          0x21
#define CACHE_EXCEPTION             0x22
#define GENERAL1_EXCEPTION          0x23
#define GENERAL2_EXCEPTION          0x24
#define DEBUG_EXCEPTION             0x25
#define SPI0_TSCLK_WAIT_ERROR       0x30
#define SPI1_TSCLK_WAIT_ERROR       0x31
#define SPI0_RSCLK_WAIT_ERROR       0x32
#define SPI1_RSCLK_WAIT_ERROR       0x33
#define SPI0_TRAINING_WAIT_ERROR    0x34
#define SPI1_TRAINING_WAIT_ERROR    0x35
#define SPI0_STAT_SYNC_WAIT_ERROR   0x36
#define SPI1_STAT_SYNC_WAIT_ERROR   0x37
#define RESERVED_CODE_BASE          0x80

#define TLBMISS_ADDRESS             0x200
#define XTLBMISS_ADDRESS            0x280
#define CACHE_ADDRESS               0x300
#define GENERAL1_ADDRESS            0x380
#define GENERAL2_ADDRESS            0x400
#define DEBUG_ADDRESS               0x480

/* Addresses for various things on boot bus.  These addresses
** are used to configure the boot bus mappings. */

/* Boot FLASH uses CS0 which reserves 128MB + 4MB                    : 0x17C00000 - 0x1FFFFFFF */
#define BOARD_BASE_FPGA_ADDR        0x16000000 /* CS1 reserves 16MB  : 0x16000000 - 0x16FFFFFF */
#define BOARD_BASE_PMEM_ADDR        0x28000000 /* CS3 reserves 64MB  : 0x28000000 - 0x2BFFFFFF */
#define BOARD_BASE_OTHER_PMEM_ADDR  0x29000000 /* other Octeon's PMEM is also in CS3 (second 16MB) */
#define BOARD_BASE_FLASH_SB_ADDR    0x30000000 /* CS2 reserves 128MB : 0x30000000 - 0x37FFFFFF */
#define BOARD_BASE_DIAG_ADDR        0x40000000 /* CS4 reserves 128MB : 0x40000000 - 0x47FFFFFF */

#define BOARD_FPGA_CHIP_SEL         1
#define BOARD_FLASH_SB_CHIP_SEL     2
#define BOARD_PMEM_CHIP_SEL         3
#define BOARD_DIAG_CHIP_SEL         4

/* #define OCTEON_CF_ATTRIB_CHIP_SEL   2 */
/* #define OCTEON_CF_ATTRIB_BASE_ADDR  0x1d010000 */
/* #define OCTEON_CF_COMMON_CHIP_SEL   3 */
/* Address bit 11 selects common memory space for Compact flash accesses */
#define OCTEON_CF_COMMON_BASE_ADDR  (0x1d000000 | (1 << 11))
/* #define OCTEON_CHAR_LED_CHIP_SEL    4 */
/* #define OCTEON_CHAR_LED_BASE_ADDR   0x1d020000 */
/* #define OCTEON_PAL_CHIP_SEL         1 */
#define OCTEON_PAL_BASE_ADDR        0x1d030000

/* SFP definitions */
#define SFP_TRANSCEIVER_6           6
#define SFP_COPPER                  0
#define SFP_FIBER                   7
#define SFP_VACANT                  0xFF

#define SFP_VS_STATUS               1
#define SFP_VS_EXTENDED_ADDRESS     22

/* SPD EEPROM addresses on AT5810 board */
#define BOARD_MMC_EEPROM_SIZE       (64 * 1024)
#define BOARD_MMC_RESERVED_START    0
#define BOARD_MMC_RESERVED_SIZE     (2 * 1024)
#define BOARD_MMC_BLADE_MAC_START   BOARD_MMC_RESERVED_START
#define BOARD_MMC_BLADE_MAC_SIZE    6
#define BOARD_MMC_RTM_MAC_START     (BOARD_MMC_BLADE_MAC_START + BOARD_MMC_BLADE_MAC_SIZE)
#define BOARD_MMC_RTM_MAC_SIZE      6
#define BOARD_MMC_POST_SIZE         1
#define BOARD_MMC_POST_UNDEFINED    0xFF
#define BOARD_MMC_POST_SHORT        0x00
#define BOARD_MMC_POST_LONG         0x01
#define BOARD_MMC_MEMTEST_POST      (BOARD_MMC_RTM_MAC_START  + BOARD_MMC_RTM_MAC_SIZE)
#define BOARD_MMC_PMEMTEST_POST     (BOARD_MMC_MEMTEST_POST   + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_PHYTEST_POST      (BOARD_MMC_PMEMTEST_POST  + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_CSUMTEST_POST     (BOARD_MMC_PHYTEST_POST   + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD1_POST        (BOARD_MMC_CSUMTEST_POST  + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD2_POST        (BOARD_MMC_RSVD1_POST     + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD3_POST        (BOARD_MMC_RSVD2_POST     + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD4_POST        (BOARD_MMC_RSVD3_POST     + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD5_POST        (BOARD_MMC_RSVD4_POST     + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD6_POST        (BOARD_MMC_RSVD5_POST     + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD7_POST        (BOARD_MMC_RSVD6_POST     + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD8_POST        (BOARD_MMC_RSVD7_POST     + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD9_POST        (BOARD_MMC_RSVD8_POST     + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD10_POST       (BOARD_MMC_RSVD9_POST     + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD11_POST       (BOARD_MMC_RSVD10_POST    + BOARD_MMC_POST_SIZE)
#define BOARD_MMC_RSVD12_POST       (BOARD_MMC_RSVD11_POST    + BOARD_MMC_POST_SIZE)
#define BOARD_POST_LOG_START        (BOARD_MMC_RESERVED_START + BOARD_MMC_RESERVED_SIZE)
#define BOARD_POST_LOG_SIZE         16
#define BOARD_EEPROM_UBOOT_START    (BOARD_POST_LOG_START + BOARD_POST_LOG_SIZE)
#define BOARD_MMC_UBOOT_APPL_START  (BOARD_MMC_EEPROM_SIZE - 2)

#define BOARD_DIMM_0_SPD_TWSI_ADDR  0x50
#define BOARD_DIMM_1_SPD_TWSI_ADDR  0x51
#define BOARD_DIMM_2_SPD_TWSI_ADDR  0x52
#define BOARD_DIMM_3_SPD_TWSI_ADDR  0x53

#define BOARD_EEPROM_TWSI_ADDR      0x62
#define BOARD_SFP0_TWSI_ADDR        0x63
#define BOARD_SFP1_TWSI_ADDR        0x64
#define BOARD_GBE_SWITCH_TWSI_ADDR  0x65

#define BOARD_MCU_TWSI_ADDR         0x60

#define BOARD_TWSI_READY_WAIT       100000000
#define BOARD_TWSI_READ_CMD_WAIT    100000000
#define BOARD_TWSI_WRITE_CMD_WAIT   100000000
#define BOARD_ERROR_MAX_RETRIES     100000

/* FPGA Definitions - General */
#define BOARD_VERSION_ID_REG                  (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0000)
#define BOARD_MASTER_CONTROL_REG              (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0002)
#define BOARD_RESET_REG                       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0004)
#define BOARD_OCTEON_INTERRUPT_ENABLE_REG     (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0006)
#define BOARD_OCTEON_INTERRUPT_PENDING_REG    (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0008)
#define BOARD_GBE_SWITCH_STATUS_REG           (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x000A)
#define BOARD_FP_SFP_CONTROL_STATUS_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x000C)
#define BOARD_FLASH_DEVICE_SEL_REG            (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x000E)
#define BOARD_DIAG_ADDR_DATA_LATCH_REG        (uint32_t *)(BOARD_BASE_FPGA_ADDR+0x0010)
#define BOARD_FIXED_PATTERN_REG               (uint32_t *)(BOARD_BASE_FPGA_ADDR+0x0014)
/* FPGA Definitions - TWSI/I2C Register Addresses */
#define BOARD_EEPROM_TWSI_CTRL_REG             (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0020)
#define BOARD_EEPROM_TWSI_ADDR_UPPER_REG       (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0021)
#define BOARD_EEPROM_TWSI_ADDR_LOWER_REG       (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0022)
#define BOARD_EEPROM_TWSI_DATA_REG             (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0023)
#define BOARD_SFP0_TWSI_CTRL_REG               (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0024)
#define BOARD_SFP0_TWSI_ADDR_UPPER_REG         (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0025)
#define BOARD_SFP0_TWSI_ADDR_LOWER_REG         (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0026)
#define BOARD_SFP0_TWSI_DATA_REG               (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0027)
#define BOARD_SFP1_TWSI_CTRL_REG               (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0028)
#define BOARD_SFP1_TWSI_ADDR_UPPER_REG         (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0029)
#define BOARD_SFP1_TWSI_ADDR_LOWER_REG         (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x002A)
#define BOARD_SFP1_TWSI_DATA_REG               (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x002B)
#define BOARD_GBE_SWITCH_TWSI_CTRL_REG         (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x002C)
#define BOARD_GBE_SWITCH_TWSI_ADDR_UPPER_REG   (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x002D)
#define BOARD_GBE_SWITCH_TWSI_ADDR_LOWER_REG   (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x002E)
#define BOARD_GBE_SWITCH_TWSI_DATA_REG         (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x002F)
/* FPGA Definitions - LEDs */
#define BOARD_GBE_SWITCH_LED_CLASS0_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0040)
#define BOARD_GBE_SWITCH_LED_CLASS1_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0042)
#define BOARD_GBE_SWITCH_LED_CLASS2_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0044)
#define BOARD_GBE_SWITCH_LED_CLASS3_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0046)
#define BOARD_GBE_SWITCH_LED_CLASS4_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0048)
#define BOARD_GBE_SWITCH_LED_CLASS5_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x004A)
#define BOARD_GBE_SWITCH_LED_CLASS6_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x004C)
#define BOARD_GBE_SWITCH_LED_CLASS7_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x004E)
#define BOARD_GBE_SWITCH_LED_CLASS8_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0050)
#define BOARD_GBE_SWITCH_LED_CLASS9_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0052)
#define BOARD_GBE_SWITCH_LED_CLASS10_REG      (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0054)
#define BOARD_GBE_SWITCH_LED_CLASS11_REG      (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0056)
#define BOARD_GBE_SWITCH_LED_ENABLE_REG       (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x005C)
#define BOARD_GBE_SWITCH_LED_TEST_REG         (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x005E)
/* FPGA Definitions - Mailbox */
#define BOARD_CAV_MB_FIFO_REG                 (uint32_t *)(BOARD_BASE_FPGA_ADDR+0x0060)
#define BOARD_CAV_XMT_DOORBELL_REG            (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0064)
#define BOARD_CAV_RCV_DOORBELL_REG            (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0066)
#define BOARD_IPMC_MB_REG                     (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x0068)
#define BOARD_IPMC_XMT_DOORBELL_REG           (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x006A)
#define BOARD_IPMC_RCV_DOORBELL_REG           (uint16_t *)(BOARD_BASE_FPGA_ADDR+0x006C)
/* FPGA Definitions - Redhawk */
#define BOARD_REDHAWK_BASE_REG                (BOARD_BASE_FPGA_ADDR+0x00400000)
#define BOARD_REDHAWK_CO_DEVICE               (uint32_t *)(BOARD_REDHAWK_BASE_REG+0x0000)
/* FPGA Definitions - RTM/Eagle */
#define BOARD_RTM_EAGLE_BASE_REG              (BOARD_BASE_FPGA_ADDR+0x00500000)
#define BOARD_RTM_EAGLE_CO_DEVICE             (uint32_t *)(BOARD_RTM_EAGLE_BASE_REG+0x0000)
/* FPGA Defintions - RTM/CPLD */
#define BOARD_RTM_CPLD_BASE_REG               (BOARD_BASE_FPGA_ADDR+0x00520000)
#define BOARD_RTM_GE_REVISION                 (uint16_t *)(BOARD_RTM_CPLD_BASE_REG+0x0000)
#define BOARD_RTM_GE_CARDID                   (uint16_t *)(BOARD_RTM_CPLD_BASE_REG+0x0002)

#define BOARD_TWSI_RUN_BIT                    0x80
#define BOARD_TWSI_ERROR_BIT                  0x40

#define BOARD_TWSI_RUN_READ_VAL               0x80
#define BOARD_TWSI_RUN_WRITE_VAL              0x81

#define BOARD_TXCR_CH0_EN                     0x01
#define BOARD_TXCR_CH1_EN                     0x02
#define BOARD_TXCR_CH2_EN                     0x04
#define BOARD_TXCR_CH3_EN                     0x08

#define BOARD_LED_GREEN                       0x08
#define BOARD_LED_YELLOW                      0x04

#define RH_DEFAULT_DEVID                      0x1212206D
#define EG_DEFAULT_DEVID                      0x42521049

#define SWFB_COMMAND_MAX                      512

#define CFG_64BIT_VSPRINTF  1
#define CFG_64BIT_STRTOUL   1

/* Master Control Register Ownership */
#define PHY_OWNED_MASK                        0x0003
#define PHY_OCT_B_OWNED                       0x0003
#define PHY_OCT_A_OWNED                       0x0002
#define GES_OWNED_MASK                        0x000C
#define GES_OCT_B_OWNED                       0x000C
#define GES_OCT_A_OWNED                       0x0008
#define RHWK_OWNED_MASK                       0x0030
#define RHWK_OCT_B_OWNED                      0x0030
#define RHWK_OCT_A_OWNED                      0x0020
#define GES_LED_OWNED_MASK                    0x00C0
#define GES_LED_OCT_B_OWNED                   0x00C0
#define GES_LED_OCT_A_OWNED                   0x0080
#define SFP_OWNED_MASK                        0x0300
#define SFP_OCT_B_OWNED                       0x0300
#define SFP_OCT_A_OWNED                       0x0200
#define PMEM_OWNED_MASK                       0x0C00
#define PMEM_OCT_B_OWNED                      0x0C00
#define PMEM_OCT_A_OWNED                      0x0800
#define MEMMOD_OWNED_MASK                     0x3000
#define MEMMOD_OCT_B_OWNED                    0x3000
#define MEMMOD_OCT_A_OWNED                    0x2000
#define RTM_OWNED_MASK                        0xC000
#define RTM_OCT_B_OWNED                       0xC000
#define RTM_OCT_A_OWNED                       0x8000
#define RTM_NOT_PRESET                        0x0000

/* RTM Identifier */
#define GE_RTM_CARDID 0x2090
/* Set bootdelay to 0 for immediate boot */
#define CONFIG_BOOTDELAY	0	/* autoboot after X seconds	*/

#define CONFIG_BAUDRATE		115200
#define CONFIG_DOWNLOAD_BAUDRATE		115200

/* valid baudrates */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
#undef	CONFIG_BOOTARGS


#define CFG_LOAD_ADDR       0x100000
#define CFG_BOOTOCT_ADDR    0x100000

#define CONFIG_MII

#define CFG_MAX_PROMPT_SIZE 50

/*
** Define CONFIG_PCI only if the system is known to provide a PCI
** clock to Octeon.  A bus error exception will occur if the inactive
** Octeon PCI core is accessed.  U-boot is not currently configured to
** recover when a exception occurs.
*/
#if CONFIG_OCTEON_PCI_UBOOT
#define CONFIG_PCI
#endif
/*-----------------------------------------------------------------------
 * PCI Configuration
 */
#if defined(CONFIG_PCI)

#define PCI_CONFIG_COMMANDS (CFG_CMD_PCI)

/*
** Define CONFIG_OCTEON_PCI_HOST = 1 to map the pci devices on the
** bus.  Define CONFIG_OCTEON_PCI_HOST = 0 for target mode when the
** host system performs the pci bus mapping instead.  Note that pci
** commands are enabled to allow access to configuration space for
** both modes.
*/
#ifndef CONFIG_OCTEON_PCI_HOST
#define CONFIG_OCTEON_PCI_HOST	0
#endif

#if (CONFIG_OCTEON_PCI_HOST)
#define CONFIG_PCI_PNP
#endif /* CONFIG_OCTEON_PCI_HOST */
#else  /* CONFIG_PCI */
#define PCI_CONFIG_COMMANDS (0)
#endif /* CONFIG_PCI */

/*
** The AT5810 does not use the internal arbiter in Octeon.
** Enable this for boards that do.
*/
#define USE_OCTEON_INTERNAL_ARBITER

/* Support for Intel 8254x gigabit chips. */
#define CONFIG_E1000

/* Define this to enable built-in octeon ethernet support */
#undef OCTEON_RGMII_ENET
/* Define this to enable spi4000 support */
#define OCTEON_SPI4000_ENET

/* Enable Octeon built-in networking if either SPI or RGMII support is enabled */
#if defined(OCTEON_RGMII_ENET) || defined(OCTEON_SPI4000_ENET)
#define OCTEON_INTERNAL_ENET
#endif

#if CONFIG_OCTEON_PCI_HOST
#define EXTRA_INCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | PCI_CONFIG_COMMANDS )
#define EXTRA_EXCLUDE_COMMANDS   (0)
#elif  defined(OCTEON_INTERNAL_ENET)
#define EXTRA_INCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII)
#define EXTRA_EXCLUDE_COMMANDS   (0)
#else
#define EXTRA_INCLUDE_COMMANDS   (0)
#define EXTRA_EXCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | PCI_CONFIG_COMMANDS )
#endif

/*-----------------------------------------------------------------------
 * U-boot Commands Configuration
 */
/* Srecord loading seems to be busted - checking for ctrl-c eats bytes */
#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_OCTEON | CFG_CMD_LOADB | CFG_CMD_FLASH \
                                  | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_RUN | CFG_CMD_EEPROM \
                                  | EXTRA_INCLUDE_COMMANDS | CFG_CMD_ASKENV)\
                                  & ~(EXTRA_EXCLUDE_COMMANDS | CFG_CMD_FPGA | CFG_CMD_BDI \
                                   | CFG_CMD_BEDBUG | CFG_CMD_BOOTD | CFG_CMD_LOADS | CFG_CMD_NFS))
#include <cmd_confdefs.h>

/*-----------------------------------------------------------------------
 * Networking Configuration
 */
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#define CONFIG_NET_MULTI

#ifdef CONFIG_PCI_PNP
/*
** Enable PCI networking devices if PCI is auto configured by u-boot.
*/
#define CONFIG_NATSEMI
#endif /* CONFIG_PCI_PNP */

#define CONFIG_BOOTP_DEFAULT		(CONFIG_BOOTP_SUBNETMASK | \
					CONFIG_BOOTP_GATEWAY	 | \
					CONFIG_BOOTP_HOSTNAME	 | \
					CONFIG_BOOTP_BOOTPATH)

#define CONFIG_BOOTP_MASK		CONFIG_BOOTP_DEFAULT
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */


#define CONFIG_NET_RETRY_COUNT 5

#define CONFIG_AUTO_COMPLETE 1
#define CFG_CONSOLE_INFO_QUIET 1

#define CONFIG_DOS_PARTITION 1

#define CFG_IDE_MAXBUS 1
#define CFG_IDE_MAXDEVICE 1

#ifdef CFG_CMD_EEPROM
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_I2C_EEPROM_ADDR     BOARD_EEPROM_TWSI_ADDR
#endif

/* Base address of Common memory for Compact flash */
#define CFG_ATA_BASE_ADDR  OCTEON_CF_COMMON_BASE_ADDR

/* Offset from base at which data is repeated so that it can be
** read as a block */
#define CFG_ATA_DATA_OFFSET     0x400

/* Not sure what this does, probably offset from base
** of the command registers */
#define CFG_ATA_REG_OFFSET      0

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory      */
#ifdef CONFIG_OCTEON_FAILSAFE
#define	CFG_PROMPT		((cvmx_read_csr(CVMX_GPIO_RX_DAT) & 0x8000) ? "AT5810 Octeon-B FS# " : "AT5810 Octeon-A FS# ")
#else
#if CONFIG_RAM_RESIDENT
#define	CFG_PROMPT		((cvmx_read_csr(CVMX_GPIO_RX_DAT) & 0x8000) ? "AT5810 Octeon-B(ram)# " : "AT5810 Octeon-A(ram)# ")
#else
#define	CFG_PROMPT		((cvmx_read_csr(CVMX_GPIO_RX_DAT) & 0x8000) ? "AT5810 Octeon-B# " : "AT5810 Octeon-A# ")
#endif
#endif
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
#define	CFG_MAXARGS		64		/* max number of command args*/

#define CFG_MALLOC_LEN		126*1024

#define CFG_BOOTPARAMS_LEN	32*1024

#define CFG_HZ			500000000ull      /* FIXME causes overflow in net.c */

#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */


#define CFG_MEMTEST_START	(CFG_SDRAM_BASE + 0x100000)
#define CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0xffffff)

#ifdef NOTNOW
	"bootloader_flash_update=protect off 0xbf460000 0xbf4fffff;erase 0xbf460000 0xbf4fffff;cp.b 0x7000000 0xbf460000 0x60000\0"	\
	"mempost=short\0"						\
	"csumpost=none\0"						\
	"phypost=short\0"						\
	"pmempost=short\0"						\
	""
#else
#define	CONFIG_EXTRA_ENV_SETTINGS			\
	"swfb_cmd=bootoctlinux\0"				\
	"swfb_flash_addr=b8000000\0"			\
	"swfb_ram_addr=6000000\0"				\
	"swfb_image_size=1800000\0"				\
	"swfb_cmd_arg=coremask=ffff\0"			\
	"autoload=yes\0"						\
	"autoscript=yes\0"						\
	"loadaddr=20001000\0"					\
	"ethact=e1000#0\0"						\
	"xaui0=yes\0"							\
	"e1000bonding=yes\0"					\
	"rhhphy0to=3\0"							\
	"uboot_version=" U_BOOT_VERSION	"\0"	\
	"presteramru=10240\0"					\
	"disable_spi4000=yes\0"					\
	"p0vid=2\0"								\
	"p1vid=3\0"								\
	"p2vid=1\0"								\
	"p3vid=1\0"								\
	"p4vid=1\0"								\
	"p5vid=3\0"								\
	"p6vid=2\0"								\
	"p7vid=1\0"								\
	"p8vid=4\0"								\
	"p9vid=5\0"								\
	"stdin=serial\0"						\
	"stdout=serial\0"						\
	"stderr=serial\0"						\
	"pmem_ddr=n\0"                                                  \
	""
#endif

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CFG_FLASH_SIZE	(128*1024*1024)	/* Flash size (bytes) */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	(1024)	/* max number of sectors on one chip */

/* Remapped base of flash for entire flash access */
/* Without remapping there would be a 4Meg limit */
/* The entire flash size is subtacted to preserve pc continuity */
#define CFG_FLASH_BASE		(0xbfc00000 -  CFG_FLASH_SIZE)
#define CFG_FLASH_PROTECT_LEN   0x80000  /* protect low 512K */

/* The following #defines are needed to get flash environment right */
#define	CFG_MONITOR_BASE	TEXT_BASE
#define	CFG_MONITOR_LEN		(192 << 10)

#define CFG_INIT_SP_OFFSET	0x400000

#define CFG_FLASH_CFI   1
#define CFG_FLASH_CFI_DRIVER   1

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */

#if CONFIG_RAM_RESIDENT
#define	CFG_ENV_IS_NOWHERE	1
#else
#define	CFG_ENV_IS_IN_FLASH	1
#endif

#define CFG_UBOOT_SIZE                    (2 * 1024 * 1024) /* 2MBytes */
#define CFG_FLASH_SECTOR_SIZE             (128 * 1024) /* 128 KBytes */
/* PRE-CS0 remapping */
#define CFG_ENV_SIZE                      CFG_FLASH_SECTOR_SIZE
#define CFG_NFI_SIZE                      CFG_FLASH_SECTOR_SIZE
#define CFG_NFI_SECTOR                    15
#define CFG_NFI_FASTBOOT_KEY              0x0f1e2d3c
#define CFG_FAILSAFE_BOOTLOADER_BASE      0xbfc00000
#define CFG_NORMAL_BOOTLOADER_BASE        (CFG_FAILSAFE_BOOTLOADER_BASE + CFG_UBOOT_SIZE)

#define CFG_IMAGE_SIZE_MAX                (CFG_UBOOT_SIZE - (CFG_ENV_SIZE + CFG_NFI_SIZE))

/* POST-CS0 remapping */
/* FLASH address map */
#define CFG_FS_BOOTLOADER_BASE            0xb7c00000
#define CFG_NORM_BOOTLOADER_BASE          (CFG_FS_BOOTLOADER_BASE + CFG_UBOOT_SIZE)
#define CFG_NFI_ADDR                      (CFG_FS_BOOTLOADER_BASE + (CFG_NFI_SECTOR * CFG_FLASH_SECTOR_SIZE))
#define CFG_NFI_FASTBOOT_KEY_ADDR         (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 8))
#define CFG_NFI_IMAGE_SIZE_ADDR           (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 16))
#define CFG_NFI_IMAGE_CHECKSUM_ADDR       (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 24))

#ifdef CONFIG_OCTEON_FAILSAFE
#define CFG_ENV_ADDR                      ((CFG_FS_BOOTLOADER_BASE + CFG_UBOOT_SIZE)-\
                                           (CFG_NFI_SIZE + CFG_ENV_SIZE))
#else
#define CFG_ENV_ADDR                      ((CFG_NORM_BOOTLOADER_BASE + CFG_UBOOT_SIZE)-\
                                           (CFG_NFI_SIZE + CFG_ENV_SIZE))
#endif

#define CFG_IMAGE_NOT_PRESENT             0xFFFFFFFFFFFFFFFF

#define CFG_SWFB_BASE                     (CFG_ENV_ADDR + CFG_ENV_SIZE)

#define CONFIG_FLASH_8BIT

#define CONFIG_NR_DRAM_BANKS	2

#define CONFIG_MEMSIZE_IN_BYTES

/* Prestera Ethernet Interface Identification */
#define PRES_FP_CP_0        0 /* Front Panel Control Port 0 */
#define PRES_FP_CP_1        1 /* Front Panel Control Port 1 */
#define PRES_BI_CP_0        2 /* Base Interface Control Port 0 */
#define PRES_BI_CP_1        3 /* Base Interface Control Port 1 */
#define PRES_OB_CP_0        4 /* Octeon B / 82546 Control Port 0 */
#define PRES_OB_CP_1        5 /* Octeon B / 82546 Control Port 1 */
#define PRES_OA_CP_0        6 /* Octeon A / 82546 Control Port 0 */
#define PRES_OA_CP_1        7 /* Octeon A / 82546 Control Port 1 */
#define PRES_RTM_CP_0       8 /* RTM Control Port 0 */
#define PRES_RTM_CP_1       9 /* RTM Control Port 1 */

#define SPI4000_PORT_MAX       16
#define SPI4000_MAP_STRING_MAX 16
#define EAGLE_LINK_RETRY_LIMIT 100

/* Boot Progress Messages
 * Upper - bit 13 => octeon A(0) / B(1), bits 12 ... 8 => timeout (minutes)
 * Lower byte - bits 7 .. 0 => progress code
 */
#define BPM_OCTEON_SPECIFIC    ((cvmx_read_csr(CVMX_GPIO_RX_DAT) & 0x8000) ? 0x2000 : 0x0000)
#define BPM_SYSTEM_INIT        (BPM_OCTEON_SPECIFIC | 0x0100)
#define BPM_CS_INIT            (BPM_OCTEON_SPECIFIC | 0x0101)
#define BPM_TIMER_INIT         (BPM_OCTEON_SPECIFIC | 0x0102)
#define BPM_ENV_INIT           (BPM_OCTEON_SPECIFIC | 0x0103)
#define BPM_EARLY_BOARD_INIT   (BPM_OCTEON_SPECIFIC | 0x0104)
#define BPM_INIT_BAUDRATE      (BPM_OCTEON_SPECIFIC | 0x0105)
#define BPM_SERIAL_INIT        (BPM_OCTEON_SPECIFIC | 0x0106)
#define BPM_CONSOLE_INIT_F     (BPM_OCTEON_SPECIFIC | 0x0107)
#define BPM_DISPLAY_BANNER     (BPM_OCTEON_SPECIFIC | 0x0108)
#define BPM_DRAM_CALIBRATE     (BPM_OCTEON_SPECIFIC | 0x0109)
#define BPM_MEM_MAP_CALCULATE  (BPM_OCTEON_SPECIFIC | 0x010A)
#define BPM_MEMPOST_SHORT      (BPM_OCTEON_SPECIFIC | 0x020B)
#define BPM_MEMPOST_LONG       (BPM_OCTEON_SPECIFIC | 0x040C)
#define BPM_PMEMPOST_SHORT     (BPM_OCTEON_SPECIFIC | 0x020D)
#define BPM_PMEMPOST_LONG      (BPM_OCTEON_SPECIFIC | 0x040E)
#define BPM_PHYPOST_SHORT      (BPM_OCTEON_SPECIFIC | 0x010F)
#define BPM_PHYPOST_LONG       (BPM_OCTEON_SPECIFIC | 0x0110)
#define BPM_CSUMPOST_SHORT     (BPM_OCTEON_SPECIFIC | 0x0211)
#define BPM_CSUMPOST_LONG      (BPM_OCTEON_SPECIFIC | 0x0412)
#define BPM_CODE_RELOCATE      (BPM_OCTEON_SPECIFIC | 0x0113)
#define BPM_RAM_BASED_EXECUTE  (BPM_OCTEON_SPECIFIC | 0x0114)
#define BPM_CMD_TABLE_RELOC    (BPM_OCTEON_SPECIFIC | 0x0115)
#define BPM_FLASH_INIT         (BPM_OCTEON_SPECIFIC | 0x0116)
#define BPM_MALLOC_INIT        (BPM_OCTEON_SPECIFIC | 0x0117)
#define BPM_MALLOC_BIN_RELOC   (BPM_OCTEON_SPECIFIC | 0x0118)
#define BPM_ENV_RELOC          (BPM_OCTEON_SPECIFIC | 0x0119)
#define BPM_BACKPRESSURE_WA    (BPM_OCTEON_SPECIFIC | 0x011A)
#define BPM_L2_CACHE_F_UL      (BPM_OCTEON_SPECIFIC | 0x011B)
#define BPM_DRAM_CLEAR         (BPM_OCTEON_SPECIFIC | 0x011C)
#define BPM_PCI_INIT           (BPM_OCTEON_SPECIFIC | 0x011D)
#define BPM_ETHERNET_INIT      (BPM_OCTEON_SPECIFIC | 0x011E)
#define BPM_PRESTERA_INIT      (BPM_OCTEON_SPECIFIC | 0x011F)
#define BPM_REDHAWK_INIT       (BPM_OCTEON_SPECIFIC | 0x0120)
#define BPM_EAGLE_INIT         (BPM_OCTEON_SPECIFIC | 0x0121)
#define BPM_PHYLINK_INIT       (BPM_OCTEON_SPECIFIC | 0x0122)
#define BPM_SPI0_INIT_DELAY    (BPM_OCTEON_SPECIFIC | 0x0123)
#define BPM_SPI0_INIT          (BPM_OCTEON_SPECIFIC | 0x0124)
#define BPM_SPI0_TSCLK_WAIT    (BPM_OCTEON_SPECIFIC | 0x0225)
#define BPM_SPI0_RSCLK_WAIT    (BPM_OCTEON_SPECIFIC | 0x0226)
#define BPM_SPI0_TRAINING_WAIT (BPM_OCTEON_SPECIFIC | 0x0227)
#define BPM_SPI0_CAL_SEND      (BPM_OCTEON_SPECIFIC | 0x0228)
#define BPM_SPI0_STAT_SYNC     (BPM_OCTEON_SPECIFIC | 0x0229)
#define BPM_SPI1_INIT_DELAY    (BPM_OCTEON_SPECIFIC | 0x012A)
#define BPM_SPI1_INIT          (BPM_OCTEON_SPECIFIC | 0x012B)
#define BPM_SPI1_TSCLK_WAIT    (BPM_OCTEON_SPECIFIC | 0x022C)
#define BPM_SPI1_RSCLK_WAIT    (BPM_OCTEON_SPECIFIC | 0x022D)
#define BPM_SPI1_TRAINING_WAIT (BPM_OCTEON_SPECIFIC | 0x022E)
#define BPM_SPI1_CAL_SEND      (BPM_OCTEON_SPECIFIC | 0x022F)
#define BPM_SPI1_STAT_SYNC     (BPM_OCTEON_SPECIFIC | 0x0230)
#define BPM_VERSION_NUM_STORE  (BPM_OCTEON_SPECIFIC | 0x0131)
#define BPM_MAC_ADDR_UPDATE    (BPM_OCTEON_SPECIFIC | 0x0132)
#define BPM_MAINLOOP           (BPM_OCTEON_SPECIFIC | 0x0033)

#define BPM_DOORBELL_ENTRY     0x4001

#define BOOT_PROGRESS_UPDATE(bpm) *BOARD_IPMC_MB_REG = bpm; \
                                  *BOARD_IPMC_XMT_DOORBELL_REG = BPM_DOORBELL_ENTRY;

#define PMEM_START_DEFAULT        0x410000000ull
#define BOARD_BASE_PMEM_DDR_ADDR  PMEM_START_DEFAULT
#define PMEM_SIZE_DEFAULT         (16 * 1024 * 1024) /* 16 MB */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		( 8 * 1024)
#define CFG_ICACHE_SIZE		(32 * 1024)
#define CFG_CACHELINE_SIZE	128

/*-----------------------------------------------------------------------
 * BOARD ID Information
 */
#define DDR2_512MB          0x00
#define DDR2_1GB            0x01
#define DDR2_2GB            0x02
#define DDR2_4GB            0x03

#define EGRESS_IO_VIA_RTM   0x08

/*-----------------------------------------------------------------------
 * DRAM Module Organization
 *
 * Octeon can be configured to use two pairs of DIMM's, lower and
 * upper, providing a 128/144-bit interface or one to four DIMM's
 * providing a 64/72-bit interface.  This structure contains the TWSI
 * addresses used to access the DIMM's Serial Presence Detect (SPD)
 * EPROMS and it also implies which DIMM socket organization is used
 * on the board.  Software uses this to detect the presence of DIMM's
 * plugged into the sockets, compute the total memory capacity, and
 * configure DRAM controller.  All DIMM's must be identical.
 */

#define DRAM_SOCKET_CONFIGURATION \
	{BOARD_DIMM_0_SPD_TWSI_ADDR, BOARD_DIMM_1_SPD_TWSI_ADDR}, \
	{BOARD_DIMM_2_SPD_TWSI_ADDR, BOARD_DIMM_3_SPD_TWSI_ADDR}

#if 0  /* Example: Enable for designs that don't use DIMMs with SPD */
/*
** For memory configurations that don't incorporate Serial Presence
** Detect (SPD) the SPD EEPROM can be simulated using a static table
** in memory.  This capability is enabled by defining
** STATIC_DRAM_CONFIG_TABLE to point to the array that contains the
** simulated SPD data.  In this case the DRAM_SOCKET_CONFIGURATION
** table takes on a slightly different function.  Instead of providing
** the TWSII address of each SPD EEPROM a non-zero value indicates
** that the STATIC_DRAM_CONFIG_TABLE should be applied for that DIMM
** interface.  A zero value indicates that no DRAM is present on that
** DIMM interface.
*/
#define STATIC_512MB_DRAM_CONFIG_TABLE static_512MB_ddr2_spd_data
#define STATIC_1GB_DRAM_CONFIG_TABLE static_1GB_ddr2_spd_data
#define STATIC_2GB_DRAM_CONFIG_TABLE static_2GB_ddr2_spd_data
#define STATIC_4GB_DRAM_CONFIG_TABLE static_4GB_ddr2_spd_data
#endif

#define DDR_BOARD_DELAY 3700

#endif	/* __CONFIG_H */
