/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Copyright 2004,2005 Cavium Networks
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * This file contains the configuration parameters for the octeon simulator
 */

#ifndef OCTEON_TNPA5651X_H
#define OCTEON_TNPA5651X_H
#include "octeon_common.h"

#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
#define CONFIG_OCTEON		1
#define CONFIG_OCTEON_56XX	1
#define CFG_LATE_BOARD_INIT	1
#define CONFIG_OCTEON_5651x     1

#define CONFIG_OCTEON_SGMII_DUAL 1

#define CONFIG_GEFES_PICMG_SUPPORT 1

#define CFG_PCI_CONSOLE 1
#define CFG_CONSOLE_IS_IN_ENV 1

#define CFG_MAX_PROMPT_SIZE 50

#define BOARD_MMC_AMC_MAC_SIZE  24

/* CONFIG_OCTEON_W5434 set by Makefile in include/config.h */

#if !defined(__U_BOOT_HOST__) && !defined(__BYTE_ORDER)
/* Set endian macros for simple exec includes, but not for host utilities */
#define __BYTE_ORDER __BIG_ENDIAN
#endif

/* Defaults to use if bootloader cannot autodetect settings */
#define DEFAULT_ECLK_FREQ_MHZ        600  /* (was 533 for 56x4) Used if multiplier read fails, and for DRAM refresh rates */
/* Set this for 533 memory, as this config will work with 400 Mhz memory,
** albeit with poor performance.  This at least prevents a dead board.*/
//#define WNPA3850_REV1_DEF_DRAM_FREQ  533

#define CONFIG_OCTEON_LLM_WORKAROUND
#define CONFIG_OCTEON_PCIX_WORKAROUND

/* Used to control conditional compilation for shared code between simple
** exec and u-boot */
#define CONFIG_OCTEON_U_BOOT

/* W5434 uses configuration eeprom */
#define CONFIG_OCTEON_EEPROM_TUPLES     1

/* let the eth address be writeable */
#define CONFIG_ENV_OVERWRITE 1

/* bootloader usable memory size in bytes for TNPA5651X, hard code until autodetect.
   set for 2 GB, since apparently all of these boards will have at least that. */ 
#define OCTEON_MEM_SIZE (2*1024*1024*1024ULL)

/* POST "no error" indication */
#define NO_POST_ERROR               0xFF
#define FLASH_CHECKSUM_ERROR        0x00
#define RAM_FAILURE                 0x01
#define PHY_FAILURE                 0x02
#define RLDRAM_FAILURE				0x04
#define INTERFACE0_DIMM_NOT_DETECTED  0x05
#define INTERFACE1_DIMM_NOT_DETECTED  0x06
#define PMEM_FAILURE                0x08
#define TLBMISS_EXCEPTION           0x20
#define XTLBMISS_EXCEPTION          0x21
#define CACHE_EXCEPTION             0x22
#define GENERAL1_EXCEPTION          0x23
#define GENERAL2_EXCEPTION          0x24
#define DEBUG_EXCEPTION             0x25
#define SPI0_TSCLK_WAIT_ERROR       0x30
#define SPI1_TSCLK_WAIT_ERROR       0x31
#define SPI0_RSCLK_WAIT_ERROR       0x32
#define SPI1_RSCLK_WAIT_ERROR       0x33
#define SPI0_TRAINING_WAIT_ERROR    0x34
#define SPI1_TRAINING_WAIT_ERROR    0x35
#define SPI0_STAT_SYNC_WAIT_ERROR   0x36
#define SPI1_STAT_SYNC_WAIT_ERROR   0x37
#define RESERVED_CODE_BASE          0x80

#define TLBMISS_ADDRESS             0x200
#define XTLBMISS_ADDRESS            0x280
#define CACHE_ADDRESS               0x300
#define GENERAL1_ADDRESS            0x380
#define GENERAL2_ADDRESS            0x400
#define DEBUG_ADDRESS               0x480

/* Addresses for various things on boot bus.  These addresses
** are used to configure the boot bus mappings. */
/* Boot FLASH uses CS0 which reserves 128MB + 4MB                    : 0x17C00000 - 0x1FFFFFFF */
#define BOARD_BASE_PMEM_LOWER_ADDR  0x13000000 /* CS2 reserves 16MB  : 0x30000000 - 0x30FFFFFF */
#define BOARD_BASE_PMEM_UPPER_ADDR  0x14000000 /* CS3 reserves 16MB  : 0x31000000 - 0x31FFFFFF */
#define BOARD_BASE_IDE_CMD_ADDR     0x15000000 /* CS4 reserved 64kB  : 0x32000000 - 0x3200FFFF */
#define BOARD_BASE_IDE_CTL_ADDR     0x15010000 /* CS5 reserved 64kB  : 0x32010000 - 0x3201FFFF */
#define BOARD_BASE_FPGA_ADDR        0x16000000 /* CS1 reserves 16MB  : 0x26000000 - 0x26FFFFFF */

/* keep this defined to the base of the PMEM addresses for backwards compatiblilty */
#define BOARD_BASE_PMEM_ADDR 		BOARD_BASE_PMEM_LOWER_ADDR   
#define BOARD_BASE_PMEM_DDR_ADDR        0x410000000ull

//jeremy w5434 - I think this is WRONG. I think these are being used mistakenly for the RAM memory addresses in cmd_eeprom memtest_xxbit()
#define PMEM_START_DEFAULT     BOARD_BASE_PMEM_LOWER_ADDR
#define PMEM_SIZE_DEFAULT      (32 * 1024 * 1024) /* 32 MB */


#define BOARD_FLASH_CHIP_SEL        0
#define BOARD_FPGA_CHIP_SEL         1
#define BOARD_PMEM_LOWER_CHIP_SEL	2
#define BOARD_PMEM_UPPER_CHIP_SEL   3
#define BOARD_IDE_CMD_CHIP_SEL      4
#define BOARD_IDE_CTL_CHIP_SEL      5

/* SPD EEPROM addresses on TNPA5651x (was 56X4) board */
#define BOARD_MMC_RESERVED_START    0
#define BOARD_MMC_RESERVED_SIZE     (2 * 1024)
#define BOARD_POST_LOG_START        (BOARD_MMC_RESERVED_START + BOARD_MMC_RESERVED_SIZE)
#define BOARD_POST_LOG_SIZE         16
#define BOARD_EEPROM_UBOOT_START    (BOARD_POST_LOG_START + BOARD_POST_LOG_SIZE)

/* TWSI Addresses */
#define BOARD_DIMM_0_SPD_TWSI_ADDR  0x57
#define BOARD_DIMM_1_SPD_TWSI_ADDR  0x58

#define BOARD_EEPROM_TWSI_ADDR      0x50
#define BOARD_SFP0_TWSI_ADDR        0x53
#define BOARD_SFP1_TWSI_ADDR        0x54
#define BOARD_SFP2_TWSI_ADDR        0x55
#define BOARD_SFP3_TWSI_ADDR        0x56
#define BOARD_TEMP_SENSOR_TWSI_ADDR 0x4c


/* #define BOARD_MCU_TWSI_ADDR         0x60 */

#define BOARD_TWSI_READY_WAIT       100000000
#define BOARD_TWSI_READ_CMD_WAIT    100000000
#define BOARD_TWSI_WRITE_CMD_WAIT   100000000
#define BOARD_ERROR_MAX_RETRIES     100000

#define BOARD_NFI_RESTORE_SIZE      1024

/* FPGA Definitions - General */
#define BOARD_VERSION_ID_REG                  (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0000)
/* two names for the same thing... */
#define BOARD_MODE_REG                        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0001)
#define BOARD_ID_DIPSWITCH_REG                (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0001)
#define BOARD_SDRAM_CONFIG_REG                (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0002)
#define BOARD_BOARD_CONFIG_REG                (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0003)
#define BOARD_INT_ENABLE_REG                  (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0004)
#define BOARD_INT_STATUS_REG                  (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0005)
#define BOARD_SFP_INT_ENABLE_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0006)
#define BOARD_SFP_INT_STATUS_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0007)
#define BOARD_RESET_REG                       (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0008)
#define BOARD_MISC_CTRL_REG                   (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0009)
#define BOARD_I2C_BUSY_REG                    (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000A)
#define BOARD_I2C_SW_RESET_REG                (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000B)
#define BOARD_SFP_TX_DISABLE_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000C)

#define FPGA_SWITCH_REG_EN_BIST  0x08   /* SW3-SEG4 on(0) = Allow BIST to run */

/* FPGA Definitions - TWSI/I2C Register Addresses */
#if defined(CONFIG_OCTEON_GEF_SFP_PRESENT)
#define BOARD_SFP3_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0010)
#define BOARD_SFP3_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0011)
#define BOARD_SFP3_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0012)
#define BOARD_SFP3_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0013)
#define BOARD_SFP2_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0014)
#define BOARD_SFP2_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0015)
#define BOARD_SFP2_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0016)
#define BOARD_SFP2_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0017)
#define BOARD_SFP1_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0018)
#define BOARD_SFP1_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0019)
#define BOARD_SFP1_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001A)
#define BOARD_SFP1_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001B)
#define BOARD_SFP0_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001C)
#define BOARD_SFP0_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001D)
#define BOARD_SFP0_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001E)
#define BOARD_SFP0_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001F)
#endif /* CONFIG_OCTEON_GEF_SFP_PRESENT */

#define BOARD_LP_XMIT_DBELL_0                 (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0020)
#define BOARD_LP_XMIT_DBELL_1                 (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0021)
#define BOARD_LP_XMIT_MBOX                    (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0022)
#define BOARD_HP_XMIT_DBELL_0                 (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0024)
#define BOARD_HP_XMIT_DBELL_1                 (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0025)
#define BOARD_HP_XMIT_MBOX                    (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0026)
#define BOARD_RECV_DBELL_0                    (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0028)
#define BOARD_RECV_DBELL_1                    (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0029)
#define BOARD_RECV_MBOX                       (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x002A)
#define BOARD_FLUSH_RECV_MBOX                 (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x002B)
/* This is the reg to control the upper 3 address lines to the bootflash */
#define BOARD_BOOT_FLASH_UPPER_ADDR_BITS_REG	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0020)
#define BOARD_MISC_FUNCTIONS_REG            	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0021)
#define BOARD_PHY_INTERRUPT_REG             	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0022)

#define BOARD_FPGA_OCTEON_MODE_UBOOT           (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0001) /* Read QLM1/QLM3 MUX setting */
#define BOARD_FPGA_QLM_1_3_CTRL_UBOOT           (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0030) /* Read QLM1/QLM3 mode cntrl settings */
#define BOARD_FPGA_INT_CTRL2                  (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0031)
#define BOARD_FPGA_INT_STATUS2                (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0032) 

#define BOARD_FIT_KEY_CODE_REG              	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0040)
#define BOARD_FIT_OSCILLATOR_CTRL_REG       	(uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0041)

/* beg adrs of MAC adrs table in FPGA dual-port RAM */
#define BOARD_DPR_MAC_COUNT                   (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0087)

/* the symbols below represent the "I2C IN USE" flags for the H8 & Octeon */
#define BOARD_DPR_H8_I2C_IN_USE               (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x00B0)
#define BOARD_DPR_OCT_I2C_IN_USE              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x00B1)

#define MAC_ADRS_COUNT   4     /* should be exactly these many mac adrs in table */
#define DPR_MAC_COUNT_OS 0x87  /* offset of mac count in dual-port RAM */
#define TOT_MAC_ENTRY_BYTES 0x07 /* tot bytes in each mac entry */
#define MAC_ETH0 0          /* designation for 1st Eth port attached to QLM1 */
#define MAC_ETH1 1          /* designation for 2nd Eth port attached to QLM3 */
#define MAC_ETH2 2          /* Port 0 on 82571 on QLM2 */
#define MAC_ETH3 3          /* Port 1 on 82571 on QLM2 */

/* These are the offsets into the 64 byte
   namedalloc area where each of these mac
   addresses are stored by U-boot to be
   later retrieved by the E1000 and the
   Cavium ethernet Linux drivers.
*/

#define MAC_ETH0_OFFSET (0 * 6)
#define MAC_ETH1_OFFSET (4 * 6)
#define MAC_ETH2_OFFSET (8 * 6)
#define MAC_ETH3_OFFSET (9 * 6)

#define UBOOT_SUCCESS 0           /* indication of successful completion */
#define UBOOT_PROBLEM_DETECTED 1  /* indication of unsuccessful completion */

#define SDRAM_CHANNEL_01  (1 << 6)
#define SDRAM_RANK_2      (1 << 5)
#define SDRAM_RANK_1       0
#define SDRAM_DENSITY_2G  (1 << 3)
#define SDRAM_DENSITY_1G   0
#define SDRAM_SPEED_400    0
#define SDRAM_SPEED_533   (1 << 0)
#define SDRAM_SPEED_667_5 (1 << 1)
#define SDRAM_SPEED_667_4 (3 << 0)
#define SDRAM_SPEED_800_6 (1 << 2)
#define SDRAM_SPEED_800_5 (5 << 0)
#define SDRAM_SPEED_MASK   0x07

/* Use these to setup QLM1 and QLM3 for SGMII or XAUI operation */

/* These GMX registers will be used in SGMII mode ONLY (!!) to
   set only one of the four lanes active so that it gets all
   the FIFO buffer space.  In XAUI mode, all 4 lanes are active
   by default.

   These PCS registers are used to setup SGMII mode and 1 G speed.

   These large value defines need "ull" or they will be interpreted
   by the compiler as "long" and generate a warning that the define
   is not large enough to hold the value.

   
*/

#define GMX0_TX_PRTS   0x0001180008000480ull
#define GMX1_TX_PRTS   0x0001180010000480ull

#define GMX0_RX_PRTS   0x0001180008000410ull
#define GMX1_RX_PRTS   0x0001180010000410ull

#define GMX_PRTS 0x0001  /* give the entire FIFO buffer space to one lane
							 when we are not using XAUI */

#define GMX0_PRT0_CFG  0x0001180008000010ull
#define GMX0_PRT1_CFG  0x0001180008000810ull
#define GMX0_PRT2_CFG  0x0001180008001010ull
#define GMX0_PRT3_CFG  0x0001180008001810ull

#define GMX0_INF_MODE  0x00011800080007F8ull

#define GMX1_PRT0_CFG  0x0001180010000010ull
#define GMX1_PRT1_CFG  0x0001180010000810ull
#define GMX1_PRT2_CFG  0x0001180010001010ull
#define GMX1_PRT3_CFG  0x0001180010001810ull

#define GMX1_INF_MODE  0x00011800100007F8ull


/* interface 0 (QLM 1) */
#define PCS0_MISC0_CTL_REG 0x00011800B0001078ull
#define PCS0_MISC1_CTL_REG 0x00011800B0001478ull
#define PCS0_MISC2_CTL_REG 0x00011800B0001878ull
#define PCS0_MISC3_CTL_REG 0x00011800B0001C78ull

#define PCS0_MR0_CONTROL_REG 0x00011800B0001000ull
#define PCS0_MR1_CONTROL_REG 0x00011800B0001400ull
#define PCS0_MR2_CONTROL_REG 0x00011800B0001800ull
#define PCS0_MR3_CONTROL_REG 0x00011800B0001C00ull

#define PCS0_TX_RX0_POLARITY_REG 0x00011800B0001048ull
#define PCS0_TX_RX1_POLARITY_REG 0x00011800B0001448ull
#define PCS0_TX_RX2_POLARITY_REG 0x00011800B0001848ull
#define PCS0_TX_RX3_POLARITY_REG 0x00011800B0001C48ull

#define PCS0_LINK0_TIMER_COUNT_REG 0x00011800B0001040ull
#define PCS0_LINK1_TIMER_COUNT_REG 0x00011800B0001440ull
#define PCS0_LINK2_TIMER_COUNT_REG 0x00011800B0001840ull
#define PCS0_LINK3_TIMER_COUNT_REG 0x00011800B0001C40ull

#define PCS0_MR0_STATUS_REG  0x00011800B0001008ull
#define PCS0_MR1_STATUS_REG  0x00011800B0001408ull
#define PCS0_MR2_STATUS_REG  0x00011800B0001808ull
#define PCS0_MR3_STATUS_REG  0x00011800B0001C08ull

/* interface 1 (QLM 3) */
#define PCS1_MISC0_CTL_REG 0x00011800B8001078ull
#define PCS1_MISC1_CTL_REG 0x00011800B8001478ull
#define PCS1_MISC2_CTL_REG 0x00011800B8001878ull
#define PCS1_MISC3_CTL_REG 0x00011800B8001C78ull
#define PCS1_MR0_CONTROL_REG 0x00011800B8001000ull /* defined elsewhere */
#define PCS1_MR1_CONTROL_REG 0x00011800B8001400ull
#define PCS1_MR2_CONTROL_REG 0x00011800B8001800ull
#define PCS1_MR3_CONTROL_REG 0x00011800B8001C00ull

#define PCS1_MR0_STATUS_REG  0x00011800B8001008ull
#define PCS1_MR1_STATUS_REG  0x00011800B8001408ull
#define PCS1_MR2_STATUS_REG  0x00011800B8001808ull
#define PCS1_MR3_STATUS_REG  0x00011800B8001C08ull

#define PCS1_TX_RX0_POLARITY_REG 0x00011800B8001048ull
#define PCS1_TX_RX1_POLARITY_REG 0x00011800B8001448ull
#define PCS1_TX_RX2_POLARITY_REG 0x00011800B8001848ull
#define PCS1_TX_RX3_POLARITY_REG 0x00011800B8001C48ull

#define PCS1_LINK0_TIMER_COUNT_REG 0x00011800B8001040ull
#define PCS1_LINK1_TIMER_COUNT_REG 0x00011800B8001440ull
#define PCS1_LINK2_TIMER_COUNT_REG 0x00011800B8001840ull
#define PCS1_LINK3_TIMER_COUNT_REG 0x00011800B8001C40ull

#define PCSX0_STATUS1_REG 0x00011800B0000808ull
#define PCSX0_STATUS2_REG 0x00011800B0000820ull
#define PCSX1_STATUS1_REG 0x00011800B8000808ull
#define PCSX1_STATUS2_REG 0x00011800B8000820ull

/* status reg masks */

#define LINK_STATUS 0x04    /* 0 = link down  1 = link up */
#define AUTO_NEG_ABLE 0x08  /* 1 = auto neg capable */
#define REMOTE_FAULT 0x10   /* 1 = remote fault detected */
#define AUTO_NEG_COMPLETE 0x20 /* auto neg complete, check results in PCSx_ANy_REG */
#define PRB_SUP 0x40        /* preamble suppression: 1 = able to work w/o preamble bytes at
							   beginning of frame, 0 = unable to work w/o preamble bytes */
#define EXT_ST 0x100      /* 1= extended status info in reg15 */
#define HUN_T2HD 0x200  /* 1 = 100 Base-T2 half duplex */
#define HUN_T2FD 0x400  /* 1 = 100 Base-T2 full duplex */
#define TEN_HD 0x800      /* 1 = 10 Mb half duplex */
#define TEN_FD 0x1000     /* 1 = 10 Mb full duplex */
#define HUN_XHD 0x2000    /* 1 = 100 Base-X half duplex */
#define HUN_XFD 0x4000    /* 1 = 100 Base-X full duplex */
#define HUN_T4  0x8000    /* 1 = 100 Base-T4 capable */

#define PCS_MISC_CTRL_VAL_NOGMX 0x0800 /* GMX disabled */
#define PCS_MISC_CTRL_VAL1_NOGMX 0x1901 /* GMX disabled, otherwise same as
										  PCS_MISC_CTRL_VAL */

#define PCS_MISC_CTRL_VAL 0x1101   /* According to Pete, we want to run in 1000Base X mode and NOT
									  SGMII - this means we can't negotiate down to 10 or 100 Mb */

#define PCS_MISC_CTRL_VAL1SGMII_NOGMX 0x1801 /* GMX disabled, otherwise same as
										  PCS_MISC_CTRL_VAL */

#define PCS_MISC_CTRL_VALSGMII 0x1001   /* TESTING: SGMII mode */


#define PCS_MRx_VAL1 0x1940  /* spd=1000Mb, full duplex, reset, auto-negotiate - pg 686) */
#define PCS_MRx_VAL2 0x1B40  /* spd=1000Mb, full duplex, reset, auto-negotiate restart,
                                 auto-negotiate - pg 686) */

#define LINK_TIMER_COUNT 0x19A4  /* for core clock period of 600 MHZ and 10 ms -
									see pg 689 in Octeon docs (was 0x16E4) */

/* #define PCS_MRx_NOAUTONEG_VAL1 0x0940   spd=1000Mb, full duplex, reset, no auto-negotiate
										  no reset - pg 686) */
/* #define PCS_MRx_NOAUTONEG_RESET 0x8940   spd=1000Mb, full duplex, reset, no auto-negotiate
										   with reset - pg 686) */


#define PCS_MRx_NOAUTONEG_VAL1 0x0140
#define PCS_MRx_NOAUTONEG_RESET 0x8140

#define PCS_MRx_AUTONEG_VAL1 0x1140
#define PCS_MRx_AUTONEGRESTART_VAL1 0x1340
#define PCS_MRx_AUTONEG_RESET 0x9140


#define GMX_ENABLE 0x0002
#define GMX_EN_CLR 0x000e
#define GMX_EN_SET 0x000f

#define SGMII_MODE 1


//need this code to put wherever we initialize the PHY interrupts
//cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 0x00);	// Set GPIO 12 to input pin
// 

/* MDIO Address of the M88E1111 PHYs*/
#define BOARD_PHY0_MDIO_ADDR				0x40
#define BOARD_PHY1_MDIO_ADDR				0x41
#define BOARD_PHY2_MDIO_ADDR				0x42
#define BOARD_PHY3_MDIO_ADDR				0x43


#define BOARD_TWSI_RUN_BIT                  0x80
#define BOARD_TWSI_ERROR_BIT                0x40

#define BOARD_TWSI_RUN_READ_VAL             0x80
#define BOARD_TWSI_RUN_WRITE_VAL            0x81

#define BOARD_TXCR_CH0_EN                   0x01
#define BOARD_TXCR_CH1_EN                   0x02
#define BOARD_TXCR_CH2_EN                   0x04
#define BOARD_TXCR_CH3_EN                   0x08

#define BOARD_LED_GREEN                     0x08
#define BOARD_LED_YELLOW                    0x04

#define SWFB_COMMAND_MAX                    512

#define CFG_64BIT_VSPRINTF  1
#define CFG_64BIT_STRTOUL   1

/* 10G PHYs */

/* MDIO Address of the AMCC 2025 10G PHY*/
#define BOARD_10G_PHY0_MDIO_ADDR                        0x00
#define BOARD_10G_PHY1_MDIO_ADDR                        0x01

#define MDIO_BUS_0       0
#define MDIO_BUS_1       1

#define CLAUSE22_NOT_USED           0x1F /* all 5 bits set to 1's */
#define AMCC_HEARTBEAT_THRESHOLD    10      /* used to check if the phy is alive */

#define AMCC_DEV_ADDR_PMA_PMD           1
#define AMCC_DEV_ADDR_WIS               2
#define AMCC_DEV_ADDR_PCS               3
#define AMCC_DEV_ADDR_XGXS              4

#define QT2025_PCS_REG_UC_STATUS        0xD7FD /* returns boot status, SFP status, and link status */
#define QT2025_PCS_REG_FW_HEARTB        0xD7EE /* heartbeat register, if the phy is booted this register will increment from 0x00 to 0xff*/
#define QT2025_PCS_REG_PHASE_REG        0xD653 /* heartbeat register, if the phy is booted this register will increment from 0x00 to 0xff*/
#define QT2025_PMA_PMD_CTRL1_REG        0x0000
#define QT2025_PMA_MDIO_RESETS_REG      0xC300
#define QT2025_PMA_UC8051_CFG_REG       0xC302
#define QT2025_PMA_I2C_RATE_SELECT_REG  0xC316
#define QT2025_PMA_I2C_SLAVE_ADDR_REG   0xC318
#define QT2025_PMA_UC8051_SPARE_2_REG   0xC319
#define QT2025_PMA_UC8051_SPARE_3_REG   0xC31A
#define QT2025_PCS_10G_R_SEED_B0_REG    0x0026
#define QT2025_PCS_10G_R_SEED_B1_REG    0x0027
#define QT2025_PCS_10G_R_SEED_B2_REG    0x0028
#define QT2025_PCS_VENDOR_SPECIFIC_REG  0xC000
#define QT2025_PMA_VENDOR_SPECIFIC1_REG 0xC001
#define QT2025_XDRV_CTRL_5_REG          0xC05A
#define QT2025_PMA_PMD_MODE_REG         0xC301
#define QT2025_PMA_PMD_PAD_IN_STATUS_REG 0xD002
#define QT2025_PMA_PMD_PAD_IN_INV_REG    0xD003
#define QT2025_PMA_PMD_PAD_OUT_STATUS_REG 0xD004
#define QT2025_GPIO_LED1_REG            0xD006
#define QT2025_GPIO_LED2_REG            0xD007
#define QT2025_PCS_FW_VERSION1_REG      0xD7F3
#define QT2025_PCS_FW_VERSION2_REG      0xD7F4
#define QT2025_PCS_FW_VERSION3_REG      0xD7F5
#define QT2025_PCS_FW_BUILD1_REG        0xD7F6
#define QT2025_PCS_FW_BUILD2_REG        0xD7F7
#define QT2025_PCS_FW_BUILD3_REG        0xD7F8
#define QT2025_PCS_SW_DLD_REG           0xE854
#define QT2025_PMA_CORE_CONT2_REG       0xF053
#define QT2025_PMA_FINAL_INIT1_REG      0xF058
#define QT2025_PMA_FINAL_INIT2_REG      0xF055
#define QT2025_PCS_LED_CTRL_REG         0xD70D

#define QT2025_PCS_PRECALC_CSUM0_REG    0x8A00
#define QT2025_PCS_PRECALC_CSUM1_REG    0x8A01

#define QT2025_PCS_POSTCALC_CSUM0_REG   0xD718
#define QT2025_PCS_POSTCALC_CSUM1_REG   0xD719

#define QT2025_PCS_FWSIZE0_REG          0x8A02
#define QT2025_PCS_FWSIZE1_REG          0x8A03

#define QT2025_PCS_CSUMSTAT0_REG        0xD716
#define QT2025_PCS_CSUMSTAT1_REG        0xD717

#define QT2025_PCS_R_STATUS_1_REG       0x0020
#define QT2025_PCS_R_STATUS_2_REG       0x0021

#define QT2025_PMA_RXSIGOK_REG          0x000A
#define QT2025_PHY_XGXS_LANE_STATUS_REG 0x0018

#define QT2025_PCS_RX_1G_STATUS_REG     0xC050
#define QT2025_PCS_TX_1G_STATUS_REG     0xC058

#define QT2025_PMA_RX_ALRM_STAT_REG     0x9003
#define QT2025_PMA_TX_ALRM_STAT_REG     0x9004



/**
 * Used to determine what type of I/O is on the front of the
 * card.
 */

#define SFP_COPPER                      0x00
#define SFP_DIRECT_ATTACHED     0x04
#define SFP_FIBER                       0x07

#define SFP_TYPE( x )                                                           \
        (( x == 0xFF || x < 0 ) ? VACANT :                      \
        ( x & 0x8 ) ? SFP_COPPER :                                              \
        ( (x & 0xF) == 0x4 ) ? SFP_DIRECT_ATTACHED : SFP_FIBER )
#define SFP_STRING( x )                                                         \
        (( x == SFP_FIBER ) ? "F " :                                    \
         ( x == SFP_COPPER ) ? "C " :                           \
         ( x == SFP_DIRECT_ATTACHED ) ? "DA " : "V " )


#if 0
#define  PHY_PRESENT            0x00
#define  SFP_PRESENT            0x02
#define  SFP_10G_PRESENT        0x04
#define  SFP_10G_DUAL_PRESENT   0x06

#define IS_SFP_PRESENT              ((*BOARD_ID_DIPSWITCH_REG & 0x0E) == SFP_PRESENT)
/* flag to check if there is a 10G phy on the board. It detects both 56511 and 56512(dual port) cards. */
#define IS_10G_PHY_PRESENT          (((*BOARD_ID_DIPSWITCH_REG & 0x0E) == SFP_10G_PRESENT) || IS_10G_DUAL_PHY_PRESENT)
/* flag to check if we have a 56512 dual port card. It only detects dual port cards */
#define IS_10G_DUAL_PHY_PRESENT     ((*BOARD_ID_DIPSWITCH_REG & 0x0E) == SFP_10G_DUAL_PRESENT)
#endif /* if 0 */

/* Set bootdelay to 0 for immediate boot */
#define CONFIG_BOOTDELAY	0	/* autoboot after X seconds	*/

#define CONFIG_BAUDRATE					115200
#define CONFIG_DOWNLOAD_BAUDRATE		115200

/* valid baudrates */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
#undef	CONFIG_BOOTARGS


#define CFG_LOAD_ADDR       0x100000
#define CFG_BOOTOCT_ADDR    0x100000

#undef CONFIG_MII

/*
** Define CONFIG_PCI only if the system is known to provide a PCI
** clock to Octeon.  A bus error exception will occur if the inactive
** Octeon PCI core is accessed.  U-boot is not currently configured to
** recover when a exception occurs.
*/
#if CONFIG_OCTEON_PCI_UBOOT
#define CONFIG_PCI
#endif
/*-----------------------------------------------------------------------
 * PCI Configuration
 */
#if defined(CONFIG_PCI)

#define PCI_CONFIG_COMMANDS (CFG_CMD_PCI)

/*
** Define CONFIG_OCTEON_PCI_HOST = 1 to map the pci devices on the
** bus.  Define CONFIG_OCTEON_PCI_HOST = 0 for target mode when the
** host system performs the pci bus mapping instead.  Note that pci
** commands are enabled to allow access to configuration space for
** both modes.
*/
#ifndef CONFIG_OCTEON_PCI_HOST
#define CONFIG_OCTEON_PCI_HOST	0
#endif

#if (CONFIG_OCTEON_PCI_HOST)
#define CONFIG_PCI_PNP
#endif /* CONFIG_OCTEON_PCI_HOST */
#else  /* CONFIG_PCI */
#define PCI_CONFIG_COMMANDS (0)
#endif /* CONFIG_PCI */

/*
** The W3860 does not use the internal arbiter in Octeon.
** Enable this for boards that do.
*/
/*TODO: what value for the TNPA5651X?*/
#undef USE_OCTEON_INTERNAL_ARBITER

/* Support for Intel 8254x gigabit chips. */
#define CONFIG_E1000

/* Define this to enable built-in octeon ethernet support */
#define OCTEON_RGMII_ENET
/* Define this to enable spi4000 support */
#undef OCTEON_SPI4000_ENET

/* Enable Octeon built-in networking if either SPI or RGMII support is enabled */
#if defined(OCTEON_RGMII_ENET) || defined(OCTEON_SPI4000_ENET)
#define OCTEON_INTERNAL_ENET
#endif

#if CONFIG_OCTEON_PCI_HOST
#define EXTRA_INCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | PCI_CONFIG_COMMANDS )
#define EXTRA_EXCLUDE_COMMANDS   (0)
#elif CONFIG_OCTEON_FAILSAFE
#define EXTRA_INCLUDE_COMMANDS   (0)
#define EXTRA_EXCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | PCI_CONFIG_COMMANDS )
#elif  defined(OCTEON_INTERNAL_ENET)
#define EXTRA_INCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII)
#define EXTRA_EXCLUDE_COMMANDS   (0)
#else
#define EXTRA_INCLUDE_COMMANDS   (0)
#define EXTRA_EXCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | PCI_CONFIG_COMMANDS )
#endif


/*-----------------------------------------------------------------------
 * U-boot Commands Configuration
 */
/* Srecord loading seems to be busted - checking for ctrl-c eats bytes */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_OCTEON | \
                          CFG_CMD_LOADB | CFG_CMD_EEPROM | CFG_CMD_ENV |   \
                          CFG_CMD_FLASH | CFG_CMD_IDE | CFG_CMD_FAT |     \
                          CFG_CMD_RUN | CFG_CMD_ELF | EXTRA_INCLUDE_COMMANDS | \
                          CFG_CMD_ASKENV | CFG_CMD_PING | CFG_CMD_OCTEON_BOOTLOADER_UPDATE)\
                          & ~(EXTRA_EXCLUDE_COMMANDS | CFG_CMD_FPGA | \
                              CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_BOOTD | \
                              CFG_CMD_LOADS | CFG_CMD_NFS))
#include <cmd_confdefs.h>

/*-----------------------------------------------------------------------
 * Networking Configuration
 */
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#define CONFIG_NET_MULTI

#ifdef CONFIG_PCI_PNP
/*
** Enable PCI networking devices if PCI is auto configured by u-boot.
*/
//#define CONFIG_NATSEMI /* we do not have one of these devices */
#endif /* CONFIG_PCI_PNP */

#define CONFIG_BOOTP_DEFAULT		(CONFIG_BOOTP_SUBNETMASK | \
					CONFIG_BOOTP_GATEWAY	 | \
					CONFIG_BOOTP_HOSTNAME	 | \
					CONFIG_BOOTP_BOOTPATH)

#define CONFIG_BOOTP_MASK		CONFIG_BOOTP_DEFAULT
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */


#define CONFIG_NET_RETRY_COUNT 5

#define CONFIG_AUTO_COMPLETE 1
#define CFG_CONSOLE_INFO_QUIET 1

#define CONFIG_DOS_PARTITION 1

#define CFG_IDE_MAXBUS 1
#define CFG_IDE_MAXDEVICE 1

#ifdef CFG_CMD_EEPROM
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_I2C_EEPROM_ADDR     BOARD_EEPROM_TWSI_ADDR
#endif

/* Base address of Common memory for Compact flash */
#define OCTEON_CF_COMMON_BASE_ADDR 0x15010000
#define CFG_ATA_BASE_ADDR  OCTEON_CF_COMMON_BASE_ADDR

/* Offset from base at which data is repeated so that it can be
** read as a block */
#define CFG_ATA_DATA_OFFSET     0x400

/* Not sure what this does, probably offset from base
** of the command registers */
#define CFG_ATA_REG_OFFSET      0

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory      */

#ifdef CONFIG_OCTEON_FAILSAFE
#define	CFG_PROMPT		"Octeon tnpa5651x Failsafe bootloader# "	/* Monitor Command Prompt    */
#else
#if CONFIG_RAM_RESIDENT
#define	CFG_PROMPT		"Octeon tnpa5651x(ram)# "	/* Monitor Command Prompt    */
#else
#define	CFG_PROMPT		"Octeon tnpa5651x# "	/* Monitor Command Prompt    */
#endif
#endif


#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
#define	CFG_MAXARGS		64		/* max number of command args*/

#define CFG_MALLOC_LEN		126*1024 /* from repository */

#define CFG_BOOTPARAMS_LEN	32*1024 /* from repository */

#define CFG_HZ			500000000ull      /* FIXME causes overflow in net.c */

#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */


#define CFG_MEMTEST_START	(CFG_SDRAM_BASE + 0x100000)
#define CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0xffffff)

#define ASCII_DEF_UBOOT_SIZE "00100000" /* ASCII default max size (in bytes) of
                                           Uboot image */
#define ASCII_DEF_LINUX_SIZE "2000000" /* ASCII default max size (in bytes) of 
                                          linux image */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_BOOTLOADER_UPDATE_ENV_SETTING	\
	"autoload=yes\0"					\
	"autoscript=yes\0"						\
        "ncmac_alloc=yes\0"                                             \
	CONFIG_ETH_ENV_SETTING			\
	"swfb_cmd=bootoctlinux\0"		\
	"swfb_flash_addr=b8000000\0"	\
	"swfb_ram_addr=20000000\0"		\
	"swfb_image_size="ASCII_DEF_LINUX_SIZE"\0"		\
	CONFIG_OCTEON_COREMASK	\
	"mdio_alloc=yes\0" \
	""

/**********************************/
/* define other ENV settings here */
/**********************************/
#if defined(CONFIG_OCTEON_FAILSAFE)

#define CONFIG_BOOTLOADER_UPDATE_ENV_SETTING 	\
	"bootloader_flash_update_failsafe=protect off 0xb7c00000 0xb7d3ffff;erase 0xb7c00000 0xb7d3ffff;cp.b 0x20000000 0xb7c00000 0x"ASCII_DEF_UBOOT_SIZE"; validatenfi 0 0\0"	\
	"bootloader_flash_update_normal_bank0=protect off 0xb7d40000 0xb7e7ffff;erase 0xb7d40000 0xb7e7ffff;cp.b 0x20000000 0xb7d40000 0x"ASCII_DEF_UBOOT_SIZE"; validatenfi 0\0" \
	"bootloader_flash_update_normal_bank1=protect off 0xb7e80000 0xb7fbffff;erase 0xb7e80000 0xb7fbffff;cp.b 0x20000000 0xb7e80000 0x"ASCII_DEF_UBOOT_SIZE"; validatenfi 1\0"
#else
#define CONFIG_BOOTLOADER_UPDATE_ENV_SETTING 	\
	"bootloader_flash_update_normal_bank0=protect off 0xb7d40000 0xb7e7ffff;erase 0xb7d40000 0xb7e7ffff;cp.b 0x20000000 0xb7d40000 0x"ASCII_DEF_UBOOT_SIZE"; validatenfi 0\0" \
	"bootloader_flash_update_normal_bank1=protect off 0xb7e80000 0xb7fbffff;erase 0xb7e80000 0xb7fbffff;cp.b 0x20000000 0xb7e80000 0x"ASCII_DEF_UBOOT_SIZE"; validatenfi 1\0"
#endif /* CONFIG_OCTEON_FAILSAFE */
    
/* we want to start from the first SFP port which is (usually) octeth2 */
#define CONFIG_ETH_ENV_SETTING	"ethact=octeth0\0"
#define CONFIG_OCTEON_COREMASK	"swfb_cmd_arg=coremask=fff\0"

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

#define CFG_FLASH_SIZE	(128*1024*1024)	/* Flash size (Mbytes) */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	(1024)	/* max number of sectors on one chip */

/* Remapped base of flash for entire flash access */
/* Without remapping there would be a 4Meg limit */
/* The entire flash size is subtacted to preserve pc continuity */
#define CFG_FLASH_BASE		(0xbfc00000 -  CFG_FLASH_SIZE)
#define CFG_FLASH_PROTECT_LEN   0x80000  /* protect low 512K */

#define CFG_FAILSAFE_BOOTLOADER_BASE      0xbfc00000
#define CFG_NORMAL_BOOTLOADER_BASE        (CFG_FAILSAFE_BOOTLOADER_BASE + CFG_UBOOT_SIZE)
#define CFG_FAILSAFE_BOOTLOADER_SIZE      (CFG_NORMAL_BOOTLOADER_BASE - 0xbfc00000)

#define CFG_IMAGE_SIZE_MAX                (CFG_UBOOT_SIZE - (CFG_ENV_SIZE + CFG_NFI_SIZE))

/* The following #defines are needed to get flash environment right */
#define	CFG_MONITOR_BASE	TEXT_BASE

/* was 192 */
#define	CFG_MONITOR_LEN		(192 << 10)

//#define CFG_INIT_SP_OFFSET	0x400000 /* fron repository */
#define CFG_INIT_SP_OFFSET	0x1000000   // where stack lives? jeremy

#define CFG_FLASH_CFI   1
#define CFG_FLASH_CFI_DRIVER   1

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */

#define	CFG_ENV_IS_IN_FLASH	1

#define CFG_NORMAL_RUN_START              0x80100000 /* from repository */
//#define CFG_NORMAL_RUN_START              0x80800000 /* jeremy's code */

#define CFG_FLASH_SECTOR_SIZE             (128 * 1024) /* 128 KBytes */
#define CFG_UBOOT_SIZE                    (10 * CFG_FLASH_SECTOR_SIZE) /* 1.25 MBytes */
/* PRE-CS0 remapping */
#define CFG_ENV_SIZE                      CFG_FLASH_SECTOR_SIZE
#define CFG_NFI_SIZE                      CFG_FLASH_SECTOR_SIZE
#define CFG_NFI_SECTOR                    9
#define CFG_NFI_FASTBOOT_KEY              0x0f1e2d3c
#define CFG_FAILSAFE_BOOTLOADER_BASE      0xbfc00000
#define CFG_NORMAL0_BOOTLOADER_BASE       (CFG_FAILSAFE_BOOTLOADER_BASE + CFG_UBOOT_SIZE)
#define CFG_NORMAL1_BOOTLOADER_BASE       (CFG_NORMAL0_BOOTLOADER_BASE + CFG_UBOOT_SIZE)

#define CFG_IMAGE_SIZE_MAX                (CFG_UBOOT_SIZE - (CFG_ENV_SIZE + CFG_NFI_SIZE))

/* POST-CS0 remapping */
/* FLASH address map */
#define CFG_FS_BOOTLOADER_BASE            0xb7c00000
#define CFG_NORM0_BOOTLOADER_BASE         (CFG_FS_BOOTLOADER_BASE + CFG_UBOOT_SIZE)
#define CFG_NORM1_BOOTLOADER_BASE         (CFG_NORM0_BOOTLOADER_BASE + CFG_UBOOT_SIZE)
#define CFG_NFI_ADDR                      (CFG_FS_BOOTLOADER_BASE + (CFG_NFI_SECTOR * CFG_FLASH_SECTOR_SIZE))
#define CFG_NFI_FASTBOOT_KEY_ADDR         (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 8))
#define CFG_NFI_IMAGE_SIZE_ADDR           (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 16))
#define CFG_NFI_IMAGE_CHECKSUM_ADDR       (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 24))
#define CFG_NFI_SOAK_COUNTER_ADDR         (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 32))
#define CFG_NFI_TEST_FLAG_ADDR            (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 40))
#define CFG_NFI_BOOT_BANK_ADDR            (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 48))

#define CFG_ENV_ADDR                      ((CONFIG_IMAGE_BASE + CFG_UBOOT_SIZE)-\
										   (CFG_NFI_SIZE + CFG_ENV_SIZE))




#define CFG_IMAGE_NOT_PRESENT             0xFFFFFFFFFFFFFFFF

#define CONFIG_FLASH_8BIT

#define CONFIG_NR_DRAM_BANKS	2

#define CONFIG_MEMSIZE_IN_BYTES

/* Boot Progress Messages
 * Upper - bit 13 => octeon A(0) / B(1), bits 12 ... 8 => timeout (minutes)
 * Lower byte - bits 7 .. 0 => progress code
 *
 *   The list below contains various Uboot(Octeon)-To-H8 Boot progress 
 * messages that are sent through the low-priority FPGA mailbox.
 *   Each message consists of two bytes.  The upper byte contains the
 * requested number of minutes the H8 is to delay, without receiving another
 * boot progress message, before resetting the Octeon.  The lower byte
 * is a value indicating the progress of the Uboot sequence (where in the 
 * Uboot sequence the code is currently executing).
 *
 * NOTE:  If the upper byte is set to zero, the Octeon/Uboot watchdog
 *        timer event is disabled on the H8.
 * 
 */
#define BPM_OCTEON_SPECIFIC    (0x0000)

#define BPM_DISABLE_WATCH_DOG                         0x0000
#define BPM_PRI_PROC_INIT      (BPM_OCTEON_SPECIFIC | 0x0134)
#define BPM_MAINLOOP           (BPM_OCTEON_SPECIFIC | 0x0033) /* board.c */
#define BPM_EXEC_BIST          (BPM_OCTEON_SPECIFIC | 0x00F0) /* Executing BIST  tests */


/* #define BPM_SYSTEM_INIT        (BPM_OCTEON_SPECIFIC | 0x0100) */
#define BPM_CS_INIT            (BPM_OCTEON_SPECIFIC | 0x0101) /* lib_octeon.c */
#define BPM_TIMER_INIT         (BPM_OCTEON_SPECIFIC | 0x0102) /* time.c */
#define BPM_ENV_INIT           (BPM_OCTEON_SPECIFIC | 0x0103) /* env_flash.c */
#define BPM_EARLY_BOARD_INIT   (BPM_OCTEON_SPECIFIC | 0x0104) /* octeon_tnpa56x4_board.c */
#define BPM_INIT_BAUDRATE      (BPM_OCTEON_SPECIFIC | 0x0105) /* board.c */
#define BPM_SERIAL_INIT        (BPM_OCTEON_SPECIFIC | 0x0106) /* octeon_serial.c */
#define BPM_CONSOLE_INIT_F     (BPM_OCTEON_SPECIFIC | 0x0107) /* console.c */
#define BPM_DISPLAY_BANNER     (BPM_OCTEON_SPECIFIC | 0x0108) /* board.c */
#define BPM_DRAM_CALIBRATE     (BPM_OCTEON_SPECIFIC | 0x0109) /* board.c */ 
#define BPM_MEM_MAP_CALCULATE  (BPM_OCTEON_SPECIFIC | 0x010A) /* board.c */
#define BPM_MEMPOST_SHORT      (BPM_OCTEON_SPECIFIC | 0x020B) /* cmd_eeprom.c */
#define BPM_MEMPOST_LONG       (BPM_OCTEON_SPECIFIC | 0x040C) /* cmd_eeprom.c */
#define BPM_PMEMPOST_SHORT     (BPM_OCTEON_SPECIFIC | 0x020D) /* cmd_eeprom.c */
#define BPM_PMEMPOST_LONG      (BPM_OCTEON_SPECIFIC | 0x040E) /* cmd_eeprom.c */
#define BPM_PHYPOST_SHORT      (BPM_OCTEON_SPECIFIC | 0x010F) /* cmd_eeprom.c */
#define BPM_PHYPOST_LONG       (BPM_OCTEON_SPECIFIC | 0x0110) /* cmd_eeprom.c */
#define BPM_CSUMPOST_SHORT     (BPM_OCTEON_SPECIFIC | 0x0211) /* cmd_eeprom.c */
#define BPM_CSUMPOST_LONG      (BPM_OCTEON_SPECIFIC | 0x0412) /* cmd_eeprom.c */
#define BPM_CODE_RELOCATE      (BPM_OCTEON_SPECIFIC | 0x0113) /* board.c */
#define BPM_RAM_BASED_EXECUTE  (BPM_OCTEON_SPECIFIC | 0x0114) /* board.c */
#define BPM_CMD_TABLE_RELOC    (BPM_OCTEON_SPECIFIC | 0x0115) /* board.c */
#define BPM_FLASH_INIT         (BPM_OCTEON_SPECIFIC | 0x0116) /* board.c */
#define BPM_MALLOC_INIT        (BPM_OCTEON_SPECIFIC | 0x0117) /* board.c */
#define BPM_MALLOC_BIN_RELOC   (BPM_OCTEON_SPECIFIC | 0x0118) /* board.c */
#define BPM_ENV_RELOC          (BPM_OCTEON_SPECIFIC | 0x0119) /* board.c */ 
#define BPM_BACKPRESSURE_WA    (BPM_OCTEON_SPECIFIC | 0x011A) /* board.c */
#define BPM_L2_CACHE_F_UL      (BPM_OCTEON_SPECIFIC | 0x011B) /* board.c */
#define BPM_DRAM_CLEAR         (BPM_OCTEON_SPECIFIC | 0x011C) /* board.c */
#define BPM_PCI_INIT           (BPM_OCTEON_SPECIFIC | 0x011D) /* board.c */
#define BPM_ETHERNET_INIT      (BPM_OCTEON_SPECIFIC | 0x011E) /* board.c */
/* #define BPM_PRESTERA_INIT      (BPM_OCTEON_SPECIFIC | 0x011F) */
/* #define BPM_REDHAWK_INIT       (BPM_OCTEON_SPECIFIC | 0x0120) */
/* #define BPM_EAGLE_INIT         (BPM_OCTEON_SPECIFIC | 0x0121) */
/* #define BPM_PHYLINK_INIT       (BPM_OCTEON_SPECIFIC | 0x0122) */

#if 0
#define BPM_SPI0_INIT_DELAY    (BPM_OCTEON_SPECIFIC | 0x0123)
#define BPM_SPI0_INIT          (BPM_OCTEON_SPECIFIC | 0x0124)
#define BPM_PRI_PROC_INIT      (BPM_OCTEON_SPECIFIC | 0x0134)
#define BPM_SPI0_TSCLK_WAIT    (BPM_OCTEON_SPECIFIC | 0x0225)
#define BPM_SPI0_RSCLK_WAIT    (BPM_OCTEON_SPECIFIC | 0x0226)
#define BPM_SPI0_TRAINING_WAIT (BPM_OCTEON_SPECIFIC | 0x0227)
#define BPM_SPI0_CAL_SEND      (BPM_OCTEON_SPECIFIC | 0x0228)
#define BPM_SPI0_STAT_SYNC     (BPM_OCTEON_SPECIFIC | 0x0229)
#define BPM_SPI1_INIT_DELAY    (BPM_OCTEON_SPECIFIC | 0x012A)
#define BPM_SPI1_INIT          (BPM_OCTEON_SPECIFIC | 0x012B)
#define BPM_SPI1_TSCLK_WAIT    (BPM_OCTEON_SPECIFIC | 0x022C)
#define BPM_SPI1_RSCLK_WAIT    (BPM_OCTEON_SPECIFIC | 0x022D)
#define BPM_SPI1_TRAINING_WAIT (BPM_OCTEON_SPECIFIC | 0x022E)
#define BPM_SPI1_CAL_SEND      (BPM_OCTEON_SPECIFIC | 0x022F)
#define BPM_SPI1_STAT_SYNC     (BPM_OCTEON_SPECIFIC | 0x0230)
#endif /* if 0 */

#define BPM_VERSION_NUM_STORE  (BPM_OCTEON_SPECIFIC | 0x0131) /* octeon_tnpa56x4_board.c */

#define BPM_MAC_ADDR_UPDATE    (BPM_OCTEON_SPECIFIC | 0x0132) 

#define BOOT_PROGRESS_UPDATE(bpm)                                          \
    do                                                                     \
    {                                                                      \
        /* volatile int i; */                                               \
		                                                                   \
        *BOARD_LP_XMIT_MBOX    = 0x01; wmb();         /* Message type */   \
        *BOARD_LP_XMIT_MBOX    = (bpm >> 8); wmb();   /* Message byte 0 */ \
        *BOARD_LP_XMIT_MBOX    = (bpm & 0xff); wmb(); /* Message byte 1 */ \
        *BOARD_LP_XMIT_DBELL_0 = 3; wmb();            /* Message size   */ \
        *BOARD_LP_XMIT_DBELL_1 = 0x00; wmb();         /* Clear user bit */ \
    } while(0)



/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		( 8 * 1024)
#define CFG_ICACHE_SIZE		(32 * 1024)
#define CFG_CACHELINE_SIZE	128

/*-----------------------------------------------------------------------
 * BOARD ID Information
 */
#define DDR2_512MB          0x00
#define DDR2_1GB            0x01
#define DDR2_2GB            0x02
#define DDR2_4GB            0x03

#define EGRESS_IO_VIA_RTM   0x08

/*-----------------------------------------------------------------------
 * DRAM Module Organization
 *
 * Octeon can be configured to use two pairs of DIMM's, lower and
 * upper, providing a 128/144-bit interface or one to four DIMM's
 * providing a 64/72-bit interface.  This structure contains the TWSI
 * addresses used to access the DIMM's Serial Presence Detect (SPD)
 * EPROMS and it also implies which DIMM socket organization is used
 * on the board.  Software uses this to detect the presence of DIMM's
 * plugged into the sockets, compute the total memory capacity, and
 * configure DRAM controller.  All DIMM's must be identical.
 */

#include "octeon_tnpa5651x_shared.h"

#define DRAM_SOCKET_CONFIGURATION		OCTEON_TNPA5651X_DRAM_SOCKET_CONFIGURATION0
#define DRAM_SOCKET_CONFIGURATION_INTERFACE1	OCTEON_TNPA5651X_DRAM_SOCKET_CONFIGURATION1

#if 0  /* Example: Enable for designs that don't use DIMMs with SPD */
/*
** For memory configurations that don't incorporate Serial Presence
** Detect (SPD) the SPD EEPROM can be simulated using a static table
** in memory.  This capability is enabled by defining
** STATIC_DRAM_CONFIG_TABLE to point to the array that contains the
** simulated SPD data.  In this case the DRAM_SOCKET_CONFIGURATION
** table takes on a slightly different function.  Instead of providing
** the TWSII address of each SPD EEPROM a non-zero value indicates
** that the STATIC_DRAM_CONFIG_TABLE should be applied for that DIMM
** interface.  A zero value indicates that no DRAM is present on that
** DIMM interface.
*/
    #define STATIC_512MB_DRAM_CONFIG_TABLE static_512MB_ddr2_spd_data
    #define STATIC_1GB_DRAM_CONFIG_TABLE static_1GB_ddr2_spd_data
    #define STATIC_2GB_DRAM_CONFIG_TABLE static_2GB_ddr2_spd_data
    #define STATIC_4GB_DRAM_CONFIG_TABLE static_4GB_ddr2_spd_data
#endif


/* The following symbols define the default base MAC address if no
   MAC addresses are yet available in the appropriate locations. */
#define BASE_DEFAULT_MAC_ADRS_B5 0x00
#define BASE_DEFAULT_MAC_ADRS_B4 0xD0
#define BASE_DEFAULT_MAC_ADRS_B3 0x1C
#define BASE_DEFAULT_MAC_ADRS_B2 0x00
#define BASE_DEFAULT_MAC_ADRS_B1 0x00
#define BASE_DEFAULT_MAC_ADRS_B0 0x00

/* The following symbol defines the bits in the PHY control register
   that should be set before & after the PHY is initialized.  This
   value is used when POST tests are enabled. (not a very good test) */
#define PHY_CTRL_REG_TEST_MASK 0x2040 

#define MIN_H8_CLR_COUNT 5   /* min # of H8 "IN USE" flag cleared in a row */
#define MAX_H8_WAIT_TRYS 100 /* max loops for access to common i2c bus */

// ****************** this section will probably get removed since we will not be using the CF interface.

/* Octeon true IDE mode compact flash support.  True IDE mode is
** always 16 bit. */
//#define OCTEON_CF_TRUE_IDE_CS0_CHIP_SEL     5
//#define OCTEON_CF_TRUE_IDE_CS0_ADDR         0x1d040000
//#define OCTEON_CF_TRUE_IDE_CS1_CHIP_SEL     6
//#define OCTEON_CF_TRUE_IDE_CS1_ADDR         0x1d050000


/** Define the following symbol to include BIST in the Uboot code.
 **
 ** NOTE: If this symbol is not defined, BIST will still be compiled
 **       however, it will not be linked into the UBoot code.
 **/
#define INCLUDE_BIST

#endif	/* __CONFIG_H */
