/*
Copyright (C) 2008, 2009  GE Fanuc, Inc
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
*/

/*
 * This file contains the configuration parameters for the octeon simulator
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
#define CONFIG_OCTEON		1
#define CONFIG_OCTEON_38XX	1
/* CONFIG_OCTEON_TNPA3804 set by Makefile in include/config.h */

#if !defined(__U_BOOT_HOST__) && !defined(__BYTE_ORDER)
/* Set endian macros for simple exec includes, but not for host utilities */
#define __BYTE_ORDER __BIG_ENDIAN
#endif

/* Defaults to use if bootloader cannot autodetect settings */
#define DEFAULT_ECLK_FREQ_MHZ        500  /* Used if multiplier read fails, and for DRAM refresh rates */
/* Set this for 533 memory, as this config will work with 400 Mhz memory,
** albeit with poor performance.  This at least prevents a dead board.*/
#define TNPA3804_REV1_DEF_DRAM_FREQ  533

#define CONFIG_OCTEON_LLM_WORKAROUND
#define CONFIG_OCTEON_PCIX_WORKAROUND

/* Used to control conditional compilation for shared code between simple
** exec and u-boot */
#define CONFIG_OCTEON_U_BOOT

/* TNPA3804 uses configuration eeprom */
#define CONFIG_OCTEON_EEPROM_TUPLES     1

/* let the eth address be writeable */
#define CONFIG_ENV_OVERWRITE 1

/* bootloader usable memory size in bytes for tnpa3804, hard code until autodetect */
#define OCTEON_MEM_SIZE (1*1024*1024*1024ULL)

/* POST "no error" indication */
#define NO_POST_ERROR               0xFF
#define FLASH_CHECKSUM_ERROR        0x00
#define RAM_FAILURE                 0x01
#define PHY_FAILURE                 0x02
#define RLDRAM_FAILURE				0x04
#define INTERFACE0_DIMM_NOT_DETECTED  0x05
#define INTERFACE1_DIMM_NOT_DETECTED  0x06

#define PMEM_FAILURE                0x08
#define TLBMISS_EXCEPTION           0x20
#define XTLBMISS_EXCEPTION          0x21
#define CACHE_EXCEPTION             0x22
#define GENERAL1_EXCEPTION          0x23
#define GENERAL2_EXCEPTION          0x24
#define DEBUG_EXCEPTION             0x25
#define RESERVED_CODE_BASE          0x80

#define TLBMISS_ADDRESS             0x200
#define XTLBMISS_ADDRESS            0x280
#define CACHE_ADDRESS               0x300
#define GENERAL1_ADDRESS            0x380
#define GENERAL2_ADDRESS            0x400
#define DEBUG_ADDRESS               0x480

/* Addresses for various things on boot bus.  These addresses
** are used to configure the boot bus mappings. */

#define BOARD_BASE_FPGA_ADDR        0x16000000
#define BOARD_FPGA_CHIP_SEL         1

/* #define OCTEON_CF_ATTRIB_CHIP_SEL   2 */
/* #define OCTEON_CF_ATTRIB_BASE_ADDR  0x1d010000 */
/* #define OCTEON_CF_COMMON_CHIP_SEL   3 */
/* Address bit 11 selects common memory space for Compact flash accesses */
#define OCTEON_CF_COMMON_BASE_ADDR  (0x1d000000 | (1 << 11))
/* #define OCTEON_CHAR_LED_CHIP_SEL    4 */
/* #define OCTEON_CHAR_LED_BASE_ADDR   0x1d020000 */
/* #define OCTEON_PAL_CHIP_SEL         1 */
#define OCTEON_PAL_BASE_ADDR        0x1d030000

/* SPD EEPROM addresses on TNPA3804 board */
#define BOARD_MMC_RESERVED_START    0
#define BOARD_MMC_RESERVED_SIZE     (2 * 1024)
#define BOARD_POST_LOG_START        (BOARD_MMC_RESERVED_START + BOARD_MMC_RESERVED_SIZE)
#define BOARD_POST_LOG_SIZE         16
#define BOARD_EEPROM_UBOOT_START    (BOARD_POST_LOG_START + BOARD_POST_LOG_SIZE)

#define BOARD_DIMM_0_SPD_TWSI_ADDR  0x50
#define BOARD_DIMM_1_SPD_TWSI_ADDR  0x51

#define BOARD_EEPROM_TWSI_ADDR      0x52
#define BOARD_SFP0_TWSI_ADDR        0x53
#define BOARD_SFP1_TWSI_ADDR        0x54
#define BOARD_SFP2_TWSI_ADDR        0x55
#define BOARD_SFP3_TWSI_ADDR        0x56
#define BOARD_TEMP_SENSOR_TWSI_ADDR 0x57

#define BOARD_MCU_TWSI_ADDR         0x60

#define BOARD_TWSI_READY_WAIT       100000000
#define BOARD_TWSI_READ_CMD_WAIT    100000000
#define BOARD_TWSI_WRITE_CMD_WAIT   100000000
#define BOARD_ERROR_MAX_RETRIES     100000

/* FPGA Definitions - General */
#define BOARD_VERSION_ID_REG                  (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0000)
#define BOARD_ID_DIPSWITCH_REG                (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0001)
#define BOARD_LED_CONTROL_REG                 (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0002)
#define BOARD_INTERRUPT_CONTROL_REG           (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0003)
#define BOARD_INTERRUPT_STATUS_REG            (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0004)
#define BOARD_PAYLOAD_RESET_REG               (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0005)
#define BOARD_TX_CONTROL_REG                  (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0006)
/* FPGA Definitions - TWSI/I2C Register Addresses */
#define BOARD_TEMP_SENSOR_TWSI_CTRL_REG       (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0008)
#define BOARD_TEMP_SENSOR_TWSI_ADDR_UPPER_REG (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0009)
#define BOARD_TEMP_SENSOR_TWSI_ADDR_LOWER_REG (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000A)
#define BOARD_TEMP_SENSOR_TWSI_DATA_REG       (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000B)
#define BOARD_EEPROM_TWSI_CTRL_REG            (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000C)
#define BOARD_EEPROM_TWSI_ADDR_UPPER_REG      (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000D)
#define BOARD_EEPROM_TWSI_ADDR_LOWER_REG      (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000E)
#define BOARD_EEPROM_TWSI_DATA_REG            (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x000F)
#define BOARD_SFP3_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0010)
#define BOARD_SFP3_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0011)
#define BOARD_SFP3_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0012)
#define BOARD_SFP3_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0013)
#define BOARD_SFP2_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0014)
#define BOARD_SFP2_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0015)
#define BOARD_SFP2_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0016)
#define BOARD_SFP2_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0017)
#define BOARD_SFP1_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0018)
#define BOARD_SFP1_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x0019)
#define BOARD_SFP1_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001A)
#define BOARD_SFP1_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001B)
#define BOARD_SFP0_TWSI_CTRL_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001C)
#define BOARD_SFP0_TWSI_ADDR_UPPER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001D)
#define BOARD_SFP0_TWSI_ADDR_LOWER_REG        (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001E)
#define BOARD_SFP0_TWSI_DATA_REG              (uint8_t *)(BOARD_BASE_FPGA_ADDR+0x001F)

#define BOARD_TWSI_RUN_BIT                    0x80
#define BOARD_TWSI_ERROR_BIT                  0x40

#define BOARD_TWSI_RUN_READ_VAL               0x80
#define BOARD_TWSI_RUN_WRITE_VAL              0x81

#define BOARD_TXCR_CH0_EN                     0x01
#define BOARD_TXCR_CH1_EN                     0x02
#define BOARD_TXCR_CH2_EN                     0x04
#define BOARD_TXCR_CH3_EN                     0x08

#define BOARD_LED_GREEN                       0x08
#define BOARD_LED_YELLOW                      0x04

#define SWFB_COMMAND_MAX                      512

#define CFG_64BIT_VSPRINTF  1
#define CFG_64BIT_STRTOUL   1

/* Set bootdelay to 0 for immediate boot */
#define CONFIG_BOOTDELAY	0	/* autoboot after X seconds	*/

#define CONFIG_BAUDRATE		115200
#define CONFIG_DOWNLOAD_BAUDRATE		115200

/* valid baudrates */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
#undef	CONFIG_BOOTARGS


#define CFG_LOAD_ADDR       0x100000
#define CFG_BOOTOCT_ADDR    0x100000

#define CONFIG_MII

#define CFG_MAX_PROMPT_SIZE 50

/*
** Define CONFIG_PCI only if the system is known to provide a PCI
** clock to Octeon.  A bus error exception will occur if the inactive
** Octeon PCI core is accessed.  U-boot is not currently configured to
** recover when a exception occurs.
*/
#if CONFIG_OCTEON_PCI_UBOOT
#define CONFIG_PCI
#endif
/*-----------------------------------------------------------------------
 * PCI Configuration
 */
#if defined(CONFIG_PCI)

#define PCI_CONFIG_COMMANDS (CFG_CMD_PCI)

/*
** Define CONFIG_OCTEON_PCI_HOST = 1 to map the pci devices on the
** bus.  Define CONFIG_OCTEON_PCI_HOST = 0 for target mode when the
** host system performs the pci bus mapping instead.  Note that pci
** commands are enabled to allow access to configuration space for
** both modes.
*/
#ifndef CONFIG_OCTEON_PCI_HOST
#define CONFIG_OCTEON_PCI_HOST	0
#endif

#if (CONFIG_OCTEON_PCI_HOST)
#define CONFIG_PCI_PNP
#endif /* CONFIG_OCTEON_PCI_HOST */
#else  /* CONFIG_PCI */
#define PCI_CONFIG_COMMANDS (0)
#endif /* CONFIG_PCI */

/*
** The TNPA3804 does not use the internal arbiter in Octeon.
** Enable this for boards that do.
*/
#define USE_OCTEON_INTERNAL_ARBITER

/* Support for Intel 8254x gigabit chips. */
#define CONFIG_E1000

/* Define this to enable built-in octeon ethernet support */
#define OCTEON_RGMII_ENET
/* Define this to enable spi4000 support */
#define OCTEON_SPI4000_ENET

/* Enable Octeon built-in networking if either SPI or RGMII support is enabled */
#if defined(OCTEON_RGMII_ENET) || defined(OCTEON_SPI4000_ENET)
#define OCTEON_INTERNAL_ENET
#endif

/* Disable networking for failsafe builds.  Failsafe builds
** have size constraint of 192K that must be satisfied. */
#ifdef CONFIG_OCTEON_FAILSAFE
#undef OCTEON_RGMII_ENET
#undef OCTEON_SPI4000_ENET
#undef OCTEON_INTERNAL_ENET
#undef CONFIG_OCTEON_PCI_UBOOT
#undef CONFIG_OCTEON_PCI_HOST
#undef CONFIG_MII
#endif

#if CONFIG_OCTEON_PCI_HOST
#define EXTRA_INCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | PCI_CONFIG_COMMANDS )
#define EXTRA_EXCLUDE_COMMANDS   (0)
#elif CONFIG_OCTEON_FAILSAFE
#define EXTRA_INCLUDE_COMMANDS   (0)
#define EXTRA_EXCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | PCI_CONFIG_COMMANDS )
#elif  defined(OCTEON_INTERNAL_ENET)
#define EXTRA_INCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII)
#define EXTRA_EXCLUDE_COMMANDS   (0)
#else
#define EXTRA_INCLUDE_COMMANDS   (0)
#define EXTRA_EXCLUDE_COMMANDS   (CFG_CMD_NET | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | PCI_CONFIG_COMMANDS )
#endif

/*-----------------------------------------------------------------------
 * U-boot Commands Configuration
 */
/* Srecord loading seems to be busted - checking for ctrl-c eats bytes */
#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_OCTEON | CFG_CMD_LOADB | CFG_CMD_FLASH \
                                  | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_RUN | CFG_CMD_EEPROM \
                                  | EXTRA_INCLUDE_COMMANDS | CFG_CMD_ASKENV)\
                                  & ~(EXTRA_EXCLUDE_COMMANDS | CFG_CMD_FPGA | CFG_CMD_BDI \
                                   | CFG_CMD_BEDBUG | CFG_CMD_BOOTD | CFG_CMD_LOADS | CFG_CMD_NFS))
#include <cmd_confdefs.h>

/*-----------------------------------------------------------------------
 * Networking Configuration
 */
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#define CONFIG_NET_MULTI

#ifdef CONFIG_PCI_PNP
/*
** Enable PCI networking devices if PCI is auto configured by u-boot.
*/
#define CONFIG_NATSEMI
#endif /* CONFIG_PCI_PNP */

#define CONFIG_BOOTP_DEFAULT		(CONFIG_BOOTP_SUBNETMASK | \
					CONFIG_BOOTP_GATEWAY	 | \
					CONFIG_BOOTP_HOSTNAME	 | \
					CONFIG_BOOTP_BOOTPATH)

#define CONFIG_BOOTP_MASK		CONFIG_BOOTP_DEFAULT
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */


#define CONFIG_NET_RETRY_COUNT 5

#define CONFIG_AUTO_COMPLETE 1
#define CFG_CONSOLE_INFO_QUIET 1

#define CONFIG_DOS_PARTITION 1

#define CFG_IDE_MAXBUS 1
#define CFG_IDE_MAXDEVICE 1

#ifdef CFG_CMD_EEPROM
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_I2C_EEPROM_ADDR     BOARD_EEPROM_TWSI_ADDR
#endif

/* Base address of Common memory for Compact flash */
#define CFG_ATA_BASE_ADDR  OCTEON_CF_COMMON_BASE_ADDR

/* Offset from base at which data is repeated so that it can be
** read as a block */
#define CFG_ATA_DATA_OFFSET     0x400

/* Not sure what this does, probably offset from base
** of the command registers */
#define CFG_ATA_REG_OFFSET      0

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory      */
#ifdef CONFIG_OCTEON_FAILSAFE
#define	CFG_PROMPT		"Octeon tnpa3804 Failsafe bootloader# "	/* Monitor Command Prompt    */
#else
#if CONFIG_RAM_RESIDENT
#define	CFG_PROMPT		"Octeon tnpa3804(ram)# "	/* Monitor Command Prompt    */
#else
#define	CFG_PROMPT		"Octeon tnpa3804# "	/* Monitor Command Prompt    */
#endif
#endif
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
#define	CFG_MAXARGS		64		/* max number of command args*/

#define CFG_MALLOC_LEN		64*1024

#define CFG_BOOTPARAMS_LEN	16*1024

#define CFG_HZ			500000000ull      /* FIXME causes overflow in net.c */

#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */


#define CFG_MEMTEST_START	(CFG_SDRAM_BASE + 0x100000)
#define CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0xffffff)

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"bootloader_flash_update=protect off 0xbf460000 0xbf4fffff;erase 0xbf460000 0xbf4fffff;cp.b 0x7000000 0xbf460000 0x60000\0"	\
	"autoload=yes\0"							\
	"ethact=e1000#0\0"						\
	"swfb_cmd=bootoctlinux\0"				\
	"swfb_flash_addr=b7d80000\0"			\
	"swfb_ram_addr=2000000\0"				\
	"swfb_image_size=1800000\0"				\
	"swfb_cmd_arg=coremask=0fff\0"			\
	""

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CFG_FLASH_SIZE	(128*1024*1024)	/* Flash size (bytes) */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	(1024)	/* max number of sectors on one chip */

/* Remapped base of flash for entire flash access */
/* Without remapping there would be a 4Meg limit */
/* The entire flash size is subtacted to preserve pc continuity */
#define CFG_FLASH_BASE		(0xbfc00000 -  CFG_FLASH_SIZE)
#define CFG_FLASH_PROTECT_LEN   0x80000  /* protect low 512K */

/* The following #defines are needed to get flash environment right */
#define	CFG_MONITOR_BASE	TEXT_BASE
#define	CFG_MONITOR_LEN		(192 << 10)

#define CFG_INIT_SP_OFFSET	0x400000

#define CFG_FLASH_CFI   1
#define CFG_FLASH_CFI_DRIVER   1

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */

#if CONFIG_OCTEON_FAILSAFE || CONFIG_RAM_RESIDENT
#define	CFG_ENV_IS_NOWHERE	1
#else
#define	CFG_ENV_IS_IN_FLASH	1
#endif
#define CFG_UBOOT_SIZE                   (1536 * 1024) /* 1536 KBytes */
#define CFG_FLASH_SECTOR_SIZE            (128 * 1024) /* 128 KBytes */
/* PRE-CS0 remapping */
#define CFG_ENV_SIZE                     CFG_FLASH_SECTOR_SIZE
#define CFG_NFI_SIZE                     0
#define CFG_NFI_SECTOR                   0
#define CFG_NFI_FASTBOOT_KEY             0x0
#define CFG_FAILSAFE_BOOTLOADER_BASE  0xbfc00000
#define CFG_NORMAL_BOOTLOADER_BASE    (CFG_FAILSAFE_BOOTLOADER_BASE + CFG_UBOOT_SIZE)

#define CFG_IMAGE_SIZE_MAX               (CFG_UBOOT_SIZE - (CFG_ENV_SIZE + CFG_NFI_SIZE))

/* POST-CS0 remapping */
/* FLASH address map */
#define CFG_FS_BOOTLOADER_BASE        0xb7c00000
#define CFG_NORM_BOOTLOADER_BASE      (CFG_FS_BOOTLOADER_BASE + CFG_UBOOT_SIZE)
#define CFG_NFI_ADDR                     0 /* (CFG_FS_BOOTLOADER_BASE + (CFG_NFI_SECTOR * CFG_FLASH_SECTOR_SIZE)) */
#define CFG_NFI_FASTBOOT_KEY_ADDR        0 /* (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 8)) */
#define CFG_NFI_IMAGE_SIZE_ADDR          0 /* (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 16)) */
#define CFG_NFI_IMAGE_CHECKSUM_ADDR      0 /* (CFG_NFI_ADDR + (CFG_FLASH_SECTOR_SIZE - 24)) */

#if defined( UBOOT_LEGACY_NORMAL ) || defined( CONFIG_OCTEON_FAILSAFE )
#define CFG_ENV_ADDR                     ((CFG_FS_BOOTLOADER_BASE + CFG_UBOOT_SIZE)-\
										  (CFG_NFI_SIZE + CFG_ENV_SIZE))
#else
#define CFG_ENV_ADDR                     ((CFG_NORM_BOOTLOADER_BASE + CFG_UBOOT_SIZE)-\
										  (CFG_NFI_SIZE + CFG_ENV_SIZE))
#endif

#define CFG_IMAGE_NOT_PRESENT           0xFFFFFFFFFFFFFFFF
#define CFG_SWFB_BASE					(CFG_ENV_ADDR + CFG_ENV_SIZE)
#define CONFIG_FLASH_8BIT
#define CONFIG_NR_DRAM_BANKS			2
#define CONFIG_MEMSIZE_IN_BYTES

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		( 8 * 1024)
#define CFG_ICACHE_SIZE		(32 * 1024)
#define CFG_CACHELINE_SIZE	128

/*-----------------------------------------------------------------------
 * BOARD ID Information
 */
#define DDR2_512MB          0x00
#define DDR2_1GB            0x01
#define DDR2_2GB            0x02
#define DDR2_4GB            0x03

#define EGRESS_IO_VIA_RTM   0x08

/*-----------------------------------------------------------------------
 * DRAM Module Organization
 *
 * Octeon can be configured to use two pairs of DIMM's, lower and
 * upper, providing a 128/144-bit interface or one to four DIMM's
 * providing a 64/72-bit interface.  This structure contains the TWSI
 * addresses used to access the DIMM's Serial Presence Detect (SPD)
 * EPROMS and it also implies which DIMM socket organization is used
 * on the board.  Software uses this to detect the presence of DIMM's
 * plugged into the sockets, compute the total memory capacity, and
 * configure DRAM controller.  All DIMM's must be identical.
 */

#define DRAM_SOCKET_CONFIGURATION \
	{BOARD_DIMM_0_SPD_TWSI_ADDR, BOARD_DIMM_1_SPD_TWSI_ADDR}

#if 1  /* Example: Enable for designs that don't use DIMMs with SPD */
/*
** For memory configurations that don't incorporate Serial Presence
** Detect (SPD) the SPD EEPROM can be simulated using a static table
** in memory.  This capability is enabled by defining
** STATIC_DRAM_CONFIG_TABLE to point to the array that contains the
** simulated SPD data.  In this case the DRAM_SOCKET_CONFIGURATION
** table takes on a slightly different function.  Instead of providing
** the TWSII address of each SPD EEPROM a non-zero value indicates
** that the STATIC_DRAM_CONFIG_TABLE should be applied for that DIMM
** interface.  A zero value indicates that no DRAM is present on that
** DIMM interface.
*/
#define STATIC_512MB_DRAM_CONFIG_TABLE static_512MB_ddr2_spd_data
#define STATIC_1GB_DRAM_CONFIG_TABLE static_1GB_ddr2_spd_data
#define STATIC_2GB_DRAM_CONFIG_TABLE static_2GB_ddr2_spd_data
#define STATIC_4GB_DRAM_CONFIG_TABLE static_4GB_ddr2_spd_data
#endif

/* Board delay in picoseconds */
#define DDR_BOARD_DELAY		3500 /* ~2500 - ~4500 work so use 3500 */

#endif	/* __CONFIG_H */
