/**   pcie.h
 **
 **    This file contains supports the new pcie logic for the TNPA_5651x board.
 **
 ** Author: Ted Schmitz
 ** Date originally created: 9-30-2009
 **
 **/
#include "pci.h"

#define TABLE_TERM 0xFF           /* table termination value */
#define MAX_PCIE_DEV_NO 1         /* largest PCIE dev no supported */

/* config reg access type */
#define READ 0
#define WRITE 1

#define PCIE_PORT 1
#define PCIE_BUS 0
#define PCIE_DEV 0

/* size (in bytes) of conf access */
#define B1 1
#define B2 2
#define B4 4

/* Memory BAR and I/O BAR settings internal to 82571 */
#define MEM_BAR_ETH_0 0xF0000000
#define IO_BAR_ETH_0  0x00000001
#define REG_3C_ETH_0  0x0000002C
#define MEM_BAR_ETH_1 0xF0020000
#define IO_BAR_ETH_1  0x00000021
#define REG_3C_ETH_1  0x0000002D


struct pcie_config_reg_entry
  {
  int func;     /* which Ethernet device 0 or 1 */
  int reg;      /* which config reg to access */
  int size;     /* sixe of access, 1, 2, 4 for byte, short, word */
  int access;   /* type of access: read or write */
  uint32_t val; /* value written to conf reg on writes */
  };

extern void force_init_of_82571_config_regs(pci_dev_t devno);
extern void read_pcie_config_reg(int func, int reg, int size, uint32_t * val);
extern void write_pcie_config_reg(int func, int reg, int size, uint32_t val);
extern pci_dev_t pcie_find_next_device(struct pci_device_id *ids, int index);
