/*
Copyright (C) 2008, 2009  GE Intelligent Platforms, Inc
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
*/

/* rhAsicLib - RedHawk ASIC device driver library */

/*

DESCRIPTION:
    This driver library module provides routines for programming and
    monitoring RedHawk ASIC device. The functions in this library is
    grouped into following categories,
    \ss
        * Configuration Functions
        * Statistic Functions
        * MDIO Functions
        * Two Wire Serial Interface Functions
        * Memory Access Functions
        * Diagnostic Functions
        * Interrupt Handlers
        * DPG DPV Functions
    \se

INCLUDES:
    redHawkReg.h  rhAsicLib.h regif.h systypes.h osif.h

SEE ALSO:
    regIf

*/

#include <common.h>
#include <config.h>
#include <command.h>

#ifndef CONFIG_OCTEON_AT5810
#include "systypes.h"
#endif

#include "rhOsif.h"
#include "rhRegif.h"
#include "rhAsicReg.h"
#include "rhAsicLib.h"

/*
 * Function provided by the device driver or application
 * These functions implemented in the application main files
 * since these functions require header files which are not included in this
 * file.
 */
int check_default_flag = OK;
int syncStatusChangedThreadP0 = 0;
int syncStatusChangedThreadP1 = 0;
int mdioInterfaceBusy = 0;

/*************************************************************************
 *
 * RedHawk ASIC Configurations Functions
 *
 *************************************************************************/

/******************************************************************
* rhAsicXfiSpiConfig - Initializes RedHawk in XFI mode
*
* The routine initializes XFI and SPI interfaces of RedHawk for the respective
* port specified.
*
* RETURNS: None
*/
void rhAsicXfiSpiConfig (
     int port  /* port number */
     )
{
    /* Calling the rh_xfi_config function */
    rh_xfi_config(redHawkRegs, port, 0);

    /* IFH strip enable */
    regSet(redHawkRegs, CfgDeqHeaderStripControl, port, 1);

    /* Do not drop Abort EOP packets */
    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, port, 1);
}

/******************************************************************
* rhAsicXauiSpiConfig - Initializes RedHawk in XAUI mode
*
* The routine initializes XAUI and SPI interfaces of RedHawk for the respective
* port specified.
*
* RETURNS: None
*/
void rhAsicXauiSpiConfig (
     int port  /* port number */
     )
{
    /* Calling the rh_xaui_config function */
    rh_xaui_config(redHawkRegs, port, 0);

    /* IFH strip enable */
    regSet(redHawkRegs, CfgDeqHeaderStripControl, port, 1);

    /* Do not drop Abort EOP packets */
    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, port, 1);

    /* Enable SPI stuff */
    regSet(redHawkRegs, CfgRegRxpSpiSetup__EnableStatus, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__EnableTraining, 0, 1);
    regSet(redHawkRegs, CfgRegTSpiSetup__EnableTraining, 0, 1);
    regSet(redHawkRegs, CfgRegCoLoopbackMode__PSpiRx2TxLpbk, 0, 0); /* Disable internal loopback */
    regSet(redHawkRegs, CfgRegTSpiSetup__EnableDeskew, 0, 1);

    /* Enable Sync Detect */
    regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfgensyncdet_D_xaui0, 0, 1);
    regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfgensyncdet_C_xaui0, 0, 1);
    regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfgensyncdet_B_xaui0, 0, 1);
    regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfgensyncdet_A_xaui0, 0, 1);

}

/******************************************************************
* rhAsicXfiSpi2To1Config - Initializes RedHawk in XFI - SPI 2:1 Oversubscription mode
*
* The routine initializes RedHawk in 2:1 oversubscription mode.
*
* RETURNS: None
*/
void rhAsicXfiSpi2To1Config ()
{
    /* Calling the rh_xfi_config function */
    rh_xfi_config(redHawkRegs, 0, 0);
    rh_xfi_config(redHawkRegs, 1, 0);
    regSet(redHawkRegs, CfgRegCoOversubscriptionMode__Mode2_1, 0, 1);

    /* XAUI, FCRAM and Secondary SPI Powerdown */
    rhAsicXAUIPowerdown(0);
    rhAsicXAUIPowerdown(1);
    rhAsicFCRAMPowerdown (0);
    rhAsicFCRAMPowerdown (1);
    rhAsicSPIPowerdown(1);
}

/******************************************************************
* rhAsic2To1Config - Initializes RedHawk in 2:1 Oversubscription mode
*
* The routine initializes RedHawk in 2:1 oversubscription mode according to
* the specified port and loopback settings.
*
* RETURNS: None
*/
void rhAsic2To1Config (
     int port0,     /* Port 0: XFI - 0/XAUI - 1*/
     int port1,     /* Port 1: XFI - 0/XAUI - 1*/
     int lb_mode    /* Loopback Mode : Internal - 0/External - 1*/
     )
{
    unsigned int regVal;

    /* Calling the configuration functions according to the ports specified */
    if (port0 == 0) {
        rh_xfi_config(redHawkRegs, 0, 0);
        regSet(redHawkRegs, CfgRxControl__rxeq, 0, 0x7);
        regSet(redHawkRegs, CfgRxControl__rxphase, 0, 0x17);
    } else {
        rh_xaui_config(redHawkRegs, 0, 0);
    }

    if (port1 == 0) {
        rh_xfi_config(redHawkRegs, 1, 0);
        regSet(redHawkRegs, CfgRxControl__rxeq, 1, 0x7);
        regSet(redHawkRegs, CfgRxControl__rxphase, 1, 0x17);
    } else {
        rh_xaui_config(redHawkRegs, 1, 0);
    }

    /* IFH strip enable */
    regSet(redHawkRegs, CfgDeqHeaderStripControl, 0, 1);
    regSet(redHawkRegs, CfgDeqHeaderStripControl, 1, 1);

    /* Do not drop Abort EOP packets */
    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 0, 1);
    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 1, 1);

    /* Setting the Over subscription Mode */
    regSet(redHawkRegs, CfgRegCoOversubscriptionMode, 0, 2);

    /* Setting the CalL and CalM values */
    regGet(redHawkRegs, VarRegCoFunctionActivate0, 0, &regVal);
    regVal = regVal & ~BIT_4 & ~BIT_2;
    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, regVal);
    regSet(redHawkRegs, CfgRegTSpiCalSetup, 0, 0x43);
    regSet(redHawkRegs, CfgRegRxpSpiCalSetup, 0, 0x43);
    regGet(redHawkRegs, VarRegCoFunctionActivate0, 0, &regVal);
    regVal = regVal | BIT_4 | BIT_2;
    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, regVal);

    /* Complete Power down of XAUI and XFI modules accordingly */
    if (port0 == 0)
        rhAsicXAUIPowerdown(0);
    else
        rhAsicXFIPowerdown(0);
    if (port1 == 0)
        rhAsicXAUIPowerdown(1);
    else
        rhAsicXFIPowerdown(1);
    /* FCRAM Powerdown */
    rhAsicFCRAMPowerdown(0);
    rhAsicFCRAMPowerdown(1);
    /* Secondary SPI Powerdown */
    rhAsicSPIPowerdown(1);

    /* Configure the loopback according to the user specified value */
    regSet(redHawkRegs, CfgRegRxpSpiSetup__EnableStatus, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__EnableTraining, 0, 1);
    regSet(redHawkRegs, CfgRegTSpiSetup__EnableTraining, 0, 1);
    if (lb_mode == 0) {
        regSet(redHawkRegs, CfgRegCoLoopbackMode__PSpiRx2TxLpbk, 0, 1); /* Enable internal loopback */
        regSet(redHawkRegs, CfgRegTSpiSetup__EnableDeskew, 0, 0);
    } else {
        regSet(redHawkRegs, CfgRegCoLoopbackMode__PSpiRx2TxLpbk, 0, 0); /* Disable internal loopback */
        regSet(redHawkRegs, CfgRegTSpiSetup__EnableDeskew, 0, 1);
    }
}

/******************************************************************
* rhAsicPrimary4to1Config - Initializes Primary RedHawk in XFI - SPI 4:1 Oversubscription mode
*
* The routine initializes Primary RedHawk in 4:1 oversubscription mode.
*
* RETURNS: None
*/
void rhAsicPrimary4to1Config (void)
{
    regSet(redHawkRegs, CfgRegCoRxsSpiHMPLLReg__rx_fbclk_sel, 0, 0x1);

    rh_xfi_config(redHawkRegs, 0, 0);
    regSet(redHawkRegs, CfgRxControl__rxeq, 0, 0x7);
    regSet(redHawkRegs, CfgRxControl__rxphase, 0, 0x17);

    rh_xfi_config(redHawkRegs, 1, 0);
    regSet(redHawkRegs, CfgRxControl__rxeq, 0, 0x7);
    regSet(redHawkRegs, CfgRxControl__rxphase, 0, 0x17);

    /* IFH strip enable */
    regSet(redHawkRegs, CfgDeqHeaderStripControl, 0, 1);
    regSet(redHawkRegs, CfgDeqHeaderStripControl, 1, 1);

    /* Do not drop Abort EOP packets */
    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 0, 1);
    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 1, 1);

    regSet(redHawkRegs, CfgRegCoOversubscriptionMode, 0, 4);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__MDRRDis, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__BandWidthMeterDis, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri1, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri1, 1, 1);
    regSet(redHawkRegs, CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri2, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri2, 1, 1);
    regSet(redHawkRegs, CfgRegRxpSpiCascadePortMaxBurst__MaxBurstPri1, 0, 15);
    regSet(redHawkRegs, CfgRegRxpSpiCascadePortMaxBurst__MaxBurstPri1, 1, 15);
    regSet(redHawkRegs, CfgRegRxpSpiCascadePortMaxBurst__MaxBurstPri2, 0, 15);
    regSet(redHawkRegs, CfgRegRxpSpiCascadePortMaxBurst__MaxBurstPri2, 1, 15);

    regSet(redHawkRegs, CfgRegTSpiSetup__EnableTraining, 0, 1);
    regSet(redHawkRegs, CfgRegTxSSpiSetup__EnableTraining, 0, 1);

    /* The following is to map the PriTSPi Maintanance channel */
    /* to some portId that does not exist */
    regSet(redHawkRegs, CfgRegTSpiFifoId2, 0, 40);
    regSet(redHawkRegs, CfgRegCoLoopbackMode__PSpiRx2TxLpbk, 0, 0);
    regSet(redHawkRegs, CfgRegCoSpiSetup__PSpiStatusSpeed, 0, 0);
    regSet(redHawkRegs, CfgRegCoSpiSetup__CfgSecTSClkFlip, 0, 1);

    /* When hooked up to EzChip execute the following 2 commands */
    regSet(redHawkRegs, CfgRegCoSpiSetup__PSpiStatusSpeed125, 0, 1);
    regSet(redHawkRegs, CfgRegCoSpiSetup__CfgPriTSClkFlip, 0, 1);

    /* 0- localPort0 */
    /* 1- localport1 */
    /* 2- cascadeport0 */
    /* 3- cascadeport1 */
    /* 4- localmaintanance port */
    regSet(redHawkRegs, CfgRegRxpSpiAddressMap, 0, 0);
    regSet(redHawkRegs, CfgRegRxpSpiAddressMap, 1, 1);
    regSet(redHawkRegs, CfgRegRxpSpiAddressMap, 2, 2);
    regSet(redHawkRegs, CfgRegRxpSpiAddressMap, 3, 3);
    regSet(redHawkRegs, CfgRegRxpSpiAddressMap, 4, 4);
    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdc3);

    /* Pri RSPI Calendar map */
    regSet(redHawkRegs, CfgRegRxpSpiCalSetup__CalL, 0, 4);
    regSet(redHawkRegs, CfgRegRxpSpiCalSetup__CalM, 0, 2);
    regSet(redHawkRegs, CfgMemRxpSpiCalPri, 0, 0);
    regSet(redHawkRegs, CfgMemRxpSpiCalPri, 1, 1);
    regSet(redHawkRegs, CfgMemRxpSpiCalPri, 2, 2);
    regSet(redHawkRegs, CfgMemRxpSpiCalPri, 3, 3);

    /* Sec RSPI Calendar map */
    regSet(redHawkRegs, CfgRegRxsSpiCalSetup__CalL, 0, 4);
    regSet(redHawkRegs, CfgRegRxsSpiCalSetup__CalM, 0, 2);
    regSet(redHawkRegs, CfgMemRxsSpiCalPri, 0, 0);
    regSet(redHawkRegs, CfgMemRxsSpiCalPri, 1, 1);
    regSet(redHawkRegs, CfgMemRxsSpiCalPri, 2, 0);
    regSet(redHawkRegs, CfgMemRxsSpiCalPri, 3, 1);

    /* Pri TSPI Calendar map */
    regSet(redHawkRegs, CfgRegTSpiCalSetup__CalL, 0, 4);
    regSet(redHawkRegs, CfgRegTSpiCalSetup__CalM, 0, 2);

    /* For PriTSPI in cascade mode Fifo0,1,2 are local fifos */
    /* AllFifo IDs > 3 are cascade port IDs for which the status */
    /* is obtained from the Secondary RStat bus and merged in here */
    regSet(redHawkRegs, CfgMemTSpiCal, 0, 0);
    regSet(redHawkRegs, CfgMemTSpiCal, 1, 1);
    regSet(redHawkRegs, CfgMemTSpiCal, 2, 3);
    regSet(redHawkRegs, CfgMemTSpiCal, 3, 4);

    /* Sec TSPI Calendar map */
    regSet(redHawkRegs, CfgRegTxSSpiCalSetup__CalL, 0, 4);
    regSet(redHawkRegs, CfgRegTxSSpiCalSetup__CalM, 0, 2);
    regSet(redHawkRegs, CfgMemTxSSpiCal, 0, 0);
    regSet(redHawkRegs, CfgMemTxSSpiCal, 1, 1);
    regSet(redHawkRegs, CfgMemTxSSpiCal, 2, 0);
    regSet(redHawkRegs, CfgMemTxSSpiCal, 3, 1);

    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdff);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__DisAbortInsonLOS, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__EnableStatus, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__EnableTraining, 0, 1);

    regSet(redHawkRegs, CfgRegRxsSpiSetup__EnableStatus, 0, 1);
    regSet(redHawkRegs, CfgRegRxsSpiSetup__EnableTraining, 0, 1);

    regSet(redHawkRegs, CfgRegTSpiSetup__EnableDeskew, 0, 1);
    regSet(redHawkRegs, CfgRegTSpiSetup__EnableTraining, 0, 1);

    regSet(redHawkRegs, CfgRegTxSSpiSetup__EnableDeskew, 0, 1);
    regSet(redHawkRegs, CfgRegTxSSpiSetup__EnableTraining, 0, 1);

    regSet(redHawkRegs, CfgDeqHeaderStripControl, 0, 0x00000001);
    regSet(redHawkRegs, CfgDeqHeaderStripControl, 1, 0x00000001);

    regSet(redHawkRegs, CfgRegTxMACModes, 0, 0x0000000a);
    regSet(redHawkRegs, CfgRegRxMACModes, 0, 0x00d05e37);

    regSet(redHawkRegs, CfgRegTxMACModes, 1, 0x0000000a);
    regSet(redHawkRegs, CfgRegRxMACModes, 1, 0x00d05e37);

    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 0, 1);
    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 1, 1);

    /* Just Clear the LOS coundition caused during init routine */
    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdc3);
    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdff);
    regSet(redHawkRegs, CfgRegCoDiagSel, 0, 1);

    /* Need this for the WAN card (can be removed later) */
    regSet(redHawkRegs, CfgMiscFullPacketMode0, 0, 1);
    regSet(redHawkRegs, CfgMiscFullPacketMode1, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__PacketMode, 0, 1);
    regSet(redHawkRegs, CfgRegTxSSpiThr__MTUHungryThr, 0, 0x130);
    regSet(redHawkRegs, CfgRegTxSSpiThr__MTUStarvingThr, 0, 0x130);

    /* XAUI, FCRAM and Secondary SPI Powerdown */
    rhAsicXAUIPowerdown(0);
    rhAsicXAUIPowerdown(1);
    rhAsicFCRAMPowerdown (0);
    rhAsicFCRAMPowerdown (1);
}

/******************************************************************
* rhAsicCascade4to1Config - Initializes Cascaded RedHawk in XFI - SPI 2:1 Oversubscription mode
*
* The routine initializes Secondary(cascaded) RedHawk in 2:1 oversubscription mode.
*
* RETURNS: None
*/
void rhAsicCascade4to1Config (void)
{
    /* Calling rh_xfi_config initialization functions for XFI port 0 */
    rh_xfi_config(redHawkRegs, 0, 0);
    regSet(redHawkRegs, CfgRxControl__rxeq, 0, 0x7);
    regSet(redHawkRegs, CfgRxControl__rxphase, 0, 0x17);

    /* Calling rh_xfi_config initialization functions for XFI port 0 */
    rh_xfi_config(redHawkRegs, 1, 0);
    regSet(redHawkRegs, CfgRxControl__rxeq, 1, 0x7);
    regSet(redHawkRegs, CfgRxControl__rxphase, 1, 0x17);

    /* IFH strip enable */
    regSet(redHawkRegs, CfgDeqHeaderStripControl, 0, 1);
    regSet(redHawkRegs, CfgDeqHeaderStripControl, 1, 1);

    /* Do not drop Abort EOP packets */
    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 0, 1);
    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 1, 1);

    regSet(redHawkRegs, CfgRegCoOversubscriptionMode, 0, 2);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__MDRRDis, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__BandWidthMeterDis, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri1, 0, 15);
    regSet(redHawkRegs, CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri1, 1, 15);
    regSet(redHawkRegs, CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri2, 0, 15);
    regSet(redHawkRegs, CfgRegRxpSpiLocalPortMaxBurst__MaxBurstPri2, 1, 15);

    /* Enable the following sending traffic to the Pri board */
    regSet(redHawkRegs, CfgRegTSpiFifoId0, 0, 2 );
    regSet(redHawkRegs, CfgRegTSpiFifoId1, 0, 3 );
    regSet(redHawkRegs, CfgRegTSpiFifoId2, 0, 41);
    regSet(redHawkRegs, CfgRegCoSpiSetup__PSpiStatusSpeed125, 0, 1);
    regSet(redHawkRegs, CfgRegCoSpiSetup__PSpiStatusSpeed, 0, 0);
    regSet(redHawkRegs, CfgRegCoSpiSetup__CfgPriTSClkFlip, 0, 1);

    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdc3);

    /* Pri RSPI Calendar map */
    regSet(redHawkRegs, CfgRegRxpSpiCalSetup__CalL, 0, 4);
    regSet(redHawkRegs, CfgRegRxpSpiCalSetup__CalM, 0, 2);
    regSet(redHawkRegs, CfgMemRxpSpiCalPri, 0, 0);
    regSet(redHawkRegs, CfgMemRxpSpiCalPri, 1, 1);
    regSet(redHawkRegs, CfgMemRxpSpiCalPri, 2, 0);
    regSet(redHawkRegs, CfgMemRxpSpiCalPri, 3, 1);

    /* Pri TSPI Calendar map */
    regSet(redHawkRegs, CfgRegTSpiCalSetup__CalL, 0, 4);
    regSet(redHawkRegs, CfgRegTSpiCalSetup__CalM, 0, 2);
    regSet(redHawkRegs, CfgMemTSpiCal, 0, 0);
    regSet(redHawkRegs, CfgMemTSpiCal, 1, 1);
    regSet(redHawkRegs, CfgMemTSpiCal, 2, 0);
    regSet(redHawkRegs, CfgMemTSpiCal, 3, 1);

    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdff);

    regSet(redHawkRegs, CfgRegRxpSpiSetup__EnableStatus, 0, 1);
    regSet(redHawkRegs, CfgRegRxpSpiSetup__EnableTraining, 0, 1);

    regSet(redHawkRegs, CfgRegTSpiSetup__EnableDeskew, 0, 1);
    regSet(redHawkRegs, CfgRegTSpiSetup__EnableTraining, 0, 1);

    regSet(redHawkRegs, CfgDeqHeaderStripControl, 0, 0x00000001);
    regSet(redHawkRegs, CfgDeqHeaderStripControl, 1, 0x00000001);

    regSet(redHawkRegs, CfgRegTxMACModes, 0, 0x0000000a);
    regSet(redHawkRegs, CfgRegRxMACModes, 0, 0x00d05e37);

    regSet(redHawkRegs, CfgRegTxMACModes, 1, 0x0000000a);
    regSet(redHawkRegs, CfgRegRxMACModes, 1, 0x00d05e37);

    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 0, 1);
    regSet(redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 1, 1);

    /* Just Clear the LOS coundition caused during init routine */
    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdc3);
    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdff);
    regSet(redHawkRegs, CfgRegCoDiagSel, 0, 1 );

    /* XAUI, FCRAM and Secondary SPI Powerdown */
    rhAsicXAUIPowerdown(0);
    rhAsicXAUIPowerdown(1);
    rhAsicFCRAMPowerdown (0);
    rhAsicFCRAMPowerdown (1);
    rhAsicSPIPowerdown(1);
}

#ifdef CONFIG_OCTEON_AT5810
void rhReset (reginfo_t *regdb)
{
    unsigned int regVal;

    /* Soft Reset */
    regSet( regdb, VarRegCoGlobalSoftReset, 0, 1 );
    udelay(100*1000); /* 100 [ms] */
    regGet (regdb, CfgRegCoSpiSetup, 0, &regVal);
    regVal &= ~BIT_8;  /* disable the secondary rx SPI */
    regVal |= BIT_9;   /* power down the secondary rx SPI */
    regVal &= ~BIT_10; /* disable the secondary tx SPI */
    regVal |= BIT_11;  /* power down the secondary tx SPI */
    regVal |= BIT_20;  /* status clock is 1/8 of PSPI_RDCLK */
    regSet( regdb, CfgRegCoSpiSetup, 0, regVal );
}

void rhPllCheck (reginfo_t *regdb, int pllLockBit, int pllEnaBit, char *outMess, int port)
{
    unsigned int regVal, attempts = 0;

    /* check TxPLL Lock Detect */
    regGet( regdb, StsRpSpiPLLLockDet, 0, &regVal );
    if ((regVal & pllLockBit) == 0)
    {
        printf(outMess, port);
        while (1)
        {
            if (attempts++ > 10)
            {
                printf(" failed\n");
                break;
            }
            printf(".");
            /* disable the Primary TxPLL */
            regGet (regdb, CfgRegCoSpiSetup, 0, &regVal);
            regVal &= ~pllEnaBit;  /* disable the Primary TxPLL */
            regSet( regdb, CfgRegCoSpiSetup, 0, regVal );
            udelay(100 * 1000); /* 100[ms] */
            regGet (regdb, CfgRegCoSpiSetup, 0, &regVal);
            regVal |= pllEnaBit;  /* enable the Primary TxPLL */
            regSet( regdb, CfgRegCoSpiSetup, 0, regVal );
            udelay(100 * 1000); /* 100[ms] */
            /* check TxPLL Lock Detect */
            regGet( regdb, StsRpSpiPLLLockDet, 0, &regVal );
            if ((regVal & pllLockBit) != 0)
            {
                printf(" done\n");
                break;
            }
        }
    }
}

#endif

/* Configures the COMMON slave registers */
void rhCommonInit (reginfo_t *regdb, int port)
{
	unsigned int regVal, Activate0, Activate1;

    /* Disabling all the modules initially w.r.t port */
    regGet( regdb, VarRegCoFunctionActivate0, 0, &Activate0 );
    regGet( regdb, VarRegCoFunctionActivate1, 0, &Activate1 );
    regVal = 0;

    if (port == 1) {
            regVal = regVal | BIT_31  | BIT_30 | BIT_29 \
                     | BIT_28 | BIT_27 | BIT_26 | BIT_25 \
                     | BIT_24 | BIT_23 | BIT_22 | BIT_21 \
                     | BIT_20 | BIT_19 | BIT_5  | BIT_3 ;

            Activate0 = Activate0 & (~regVal);
            regVal = 0;
            regVal = regVal | BIT_15 | BIT_13 | BIT_12 \
                     | BIT_9 | BIT_7  | BIT_6  | BIT_5 \
                     | BIT_1 ;

            Activate1 = Activate1 & (~regVal);
   } else {
            regVal =   regVal | BIT_18 | BIT_17 | BIT_16 \
                     | BIT_15 | BIT_14 | BIT_13 | BIT_12 \
                     | BIT_11 | BIT_10 | BIT_9  | BIT_8  \
                     | BIT_7  | BIT_6  | BIT_4  | BIT_2;

            Activate0 = Activate0 & (~regVal);
            regVal = 0;
            regVal =   regVal | BIT_14 | BIT_11 | BIT_10 \
                     | BIT_8  | BIT_4  | BIT_3  | BIT_2 \
                     | BIT_0 ;
            Activate1 = Activate1 & (~regVal);
    }
    regSet ( regdb, VarRegCoFunctionActivate0, 0, Activate0);
    regSet ( regdb, VarRegCoFunctionActivate1, 0, Activate1);

    /* Bring the CORE PLL out of Reset */
    regSet( regdb, CfgRegCoFCPLLConfig, 0, 0x0000003d );

    /* Waiting for FC PLL Lock... */
    regVal = 0;
    while (regVal != 0x00000001) {
        regGet( regdb, StsRegCoFCPLLLock, 0, &regVal );
        regVal = regVal & 0x00000001;
    }

    /* Set NODIV=1 and HREF=0 for the TxPLL (recommendation from LSI)
       to avoid spurious PLL LockDet */
    if (port == 0) {
        regSet (regdb, CfgRegCoTxPSpiHMPLLReg, 0, 0x13b38c);
    } else {
        regSet (regdb, CfgRegCoTxSSpiHMPLLReg, 0, 0x13b38c);
    }

    /* Toggle NPSI Core Enable bit's */
    regGet (regdb, CfgRegCoSpiSetup, 0, &regVal);
    if (port == 0) {
        regVal = regVal | BIT_12;
        regSet( regdb, CfgRegCoSpiSetup, 0, regVal );
        regVal = regVal & ~BIT_12;
        regSet( regdb, CfgRegCoSpiSetup, 0, regVal );
    } else {
        regVal = regVal | BIT_16;
        regSet( regdb, CfgRegCoSpiSetup, 0, regVal );
        regVal = regVal & ~BIT_16;
        regSet( regdb, CfgRegCoSpiSetup, 0, regVal );
    }

    /* Slow down the LED Clock */
    if (port == 0) {
        regSet( regdb, CfgRegCoClockDiv1__LEDClk0, 0, 0x29);
    } else {
        regSet( regdb, CfgRegCoClockDiv1__LEDClk1, 0, 0x29);
    }

    /* Enabling CPU slaves */
    regGet( regdb, CfgRegCoMisc, 0, &regVal );
    regVal = regVal | 0x00010000;
    regSet( regdb, CfgRegCoMisc, 0, regVal );

#ifdef CONFIG_OCTEON_AT5810
    {
        char *s;
        int hyperPhyTimeout;

        /* check PLL Lock detect */
        if (port == 0)
        {
            /* check TxPLL Lock Detect */
            rhPllCheck (regdb, BIT_0, BIT_6, "Re-enabling Redhawk Port-%d TxPLL for lock", port);
            /* check RxPLL Lock Detect */
            rhPllCheck (regdb, BIT_1, BIT_4, "Re-enabling Redhawk Port-%d RxPLL for lock", port);
        }
        else
        {
            /* check TxPLL Lock Detect */
            rhPllCheck (regdb, BIT_0, BIT_10, "Re-enabling Redhawk Port-%d TxPLL for lock", port);
            /* check RxPLL Lock Detect */
            rhPllCheck (regdb, BIT_1, BIT_8, "Re-enabling Redhawk Port-%d RxPLL for lock", port);
        }
        /* check for Hyper PHY detect */
        if (port == 0)
        {
            s = getenv("rhhphy0to");
        }
        else
        {
            s = getenv("rhhphy1to");
        }
        if (s != NULL)
        {
            hyperPhyTimeout = simple_strtoul(s, NULL, 10);
            if ((hyperPhyTimeout <= 0) || (hyperPhyTimeout > 3))
            {
                hyperPhyTimeout = 1;
            }
            if (port == 0)
            {
                /* Pri SPI */
                regSet (regdb, CfgRegCoDiagSel, 0, 0x020);
            }
		    else
            {
                /* Sec SPI */
                regSet (regdb, CfgRegCoDiagSel, 0, 0x054);
            }
            printf("Redhawk Hyper-PHY Port-%d PLL-Lock check", port);
            while (1)
            {
                printf(".");
                regGet( regdb, StsRegCoDiagData, 0, &regVal );
                regVal = regVal & 0x0000000B;
                if (regVal == 0x0000000A)
                {
                    printf(" done\n");
                    break;
                }
                if (hyperPhyTimeout-- == 0)
                {
                    printf(" failed\n");
                    break;
                }
                udelay(1000*1000); /* 1 second */
            }
        }
    }
#else
    /* Wait for HyperPhy PLL lock
       bit[3]  = TxPLL Lock Det;  bit[1] = RxPLL Lock Det; bit[0]  = NSPI Reset Out
     */
    if (port == 0) {                                          /* Pri SPI */
        regSet (regdb, CfgRegCoDiagSel, 0, 0x020);
        regVal = 0x1;
        while (regVal != 0x0000000A) {
            regGet( regdb, StsRegCoDiagData, 0, &regVal );
            regVal = regVal & 0x0000000B;
        }
    } else {                                                   /* Sec SPI */
        regSet (regdb, CfgRegCoDiagSel, 0, 0x054);
        regVal = 0x1;
        while (regVal != 0x0000000A) {
            regGet( regdb, StsRegCoDiagData, 0, &regVal );
            regVal = regVal & 0x0000000B;
        }
    }
#endif

}

/* Initializes the XFI module */
int rhRxXfiInit (reginfo_t *regdb, int port)
{
    unsigned int regVal;

    if (port == 0) {
        /* XFI Lock to Reference Clock */
        regSet( regdb, CfgRegCoXFISetup__Cfgrxlockref_xfi0, 0, 1 );

        /* Configure the Line Interface Mode for XFI */
        regGet( regdb, CfgRegCoLineInterfaceMode, 0, &regVal );
        regVal = regVal | BIT_0;
        regVal = regVal & ~BIT_1;
        regSet( regdb, CfgRegCoLineInterfaceMode, 0, regVal );
    } else {
        /* XFI Lock to Reference Clock */
        regSet( regdb, CfgRegCoXFISetup__Cfgrxlockref_xfi1, 0, 1);

        /* Configure the Line Interface Mode for XFI */
        regGet( regdb, CfgRegCoLineInterfaceMode, 0, &regVal );
        regVal = regVal | BIT_2;
        regVal = regVal & ~BIT_3;
        regSet( regdb, CfgRegCoLineInterfaceMode, 0, regVal );
    }

    regVal = 0;
    regGet( regdb, CfgRxControl, port, &regVal);
    regVal = regVal | BIT_5; /* Rx PLL Cal */
    regVal = regVal | BIT_17 | BIT_18; /* Rx PLL Loop dynamic */
    regVal = regVal & ~BIT_19; /* Rx PLL Loop dynamic */
    regVal = regVal & ~BIT_20; /* Rx PLL Loop dynamic */
    regSet( regdb, CfgRxControl, port, regVal );

    /* Waiting for the Rx Lock Detect */
    regVal = 0;
    while (regVal != 0x10) {
        regGet( regdb, CfgRxControl, port, &regVal );
        regVal = regVal & 0x10;
        osDelay (10);
    }

    /* Enable the Rx logic of XFI core */
    regGet( regdb, VarRegCoFunctionActivate1, 0, &regVal );
    if (port == 0)
        regVal = regVal | BIT_2;
    else
        regVal = regVal | BIT_5;
    regSet( regdb, VarRegCoFunctionActivate1, 0, regVal );

    regSet( regdb, CfgRxControl, port, 0x400712b0 );
    regSet( regdb, CfgStatusControl, port, 0x20000090 );

    /* XFI Lock to Data */
    if (port == 0)
        regSet( regdb, CfgRegCoXFISetup__Cfgrxlockref_xfi0, 0, 0 );
    else
        regSet( regdb, CfgRegCoXFISetup__Cfgrxlockref_xfi1, 0, 0 );

    /* Enable Rx Port Interface */
    regGet( regdb, VarRegCoFunctionActivate1, 0, &regVal );
    if (port == 0)
        regVal = regVal | BIT_10;
    else
        regVal = regVal | BIT_12;
    regSet( regdb, VarRegCoFunctionActivate1, 0, regVal );

    return OK;
}

/* Initializes the XFI module */
int rhXfiInit (reginfo_t *regdb, int port)
{
    unsigned int regVal;
    int i;

    if (port == 0) {
        /* XFI Lock to Reference Clock */
        regSet( regdb, CfgRegCoXFISetup__Cfgrxlockref_xfi0, 0, 1 );

        /* Configure the Line Interface Mode for XFI */
        regGet( regdb, CfgRegCoLineInterfaceMode, 0, &regVal );
        regVal = regVal | BIT_0;
        regVal = regVal & ~BIT_1;
        regSet( regdb, CfgRegCoLineInterfaceMode, 0, regVal );
        regSet( regdb, VarRegCoFunctionActivate1__VarXFICoreVCOEnP0, 0, 1 );
    } else {
        /* XFI Lock to Reference Clock */
        regSet( regdb, CfgRegCoXFISetup__Cfgrxlockref_xfi1, 0, 1);

        /* This field has to be 1 to access the MDIO port 1 slave */
        regSet( regdb, CfgRegCoMDIOSlaveSetup__CfgRegMDIOIntSlavePortAddrP1, 0, 1);

        /* Configure the Line Interface Mode for XFI */
        regGet( regdb, CfgRegCoLineInterfaceMode, 0, &regVal );
        regVal = regVal | BIT_2;
        regVal = regVal & ~BIT_3;
        regSet( regdb, CfgRegCoLineInterfaceMode, 0, regVal );
        regSet( regdb, VarRegCoFunctionActivate1__VarXFICoreVCOEnP1, 0, 1 );
    }

    regVal = 0;
    regGet( regdb, CfgRxControl, port, &regVal);
    regVal = regVal | BIT_5; /* Rx PLL Cal */
    regVal = regVal | BIT_17 | BIT_18; /* Rx PLL Loop dynamic */
    regVal = regVal & ~BIT_19; /* Rx PLL Loop dynamic */
    regVal = regVal & ~BIT_20; /* Rx PLL Loop dynamic */
    regSet( regdb, CfgRxControl, port, regVal );

    /* Waiting for the Rx Lock Detect */
    regVal = 0;
    while (regVal != 0x10) {
        regGet( regdb, CfgRxControl, port, &regVal );
        regVal = regVal & 0x10;
    }

    regVal = 0;
    regGet( regdb, CfgTxControl, port, &regVal);
    regVal = regVal | BIT_5; /* Tx PLL Cal */
    regSet( regdb, CfgTxControl, port, regVal );

    /* Waiting for the Tx Lock Detect */
    regVal = 0;
    while (regVal != 0x10) {
        regGet( regdb, CfgTxControl, port, &regVal );
        regVal = regVal & 0x10;
    }

    /* Enable the Tx, Rx and VCO logic of XFI core */
    regGet( regdb, VarRegCoFunctionActivate1, 0, &regVal );
    if (port == 0)
        regVal = regVal | BIT_4 | BIT_3 | BIT_2;
    else
        regVal = regVal | BIT_7 | BIT_5 | BIT_6;
    regSet( regdb, VarRegCoFunctionActivate1, 0, regVal );

    regSet( regdb, CfgRxControl, port, 0x400712b0 );
    regSet( regdb, CfgTxControl, port, 0x4c0012b0 );
    regSet( regdb, CfgStatusControl, port, 0x20000090 );

    /* XFI Lock to Data */
    if (port == 0)
        regSet( regdb, CfgRegCoXFISetup__Cfgrxlockref_xfi0, 0, 0 );
    else
        regSet( regdb, CfgRegCoXFISetup__Cfgrxlockref_xfi1, 0, 0 );
    osDelay(2000);

    /* Enable Rx Port Interface */
    regGet( regdb, VarRegCoFunctionActivate1, 0, &regVal );
    if (port == 0)
        regVal = regVal | BIT_10;
    else
        regVal = regVal | BIT_12;
    regSet( regdb, VarRegCoFunctionActivate1, 0, regVal );

    /* Unmask the Sync Status Changed Interrupt */
    regSet (regdb, StsRxSyncStatusChangedInterruptMask, port, 0);

    /* Configuring the MDIO for accessing the internal XFI core */
    regSet(regdb, CfgRegCoClockDiv0__MDIOClk, 0, 0xe);
    if (port == 0)
        regSet(regdb, CfgRegCoMDIOMode, 0, BIT_6);
    else
        regSet(regdb, CfgRegCoMDIOMode, 0, BIT_7);
    regVal = i = 0;
    while (!((regVal & BIT_12) && (regVal & BIT_0))) {
        rhAsicMdioRead(port, 32, 3, &regVal);
        if (i==10) {
            osPrintf("XFI port-%d Link not up; Module not connected\n", port);
            return ERROR;
        }
        osDelay(1000);
        i++;
    }

    /* Enable Tx Port Interface */
    regGet( regdb, VarRegCoFunctionActivate1, 0, &regVal );
    if (port == 0)
        regVal = regVal | BIT_11;
    else
        regVal = regVal | BIT_13;
    regSet( regdb, VarRegCoFunctionActivate1, 0, regVal );

    printf("XFI port-%d Tx and Rx Link Up\n", port);
    return OK;
}

void rhXauiByteSyncWait (reginfo_t *regdb, int port)
{
    unsigned int regVal, expVal;
    int i;

    /* Wait for Byte Sync Status Change Interrupt */
    regVal = i = 0;
    expVal = 1 << port;
    while (regVal != expVal) {
        regGet( regdb, StsRegCoXAUIInterrupt, 0, &regVal );
        regVal = regVal & expVal;
        if (i == 10)
        {
            printf("rhXauiInit(): Byte Sync Status Change Interrupt Wait Timeout: regVal: 0x%08x\n", regVal);
            break;
        }
        i++;
    }
}

void rhXauiGigablazeReset (int port, int loopback)
{
    unsigned int regVal;
    int i;

    /* Apply Gigablaze Reset to all the four lanes */
    if (loopback == 0)
    {
        for (i = 0; i < 4; i++)
        {
            rhAsicMdioWrite(port, 32770 + i, 3, 0xf218); /* put into reset */
            rhAsicMdioRead(port, 32770 + i, 3, &regVal);
            osDelay(500);
            rhAsicMdioWrite(port, 32770 + i, 3, 0xf008); /* take out of reset */
            rhAsicMdioRead(port, 32770 + i, 3, &regVal);
        }
        rhAsicMdioRead(port, 0, 3, &regVal); /* read gigablaze control */
        regVal |= BIT_15; /* assert reset */
        rhAsicMdioWrite(port, 0, 3, regVal); /* put into reset */
        osDelay(500);

        /* Disable RXLOS detection */
        rhAsicMdioWrite(port, 32775, 3, 0x001F);
    }
    else
    {
        for (i = 0; i < 4; i++)
        {
            rhAsicMdioWrite(port, 32770 + i, 3, 0x7218); /* put into reset/loopback */
            rhAsicMdioRead(port, 32770 + i, 3, &regVal);
        }
    }
}

int rhXauiLinkStatusGet (reginfo_t *regdb, int port)
{
    unsigned int regVal, expVal;
    int i;

    /*
     * Wait for Byte Sync Acquired status to become 1 on all the 4 XAUI
     * lanes
     */
    regVal = 0;
    i = 0;
    expVal = 0x0f0 << (port * 4);
    while (1)
    {
        regGet( regdb, StsRegCoXAUIIO, 0, &regVal );
        regVal = regVal & expVal;
        if (regVal == expVal)
        {
            break;
        }
        else
        {
            if (++i == 100)
            {
                printf ("Port-%d XAUI Module is not up; Check the connectivity: regVal: 0x%08x\n", port, regVal);
                return ERROR;
            }
            osDelay(2000);
        }
    }
    printf ("XAUI Port-%d Rx and Tx Link UP\n", port);

    return OK;
}

void rhXauiLinkStatusDisplay (int port)
{
    rhXauiLinkStatusGet (redHawkRegs, port);
}

/* Initializes the XAUI module */
int rhXauiInit (reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Enabling XAUI RXBUF inputs */
    regGet( regdb, CfgRegCoXAUIIOConfig, 0, &regVal );
    if (port == 0)
        regVal = regVal & ~BIT_4 & ~BIT_5;
    else
        regVal = regVal & ~BIT_12 & ~BIT_13;
    regSet( regdb, CfgRegCoXAUIIOConfig, 0, regVal );

    /* Disabling XAUI RXBUF inputs */
    if (port == 0)
        regVal = regVal | BIT_4 | BIT_5;
    else
        regVal = regVal | BIT_12 | BIT_13;
    regSet( regdb, CfgRegCoXAUIIOConfig, 0, regVal );

    /* Configure the Line Interface Mode for XAUI */
    regGet( regdb, CfgRegCoLineInterfaceMode, 0, &regVal );
    if (port == 0) {
        regVal = regVal | BIT_1;
        regVal = regVal & ~BIT_0;
    } else {
        regVal = regVal | BIT_3;
        regVal = regVal & ~BIT_2;
    }
    regSet( regdb, CfgRegCoLineInterfaceMode, 0, regVal );

    /* Select the Port0 XMAC clock for XAUI */
    regGet( regdb, CfgRegCoClkSelect, 0, &regVal );
    if (port == 0)
        regVal = regVal & ~BIT_2;
    else
        regVal = regVal & ~BIT_3;
    regSet( regdb, CfgRegCoClkSelect, 0, regVal );

    /* Removing softreset for PLL modules; Enables the XAUI Core */
    regGet( regdb, CfgRegCoMisc, 0, &regVal );
    if (port == 0)
        regVal = regVal | BIT_17;
    else
        regVal = regVal | BIT_18;
    regSet( regdb, CfgRegCoMisc, 0, regVal );
    osDelay(2000);

    /* Unmask Byte Sync Status change Interrupt */
    regGet( regdb, StsRegCoXAUIInterruptMask, 0, &regVal );
    if (port == 0)
        regVal = regVal & ~BIT_0;
    else
        regVal = regVal & ~BIT_1;
    regSet( regdb, StsRegCoXAUIInterruptMask, 0, regVal );

      /* Slow down the MDIO clock */
    regGet( regdb, CfgRegCoClockDiv0, 0, &regVal );
    regVal &= ~0x000000FF;
    regVal |=  0x00000009;
    regSet( regdb, CfgRegCoClockDiv0, 0, regVal );

    /* Activate MDIO module */
    regGet( regdb, VarRegCoFunctionActivate0, 0, &regVal );
    regVal = regVal | BIT_0;
    regSet( regdb, VarRegCoFunctionActivate0, 0, regVal );

    /* Select Internal MDIO Master/Slave Mode */
    regSet( regdb, CfgRegCoMDIOMode, 0, (0x00000004 << port));

    rhAsicMdioWrite(port, 32774, 3, 0x17fe);

    if (port == 0) {
        regSet( regdb, CfgRegCoXAUIIOConfig__XAUI0_TXON, 0, 0x1);
        regSet( regdb, CfgRegCoXAUIIOConfig__XAUI0_Hiterm, 0, 0x0);
        regSet( regdb, CfgRegCoXAUIIOConfig__CPUXAUI0_Termr0_FromTrimSel, 0, 0x1);
        regSet( regdb, CfgRegCoXAUIIOConfig__CPUXAUI0_Termr1_FromTrimSel, 0, 0x1);
    } else {
        regSet( regdb, CfgRegCoXAUIIOConfig__XAUI1_TXON, 0, 0x1);
        regSet( regdb, CfgRegCoXAUIIOConfig__XAUI1_Hiterm, 0, 0x0);
        regSet( regdb, CfgRegCoXAUIIOConfig__CPUXAUI1_Termr0_FromTrimSel, 0, 0x1);
        regSet( regdb, CfgRegCoXAUIIOConfig__CPUXAUI1_Termr1_FromTrimSel, 0, 0x1);
    }

    osDelay(5000);

    rhXauiGigablazeReset(port, 0);

#ifndef CONFIG_OCTEON_AT5810
    rhXauiByteSyncWait (regdb, port);
#endif

    return (rhXauiLinkStatusGet (regdb, port));
}

/* Initializes the SPI module */
void rhSpiInit (reginfo_t *regdb, int port)
{
    unsigned int regVal;

    if (port == 0) {
        /* Deactivating SPI modules; Ensuring the deactivation of SPI modules */
        regGet( regdb, VarRegCoFunctionActivate0, 0, &regVal );
        regVal = regVal & ~BIT_2;
        regVal = regVal & ~BIT_4;
        regSet( regdb, VarRegCoFunctionActivate0, 0, regVal );

        regSet( regdb, CfgRegRxpSpiDataMaxTLsb, 0, 0x0000FFFF );

        /*
         * Programming the Primary SPI Calendar Sequence
         * This is a sample calendar configuration just good enough for the
         * data path to work. User has to make sure that the SPI data and
         * status clock is available to configure the below registers
         */
        regSet( regdb, CfgRegTSpiCalSetup, 0, 0x00000029 );
        rh_program_calendar_mem(0);

        /* SPI Status channel is disabled by default; so enable it */
        regSet( regdb, CfgRegRxpSpiSetup, 0, 0x00000008 );
        /* Mapping the SPI Channel to FIFO Id */
        regSet( regdb, CfgRegRxpSpiAddressMap, 1, 0x00000001 );
        regSet( regdb, CfgRegRxpSpiAddressMap, 2, 0x00000002 );
        regSet( regdb, CfgRegRxpSpiAddressMap, 3, 0x00000003 );
        regSet( regdb, CfgRegRxpSpiAddressMap, 4, 0x00000004 );
        regSet( regdb, CfgRegRxpSpiCalSetup, 0, 0x00000029 );
        rh_program_calendar_mem(2);

        /* Configure the System Interface Mode for SPI */
        regSet( regdb, CfgRegCoSystemInterfaceMode, 0, 1 );

        /* Activating SPI modules
        regGet( regdb, VarRegCoFunctionActivate0, 0, &regVal );
        regVal = regVal | BIT_2;
        regVal = regVal | BIT_4;
        regSet( regdb, VarRegCoFunctionActivate0, 0, regVal ); */

        /* Clear the Training count stats */
        regGet( regdb, StsRegRxpSpiTrainingCount, 0, &regVal);
    } else {
        /* Deactivating SPI modules; Ensuring the deactivation of SPI modules */
        regGet( regdb, VarRegCoFunctionActivate0, 0, &regVal );
        regVal = regVal & ~BIT_3;
        regVal = regVal & ~BIT_5;
        regSet( regdb, VarRegCoFunctionActivate0, 0, regVal );

        regSet( regdb, CfgRegRxpSpiDataMaxTLsb, 0, 0x0000FFFF );

        /*
         * Programming the Secondary SPI Calendar Sequence
         * This is a sample calendar configuration just good enough for the
         * data path to work. User has to make sure that the SPI data and
         * status clock is available to configure the below registers
         */
        regSet( regdb, CfgRegTxSSpiCalSetup, 0, 0x00000073 );
        rh_program_calendar_mem(1);

        /* SPI Status channel is disabled by default; enable it */
        regSet( regdb, CfgRegRxsSpiSetup, 0, 0x00000008 );
        /* Mapping the SPI Channel to FIFO Id */
        regSet( regdb, CfgRegRxsSpiAddressMap, 0, 0x00000001 );
        regSet( regdb, CfgRegRxsSpiAddressMap, 1, 0x00000000 );
        regSet( regdb, CfgRegRxsSpiCalSetup, 0, 0x0000003f );
        rh_program_calendar_mem(3);

        /* Activating SPI modules
        regGet( regdb, VarRegCoFunctionActivate0, 0, &regVal );
        regVal = regVal | BIT_3;
        regVal = regVal | BIT_5;
        regSet( regdb, VarRegCoFunctionActivate0, 0, regVal ); */

        /* Clear the Training count stats */
        regGet( regdb, StsRegRxsSpiTrainingCount, 0, &regVal);
    }
}

/* Initializes/ Configures the Queue Manager, Memory Manager and FCRAM */
/* Activates all the modules with respect to the port provided */
void rhMiscInit (reginfo_t *regdb, int port, int ram_type)
{
    unsigned int regVal;
	unsigned int commonMask =
	BIT_0 | BIT_1 | BIT_2;  /* enable MDIO, temperature, RxP SPI */
	unsigned int MacMask = BIT_6 | BIT_7 |				/* TxMac, TxVLan,  */
						   BIT_8 | BIT_10 | BIT_11 |	/* RxDequeuer, RxDualMemCtrl, RxQueueManager */
						   BIT_12 | BIT_13 | 			/* RxEnqueuer, RxDrop */
						   BIT_15 | BIT_16 | BIT_18;	/* RxXauiMac, TxXauiMac, LED interface */
	unsigned int Port1Mask = BIT_15 | BIT_13 | BIT_12;	/* TxMemManager1, RxIntf1, TxIntf1 */
	unsigned int Port0Mask = BIT_14 | BIT_11 | BIT_10;	/* TxMemManager0, RxIntf0, TxIntf0 */

    if (port == 0) {
        /* Activating remaining modules except Primary SPI */
        regGet( regdb, VarRegCoFunctionActivate0, 0, &regVal);
        regVal = regVal | commonMask | MacMask;
        regSet( regdb, VarRegCoFunctionActivate0, 0, regVal);
        regGet( regdb, VarRegCoFunctionActivate1, 0, &regVal);
        regVal = regVal | Port0Mask;
        regSet( regdb, VarRegCoFunctionActivate1, 0, regVal);
    } else {
        /* Activating the remaining modules except Secondary SPI */
        regGet( regdb, VarRegCoFunctionActivate0, 0, &regVal);
        regVal = regVal | commonMask | (MacMask << 13);
        regSet( regdb, VarRegCoFunctionActivate0, 0, regVal);
        regGet( regdb, VarRegCoFunctionActivate1, 0, &regVal);
        regVal = regVal | Port1Mask;
        regSet( regdb, VarRegCoFunctionActivate1, 0, regVal);
    }

    /* Configuring RedHawk to generate the EFH internally */
    if (port == 0)
        regSet (regdb, CfgTxMemInsertHdr_P0, 0, 0x00000001);
    else
        regSet (regdb, CfgTxMemInsertHdr_P1, 0, 0x00000001);

    /* Calling the FCRAM init routines */
    if (ram_type != 0) {
        comm_fcram_init(port, ram_type);
        fcram_init(port, ram_type);
    }

    regSet(regdb, CfgFreePageTableInit, port, 0x00000001);

    /* Check for the FreePageTableInit done interrupt for both the instances  */
    regVal = 0;
    while (regVal == 0) {
        regGet (regdb, StsFreePageTableInitDone, port, &regVal);
    }

    /* Configure MAC to Enable Padding and Oversize frames */
    regSet (regdb, CfgRegTxMACModes, port, 0x0000000a);

    /* SHIM header is not stripped by default; strip it */
    regSet (regdb, CfgDeqHeaderStripControl, port, 0x00000001);

    /* Set the Line to CPU Full packet mode */
    regSet (regdb, CfgLineToCpuFullPacketMode, port, 1);
    regSet (regdb, StsLineToCPUFifoDataInterruptMask, port, 0);

    /* Configuring the Queue Manager */
    set_qm_maxpages (port);

    if (port == 0) {
        /* Activating RxMac and TxSpi modules Primary */
        regGet( regdb, VarRegCoFunctionActivate0, 0, &regVal);
        regVal = regVal | BIT_14 | BIT_4;
        regSet( regdb, VarRegCoFunctionActivate0, 0, regVal);
    } else {
        /* Activating RxMac And TxSpi modules Secondary */
        regGet( regdb, VarRegCoFunctionActivate0, 0, &regVal);
        regVal = regVal | BIT_27 | BIT_5;
        regSet( regdb, VarRegCoFunctionActivate0, 0, regVal);
    }
}

/* XFI Initialization Routine */
void rh_xfi_config (reginfo_t *regdb, int port, int ram_type)
{
    /* Configure the Common registers */
    rhCommonInit (regdb, port);

    /* In internal memory mode - Powerdown the FCRAM IOs and HM */
    if (ram_type == 0)
        rhAsicFCRAMPowerdown (port);

    /* Powering down the XAUI interface */
    rhAsicXAUIPowerdown (port);

    /* Initialize/Configure the XFI module */
    if (rhXfiInit (regdb, port) == ERROR)
        return;

    /* Configure the SPI */
    rhSpiInit (regdb, port);

    /* Configure the Memory Manager, Free Page Table, Queue Manager and FCRAM */
    rhMiscInit (regdb, port, ram_type);

    /* Configure the RxControl register */
    regSet (regdb, CfgRxControl__rxeq, port, 0x7);
    regSet (regdb, CfgRxControl__rxphase, port, 0x17);
}

/* XAUI Initialization routine */
void rh_xaui_config (reginfo_t *regdb, int port, int ram_type)
{
    /* Configure the Common registers */
    rhCommonInit (regdb, port);
    /* In internal memory mode - Powerdown the FCRAM IOs and HM */
    if (ram_type == 0)
        rhAsicFCRAMPowerdown (port);
    /* Powering down the XFI interface */
    rhAsicXFIPowerdown (port);
    /* Initialize/Configure the XAUI module */
    if (rhXauiInit (regdb, port) == ERROR)
    {

#ifndef CONFIG_OCTEON_AT5810
        return;
#endif

    }
    /* Configure the SPI */
    rhSpiInit (regdb, port);
    /* Configure the Memory Manager, Free Page Table, Queue Manager and FCRAM */
    rhMiscInit (regdb, port, ram_type);
}

/* Rx XFI re-initialization routine */
void rh_rxxfi_reconfig (reginfo_t *regdb, int port)
{
    unsigned int regVal, revLpbEna;

    regGet( regdb, CfgRxControl, port, &revLpbEna);
    regVal = revLpbEna;
    revLpbEna = revLpbEna & BIT_29;
    regVal &= ~BIT_29;
    regSet( regdb, CfgRxControl, port,  regVal);

    /* Disable the Rx logic of XFI core for the respective port */
    regGet( regdb, VarRegCoFunctionActivate1, 0, &regVal );
    if (port == 0)
        regVal &= ~(BIT_2 | BIT_10);
    else
        regVal &= ~(BIT_5 | BIT_12);
    regSet( regdb, VarRegCoFunctionActivate1, 0, regVal );

    /* Initialize and Configure the XFI interface */
    if (rhRxXfiInit (regdb, port) == ERROR)
        return;

    /*
     * Set the Reverse Clock Select and Reverse Loopback
     * Enable bit to their previous values
     */
    if(revLpbEna) {
        regGet( regdb, CfgRxControl, port, &regVal);
        regVal = regVal | BIT_29;
        regSet( regdb, CfgRxControl, port, regVal );
    }
}

void rhAsicXAUIPowerdown (int portNum)
{
    if (portNum == 0) {
        /* XAUI IO powerdown */
        regSet (redHawkRegs, CfgRegCoXAUIIOConfig__XAUI0_RefPd, 0, 0);

        /* Reset the XAUI XMACs  */
        regSet (redHawkRegs, VarRegCoFunctionActivate0__VarRxXauiXmacEnP0, 0, 0);
        regSet (redHawkRegs, VarRegCoFunctionActivate0__VarTxXauiXmacEnP0, 0, 0);

        /* Enable the MDIO and XAUI core before  you do MDIO operation */
        regSet (redHawkRegs, CfgRegCoMisc__VarXAUICoreEn0, 0, 1 );
        regSet (redHawkRegs, VarRegCoFunctionActivate0__VarMDIOActivate, 0, 1);

        /* Set the MDIO Mode */
        regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_2);
        /* Do Gigablaze powerdown  for port 0 */
        rhAsicMdioWrite (0, 32770, 3, 0xfe00);
        rhAsicMdioWrite (0, 32771, 3, 0xfe00);
        rhAsicMdioWrite (0, 32772, 3, 0xfe00);
        rhAsicMdioWrite (0, 32773, 3, 0xfe00);
        osDelay (500);

        /* Do Gigablaze reset for port 0 */
        rhAsicMdioWrite (0, 32770, 3, 0xfe18);
        rhAsicMdioWrite (0, 32771, 3, 0xfe18);
        rhAsicMdioWrite (0, 32772, 3, 0xfe18);
        rhAsicMdioWrite (0, 32773, 3, 0xfe18);

        regSet (redHawkRegs, CfgRegCoMisc__VarXAUICoreEn0, 0, 0);
    } else {
        /* XAUI IO powerdown */
        regSet (redHawkRegs, CfgRegCoXAUIIOConfig__XAUI1_RefPd, 0, 0);

        /* Reset the XAUI XMACs  */
        regSet (redHawkRegs, VarRegCoFunctionActivate0__VarRxXauiXmacEnP1, 0, 0);
        regSet (redHawkRegs, VarRegCoFunctionActivate0__VarTxXauiXmacEnP1, 0, 0);

        /* Enable the MDIO and XAUI core before  you do MDIO operation */
        regSet (redHawkRegs, CfgRegCoMisc__VarXAUICoreEn1, 0, 1 );
        regSet (redHawkRegs, VarRegCoFunctionActivate0__VarMDIOActivate, 0, 1);

        /* Set the MDIO Mode */
        regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_3);

        /* Do Gigablaze powerdown  for port 1 */
        rhAsicMdioWrite (1, 32770, 3, 0xfe00);
        rhAsicMdioWrite (1, 32771, 3, 0xfe00);
        rhAsicMdioWrite (1, 32772, 3, 0xfe00);
        rhAsicMdioWrite (1, 32773, 3, 0xfe00);

        osDelay (500);

        /* Do Gigablaze reset for port 1 */
        rhAsicMdioWrite (1, 32770, 3, 0xfe18);
        rhAsicMdioWrite (1, 32771, 3, 0xfe18);
        rhAsicMdioWrite (1, 32772, 3, 0xfe18);
        rhAsicMdioWrite (1, 32773, 3, 0xfe18);
        regSet (redHawkRegs, CfgRegCoMisc__VarXAUICoreEn1, 0, 0);
    }
}

void rhAsicXFIPowerdown (int portNum)
{
    if (portNum == 0) {
        regSet(redHawkRegs, CfgRegCoXFIIOConfig__XFI0_CLKOUTPowerDownN, 0, 0); /* XFI IO powerdown */

        /* Toggle the VCO Enable bits */
        regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP0, 0, 0);
        regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP0, 0, 1);

        /* Reset XFI Circutary */
        regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP0, 0, 0);
        regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP0, 0, 0);
        regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP0, 0, 0);

        /* Reset XFI Cores */
        regSet(redHawkRegs, CfgRxControl__rxclk66pd, 0, 1);
        regSet(redHawkRegs, CfgRxControl__rxlockpd, 0, 1);
        regSet(redHawkRegs, CfgRxControl__rxpd, 0, 1);

        regSet(redHawkRegs, CfgTxControl__txclk66pd, 0, 1);
        regSet(redHawkRegs, CfgTxControl__txlockpd, 0, 1);
        regSet(redHawkRegs, CfgTxControl__txpd, 0, 1);
    } else {
        regSet(redHawkRegs,CfgRegCoXFIIOConfig__XFI1_CLKOUTPowerDownN, 0, 0); /* XFI IO powerdown */

        /* Toggle the VCO Enable bits */
        regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP1, 0, 0);
        regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP1, 0, 1);

        /* Reset XFI Circutary */
        regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP1, 0, 0);
        regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP1, 0, 0);
        regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP1, 0, 0);

        /* Reset XFI Cores */
        regSet(redHawkRegs, CfgRxControl__rxclk66pd, 1, 1);
        regSet(redHawkRegs, CfgRxControl__rxlockpd, 1, 1);
        regSet(redHawkRegs, CfgRxControl__rxpd, 1, 1);

        regSet(redHawkRegs, CfgTxControl__txclk66pd, 1, 1);
        regSet(redHawkRegs, CfgTxControl__txlockpd, 1, 1);
        regSet(redHawkRegs, CfgTxControl__txpd, 1, 1);
    }
}

void rhAsicSPIPowerdown (int portNum)
{
    if (portNum == 0) {
        /* SPI IO powerdown - P0 */
        regSet (redHawkRegs, CfgRegCoSPIIOConfig__SPI0_RxPowerDown, 0, 1);
        regSet (redHawkRegs, CfgRegCoSPIIOConfig__SPI0_TxPowerDown, 0, 1);

        /* PRI SPI powerdown - HyperPhy */
        regSet(redHawkRegs, CfgRegCoSpiSetup__PTSpiPowerDn, 0, 1);
        regSet(redHawkRegs, CfgRegCoSpiSetup__PRSpiPowerDn, 0, 1);

        /* PRI SPI powerdown  */
        regSet (redHawkRegs, CfgRegCoRxpSpiHMPLLReg__RSPI_PLL, 0, 0x4a54);
        regSet (redHawkRegs, CfgRegRxpSpiHMMisc__RSPI_POWER_DOWN, 0, 1);

        /* PRI TSPI hard macro power down  */
        regSet (redHawkRegs, CfgRegTxPSpiHMMisc__TSPI_POWER_DOWN, 0, 1);
        regSet (redHawkRegs, CfgRegTxPSpiHMMisc__TSPI_POWER_DOWN_PPD, 0, 1);
        regSet (redHawkRegs, CfgRegCoTxPSpiHMPLLReg__TSPI_PLL, 0,  0xa3ac);
        regSet (redHawkRegs, CfgRegCoSpiSetup__VarNPSIEn0, 0, 1);
    } else {
        /* SPI IO powerdown - P1 */
        regSet(redHawkRegs, CfgRegCoSPIIOConfig__SPI1_RxPowerDown, 0, 1);
        regSet(redHawkRegs, CfgRegCoSPIIOConfig__SPI1_TxPowerDown, 0, 1);

        /* SEC SPI powerdown - HyperPhy */
        regSet(redHawkRegs, CfgRegCoSpiSetup__STSpiPowerDn, 0, 1);
        regSet(redHawkRegs, CfgRegCoSpiSetup__SRSpiPowerDn, 0, 1);

        /* SEC RSPI hard macro power down  */
        regSet(redHawkRegs, CfgRegCoRxsSpiHMPLLReg__RSPI_PLL, 0, 0x4a54);
        regSet(redHawkRegs, CfgRegRxsSpiHMMisc__RSPI_POWER_DOWN, 0, 1);

        /* SEC TSPI hard macro power down  */
        regSet(redHawkRegs, CfgRegTxSSpiHMMisc__TSPI_POWER_DOWN, 0, 1);
        regSet(redHawkRegs, CfgRegTxSSpiHMMisc__TSPI_POWER_DOWN_PPD, 0, 1);
        regSet(redHawkRegs, CfgRegCoTxSSpiHMPLLReg__TSPI_PLL, 0,  0xa3ac);
        regSet(redHawkRegs, CfgRegCoSpiSetup__VarNPSIEn1, 0, 1);
    }
}

void rhAsicFCRAMPowerdown (int portNum)
{
    unsigned int regVal;
    if (portNum == 0) {
        regGet (redHawkRegs, CfgRegCoFCRAMIOConfig, 0, &regVal);
        regVal = regVal | BIT_13 | BIT_12;
        regVal = regVal & ~BIT_14;
        regSet (redHawkRegs, CfgRegCoFCRAMIOConfig, 0, regVal);
    } else {
        regGet (redHawkRegs, CfgRegCoFCRAMIOConfig, 0, &regVal);
        regVal = regVal | BIT_28 | BIT_27;
        regVal = regVal & ~BIT_29;
        regSet (redHawkRegs, CfgRegCoFCRAMIOConfig, 0, regVal);
    }
    osDelay(2000);
}

/* Set Queue Manager Max Pages */
void set_qm_maxpages (int port)
{
    if (port == 0) {
        /* Configuring Port 0 Queue Manager */
        regSet (redHawkRegs, CfgDefault__Discard, 0, 1);
        regSet (redHawkRegs, CfgQueueManagerEnable, 0, 0x3F);

        /* Configuring Queue Number 0 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 0, 0);
        regSet (redHawkRegs, CfgMaxPageCountWr, 0, 32);

        /* Configuring Queue Number 1 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 0, 1);
        regSet (redHawkRegs, CfgMaxPageCountWr, 0, 32);

        /* Configuring Queue Number 2 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 0, 2);
        regSet (redHawkRegs, CfgMaxPageCountWr, 0, 32);

        /* Configuring Queue Number 3 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 0, 3);
        regSet (redHawkRegs, CfgMaxPageCountWr, 0, 32);

        /* Configuring Queue Number 4 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 0, 4);
        regSet (redHawkRegs, CfgMaxPageCountWr, 0, 32);

        /* Configuring Queue Number 5 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 0, 5);
        regSet (redHawkRegs, CfgMaxPageCountWr, 0, 32);

        /* Configuring Queue Number 6 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 0, 6);
        regSet (redHawkRegs, CfgMaxPageCountWr, 0, 32);

        /* Configuring Queue Number 7 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 0, 7);
        regSet (redHawkRegs, CfgMaxPageCountWr, 0, 32);

        /* Disabling Queue Manager */
        regSet (redHawkRegs, CfgQueueManagerEnable, 0, 0);
        osDelay(100);
        regSet (redHawkRegs, CfgDefault__Discard, 0, 0);
    } else {
        /* Configuring Port 1 Queue Manager */
        regSet (redHawkRegs, CfgDefault__Discard, 1, 1);
        regSet (redHawkRegs, CfgQueueManagerEnable, 1, 0x3F);

        /* Configuring Queue Number 0 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 1, 0);
        regSet (redHawkRegs, CfgMaxPageCountWr, 1, 32);

        /* Configuring Queue Number 1 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 1, 1);
        regSet (redHawkRegs, CfgMaxPageCountWr, 1, 32);

        /* Configuring Queue Number 2 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 1, 2);
        regSet (redHawkRegs, CfgMaxPageCountWr, 1, 32);

        /* Configuring Queue Number 3 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 1, 3);
        regSet (redHawkRegs, CfgMaxPageCountWr, 1, 32);

        /* Configuring Queue Number 4 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 1, 4);
        regSet (redHawkRegs, CfgMaxPageCountWr, 1, 32);

        /* Configuring Queue Number 5 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 1, 5);
        regSet (redHawkRegs, CfgMaxPageCountWr, 1, 32);

        /* Configuring Queue Number 6 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 1, 6);
        regSet (redHawkRegs, CfgMaxPageCountWr, 1, 32);

        /* Configuring Queue Number 7 */
        regSet (redHawkRegs, CfgMaxPageCountWrQnum, 1, 7);
        regSet (redHawkRegs, CfgMaxPageCountWr, 1, 32);

        /* Disabling Queue Manager */
        regSet (redHawkRegs, CfgQueueManagerEnable, 1, 0);
        osDelay(100);
        regSet (redHawkRegs, CfgDefault__Discard, 1, 0);
    }
}

/*************************************************************************
 *
 * RedHawk ASIC Statistic Functions
 *
 *************************************************************************/

/******************************************************************
* rhAsicShadowRegsStats - Get RedHawk Shadow Statistics
*
* The routine gets the RedHawk Shadow statistics
*
* RETURNS: None
*/
void rhAsicShadowRegsStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     shadowRegsStats *stat  /* Structure that holds the statistics */
     )
{
    STAT_INST(StsShadowRegToalFrmsReceived, &stat->ToalFrmsReceived);
    STAT_INST(StsShadowRegToalFrmsTransmitted, &stat->ToalFrmsTransmitted);
    STAT_INST(StsShadowRegGoodFrmsReceived, &stat->GoodFrmsReceived);
    STAT_INST(StsShadowRegGoodFrmsTransmitted, &stat->GoodFrmsTransmitted);
    STAT_INST(StsShadowRegCrcErrsReceived, &stat->CrcErrsReceived);
    STAT_INST(StsShadowRegCrcErrsTransmitted, &stat->CrcErrsTransmitted);
    STAT_INST(StsShadowRegFrmsDropedByRed, &stat->FrmsDropedByRed);
    STAT_INST(StsShadowRegUCastFrmsDroped, &stat->UCastFrmsDroped);
    STAT_INST(StsShadowRegMCastFrmsDroped, &stat->MCastFrmsDroped);
    STAT_INST(StsShadowRegBCastFrmsDroped, &stat->BCastFrmsDroped);
    STAT_INST(StsShadowRegMPLSFrmsDroped, &stat->MPLSFrmsDroped);
    STAT_INST(StsShadowRegEthTypeMatchFrmsDroped, &stat->EthTypeMatchFrmsDroped);
    STAT_INST(StsShadowRegMacFilterFrmsDroped, &stat->MacFilterFrmsDroped);
    STAT_INST(StsShadowRegIngFilterFrmsDroped, &stat->IngFilterFrmsDroped);
    STAT_INST(StsShadowRegDeqExcessLatencyFrmsDroped, &stat->DeqExcessLatencyFrmsDroped);
    STAT_INST(StsShadowRegEnqMemFullFrmsDroped, &stat->EnqMemFullFrmsDroped);
}

/******************************************************************
* rhAsicRxMacStats - Get RedHawk receive MAC Statistics
*
* The routine gets the receive MAC statistics of the RedHawk.
*
* RETURNS: None
*/
void rhAsicRxMacStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     rxMacStats *stat       /* Structure that holds the statistics */
     )
{
    STAT_INST(StsRegRxVLANTagRcvd, &stat->RxVLANTagRcvd);
    STAT_INST(StsRegRxPauseTime, &stat->RxPauseTime);
    STAT_INST(StsRegLsbRxOctetsRcvdOK, &stat->LsbRxOctetsRcvdOK);
    STAT_INST(StsRegMsbRxOctetsRcvdOK, &stat->MsbRxOctetsRcvdOK);
    STAT_INST(StsRegLsbRxNumOfBadOctets, &stat->LsbRxNumOfBadOctets);
    STAT_INST(StsRegMsbRxNumOfBadOctets, &stat->MsbRxNumOfBadOctets);
    STAT_INST(StsRegRxNumOfBadFrms, &stat->RxNumOfBadFrms);
    STAT_INST(StsRegRxFRcvdOK, &stat->RxFRcvdOK);
    STAT_INST(StsRegRxNumOfCRCErrors, &stat->RxNumOfCRCErrors);
    STAT_INST(StsRegRxNumOfBcastFrms, &stat->RxNumOfBcastFrms);
    STAT_INST(StsRegRxNumOfMcastFrms, &stat->RxNumOfMcastFrms);
    STAT_INST(StsRegRxFrmsOf64Octets, &stat->RxFrmsOf64Octets);
    STAT_INST(StsRegRxFrmsOf65to127Octets, &stat->RxFrmsOf65to127Octets);
    STAT_INST(StsRegRxFrmsOf128to255Octets, &stat->RxFrmsOf128to255Octets);
    STAT_INST(StsRegRxFrmsOf256to511Octets, &stat->RxFrmsOf256to511Octets);
    STAT_INST(StsRegRxFrmsOf512to1023Octets, &stat->RxFrmsOf512to1023Octets);
    STAT_INST(StsRegRxFrmsOf1024to1518Octets, &stat->RxFrmsOf1024to1518Octets);
    STAT_INST(StsRegRxJumboFrms, &stat->RxJumboFrms);
    STAT_INST(StsRegRxOversizeFrms, &stat->RxOversizeFrms);
    STAT_INST(StsRegRxUndersizeFrms, &stat->RxUndersizeFrms);
    STAT_INST(StsRegRxNumOfFragments, &stat->RxNumOfFragments);
    STAT_INST(StsRegRxNumOfJabbers, &stat->RxNumOfJabbers);
    STAT_INST(StsRegRxNumOfTooLongJabbers, &stat->RxNumOfTooLongJabbers);
    STAT_INST(StsRegRxOutOfRangeLenField, &stat->RxOutOfRangeLenField);
    STAT_INST(StsRegRxFTooLongErrors, &stat->RxFTooLongErrors);
    STAT_INST(StsRegRxMACCtrlFRcvd, &stat->RxMACCtrlFRcvd);
    STAT_INST(StsRegRxUnsuppOpcodeRcvd, &stat->RxUnsuppOpcodeRcvd);
    STAT_INST(StsRegRxGoodVLANFRcvd, &stat->RxGoodVLANFRcvd);
    STAT_INST(StsRegRxBadSAFRcvd, &stat->RxBadSAFRcvd);
    STAT_INST(StsRegRxDataError, &stat->RxDataError);
    STAT_INST(StsRegRxMcastDrop, &stat->RxMcastDrop);
    STAT_INST(StsRegRxBcastDrop, &stat->RxBcastDrop);
    STAT_INST(StsRegRxFilDrop, &stat->RxFilDrop);
    STAT_INST(StsRegRxMACInterrupt, &stat->RxMACInterrupt);
    STAT_INST(StsRegRxMACInterruptMask, &stat->RxMACInterruptMask);
    STAT_INST(StsRegRxMACDiag, &stat->RxMACDiag);
    STAT_INST(StsRegRxIPG5, &stat->RxIPG5);
    STAT_INST(StsRegRxIPG6, &stat->RxIPG6);
    STAT_INST(StsRegRxIPG7, &stat->RxIPG7);
    STAT_INST(StsRegRxIPG8, &stat->RxIPG8);
    STAT_INST(StsRegRxIPG9, &stat->RxIPG9);
    STAT_INST(StsRegRxIPG10, &stat->RxIPG10);
    STAT_INST(StsRegRxIPG11, &stat->RxIPG11);
}

/******************************************************************
* rhAsicRxDropControlStats - Get RedHawk Drop Control Statistics
*
* The routine gets the RedHawk Drop Control statistics
*
* RETURNS: None
*/
void rhAsicRxDropControlStats (
     reginfo_t *regdb,        /* pointer to the register database */
     int port,                /* port number */
     rxDropControlStats *stat /* Structure that holds the statistics */
     )
{
    STAT_INST(StsMiscTailDropCount, &stat->TailDropCount);
    STAT_INST(StsRegRxDefaultDroppedFrms, &stat->RxDefaultDroppedFrms);
    STAT_INST(StsRegMSBRxDefaultDroppedOctets, &stat->MSBRxDefaultDroppedOctets);
    STAT_INST(StsRegLSBRxDefaultDroppedOctets, &stat->LSBRxDefaultDroppedOctets);
    STAT_INST(StsRegRxDroppedBCastFrms, &stat->RxDroppedBCastFrms);
    STAT_INST(StsRegRxDroppedMCastFrms, &stat->RxDroppedMCastFrms);
    STAT_INST(StsRegMSBRxDroppedBCastMCastOctets, &stat->MSBRxDroppedBCastMCastOctets);
    STAT_INST(StsRegLSBRxDroppedBCastMCastOctets, &stat->LSBRxDroppedBCastMCastOctets);
    STAT_INST(StsRegRxMPLSTypeMatchFrms, &stat->RxMPLSTypeMatchFrms);
    STAT_INST(StsRegRxMPLSDefaultMatchFrms, &stat->RxMPLSDefaultMatchFrms);
    STAT_INST(StsRegRxMPLSLLSPMatchFrms, &stat->RxMPLSLLSPMatchFrms);
    STAT_INST(StsRegRxMPLSDLLSPMatchFrms, &stat->RxMPLSDLLSPMatchFrms);
    STAT_INST(StsRegRxMPLSDroppedFrms, &stat->RxMPLSDroppedFrms);
    STAT_INST(StsRegMSBRxMPLSDroppedOctets, &stat->MSBRxMPLSDroppedOctets);
    STAT_INST(StsRegLSBRxMPLSDroppedOctets, &stat->LSBRxMPLSDroppedOctets);
    STAT_INST(StsRegRxVLANEthertypeFrms, &stat->RxVLANEthertypeFrms);
    STAT_INST(StsRegRxSVLANEthertypeFrms, &stat->RxSVLANEthertypeFrms);
    STAT_INST(StsRegRxVLANSVLANEtherDropFrms, &stat->RxVLANSVLANEtherDropFrms);
    STAT_INST(StsRegRxStdPriMapFrms, &stat->RxStdPriMapFrms);
    STAT_INST(StsRegRxExtdPriMapFrms, &stat->RxExtdPriMapFrms);
    STAT_INST(StsRegRxNoVLANTagFrms, &stat->RxNoVLANTagFrms);
    STAT_INST(StsRegRxSingleVLANTagFrms, &stat->RxSingleVLANTagFrms);
    STAT_INST(StsRegRxDoubleVLANTagFrms, &stat->RxDoubleVLANTagFrms);
    STAT_INST(StsRegRxMT2VLANTagFrms, &stat->RxMT2VLANTagFrms);
    STAT_INST(StsRegRxVLANControlDropFrms, &stat->RxVLANControlDropFrms);
    STAT_INST(StsRegRxExtdVLANTagFrms, &stat->RxExtdVLANTagFrms);
    STAT_INST(StsRegRxVLANTagOpFrms, &stat->RxVLANTagOpFrms);
    STAT_INST(StsRegRxVLANPrioOvrwrFrms, &stat->RxVLANPrioOvrwrFrms);
    STAT_INST(StsRegRxDAMatchFrms, &stat->RxDAMatchFrms);
    STAT_INST(StsRegRxMultiHashFrms, &stat->RxMultiHashFrms);
    STAT_INST(StsRegRxTypeFrms, &stat->RxTypeFrms);
    STAT_INST(StsRegRxOtherTypeFrms, &stat->RxOtherTypeFrms);
    STAT_INST(StsRegRxLLCSNAPFrms, &stat->RxLLCSNAPFrms);
    STAT_INST(StsRegRxUnknownLLCSNAPFrms, &stat->RxUnknownLLCSNAPFrms);
    STAT_INST(StsRegRxMACDropFrms, &stat->RxMACDropFrms);
    STAT_INST(StsRegMSBRxVLANMACDropOctets, &stat->MSBRxVLANMACDropOctets);
    STAT_INST(StsRegLSBRxVLANMACDropOctets, &stat->LSBRxVLANMACDropOctets);
    STAT_INST(StsRegRxDSCPIPVerMismatchFrms, &stat->RxDSCPIPVerMismatchFrms);
    STAT_INST(StsRegRxDSCPAssignFrms, &stat->RxDSCPAssignFrms);
    STAT_INST(StsRegRxIPAssignFrms, &stat->RxIPAssignFrms);
    STAT_INST(StsRegRxDIPAssignFrms, &stat->RxDIPAssignFrms);
    STAT_INST(StsRegRxDSCPIPDropFrms, &stat->RxDSCPIPDropFrms);
    STAT_INST(StsRegMSBRxDSCPIPDropOctets, &stat->MSBRxDSCPIPDropOctets);
    STAT_INST(StsRegLSBRxDSCPIPDropOctets, &stat->LSBRxDSCPIPDropOctets);
    STAT_INST(StsRegRxDropControlEOFs, &stat->RxDropControlEOFs);
    STAT_INST(StsOVLANCtrlRdData, &stat->OVLANCtrlRdData);
    STAT_INST(StsIVLANCtrlRdData, &stat->IVLANCtrlRdData);
    STAT_INST(StsVLANIDRdData, &stat->VLANIDRdData);
    STAT_INST(StsHashRdData, &stat->HashRdData);
    STAT_INST(StsDSCPAssignData, &stat->DSCPAssignData);
    STAT_INST(StsRegRxIllegalTypeLenFrms, &stat->RxIllegalTypeLenFrms);
    STAT_INST(StsRdDataRxVlanTagRam, &stat->RdDataRxVlanTagRam);
    STAT_INST(StsRegRxInRangeLengthErrs, &stat->RxInRangeLengthErrs);
    STAT_INST(StsRegRxOutofRangeLengthErrs, &stat->RxOutofRangeLengthErrs);
    STAT_INST(StsRegRxQueue0Frms, &stat->RxQueue0Frms);
    STAT_INST(StsRegRxQueue1Frms, &stat->RxQueue1Frms);
    STAT_INST(StsRegRxQueue2Frms, &stat->RxQueue2Frms);
    STAT_INST(StsRegRxQueue3Frms, &stat->RxQueue3Frms);
    STAT_INST(StsRegRxQueue4Frms, &stat->RxQueue4Frms);
    STAT_INST(StsRegRxQueue5Frms, &stat->RxQueue5Frms);
    STAT_INST(StsRegRxQueue6Frms, &stat->RxQueue6Frms);
    STAT_INST(StsRegRxQueue7Frms, &stat->RxQueue7Frms);
}

/******************************************************************
* rhAsicRxDropControlWredStats - Get RedHawk Drop Control WRED Statistics
*
* The routine gets the RedHawk Drop Control WRED statistics
*
* RETURNS: None
*/
void rhAsicRxDropControlWredStats (
     reginfo_t *regdb,            /* pointer to the register database */
     int port,                    /* port number */
     rxDropControlWredStats *stat /* Structure that holds the statistics */
     )
{
    STAT_INST(StsWREDDropProbability, &stat->WREDDropProbability);
    STAT_INST(StsWREDDrop_0, &stat->WREDDrop_0);
    STAT_INST(StsWREDDrop_1, &stat->WREDDrop_1);
    STAT_INST(StsWREDDrop_2, &stat->WREDDrop_2);
    STAT_INST(StsWREDDrop_3, &stat->WREDDrop_3);
    STAT_INST(StsWREDDrop_4, &stat->WREDDrop_4);
    STAT_INST(StsWREDDrop_5, &stat->WREDDrop_5);
    STAT_INST(StsWREDDrop_6, &stat->WREDDrop_6);
    STAT_INST(StsWREDDrop_7, &stat->WREDDrop_7);

    STAT_INST(StsBPDUDrop_0, &stat->BPDUDrop_0);
    STAT_INST(StsBPDUDrop_1, &stat->BPDUDrop_1);
    STAT_INST(StsBPDUDrop_2, &stat->BPDUDrop_2);
    STAT_INST(StsBPDUDrop_3, &stat->BPDUDrop_3);
    STAT_INST(StsBPDUDrop_4, &stat->BPDUDrop_4);
    STAT_INST(StsBPDUDrop_5, &stat->BPDUDrop_5);
    STAT_INST(StsBPDUDrop_6, &stat->BPDUDrop_6);
    STAT_INST(StsBPDUDrop_7, &stat->BPDUDrop_7);

    STAT_INST(StsTailDrop_0, &stat->TailDrop_0);
    STAT_INST(StsTailDrop_1, &stat->TailDrop_1);
    STAT_INST(StsTailDrop_2, &stat->TailDrop_2);
    STAT_INST(StsTailDrop_3, &stat->TailDrop_3);
    STAT_INST(StsTailDrop_4, &stat->TailDrop_4);
    STAT_INST(StsTailDrop_5, &stat->TailDrop_5);
    STAT_INST(StsTailDrop_6, &stat->TailDrop_6);
    STAT_INST(StsTailDrop_7, &stat->TailDrop_7);

    STAT_INST(StsGreenColorMark_0, &stat->GreenColorMark_0);
    STAT_INST(StsGreenColorMark_1, &stat->GreenColorMark_1);
    STAT_INST(StsGreenColorMark_2, &stat->GreenColorMark_2);
    STAT_INST(StsGreenColorMark_3, &stat->GreenColorMark_3);
    STAT_INST(StsGreenColorMark_4, &stat->GreenColorMark_4);
    STAT_INST(StsGreenColorMark_5, &stat->GreenColorMark_5);
    STAT_INST(StsGreenColorMark_6, &stat->GreenColorMark_6);
    STAT_INST(StsGreenColorMark_7, &stat->GreenColorMark_7);

    STAT_INST(StsYelloColorMark_0, &stat->YelloColorMark_0);
    STAT_INST(StsYelloColorMark_1, &stat->YelloColorMark_1);
    STAT_INST(StsYelloColorMark_2, &stat->YelloColorMark_2);
    STAT_INST(StsYelloColorMark_3, &stat->YelloColorMark_3);
    STAT_INST(StsYelloColorMark_4, &stat->YelloColorMark_4);
    STAT_INST(StsYelloColorMark_5, &stat->YelloColorMark_5);
    STAT_INST(StsYelloColorMark_6, &stat->YelloColorMark_6);
    STAT_INST(StsYelloColorMark_7, &stat->YelloColorMark_7);

    STAT_INST(StsOrangeColorMark_0, &stat->OrangeColorMark_0);
    STAT_INST(StsOrangeColorMark_1, &stat->OrangeColorMark_1);
    STAT_INST(StsOrangeColorMark_2, &stat->OrangeColorMark_2);
    STAT_INST(StsOrangeColorMark_3, &stat->OrangeColorMark_3);
    STAT_INST(StsOrangeColorMark_4, &stat->OrangeColorMark_4);
    STAT_INST(StsOrangeColorMark_5, &stat->OrangeColorMark_5);
    STAT_INST(StsOrangeColorMark_6, &stat->OrangeColorMark_6);
    STAT_INST(StsOrangeColorMark_7, &stat->OrangeColorMark_7);

    STAT_INST(StsColorRedMark_0, &stat->ColorRedMark_0);
    STAT_INST(StsColorRedMark_1, &stat->ColorRedMark_1);
    STAT_INST(StsColorRedMark_2, &stat->ColorRedMark_2);
    STAT_INST(StsColorRedMark_3, &stat->ColorRedMark_3);
    STAT_INST(StsColorRedMark_4, &stat->ColorRedMark_4);
    STAT_INST(StsColorRedMark_5, &stat->ColorRedMark_5);
    STAT_INST(StsColorRedMark_6, &stat->ColorRedMark_6);
    STAT_INST(StsColorRedMark_7, &stat->ColorRedMark_7);

    STAT_INST(StsExCongMark_0, &stat->ExCongMark_0);
    STAT_INST(StsExCongMark_1, &stat->ExCongMark_1);
    STAT_INST(StsExCongMark_2, &stat->ExCongMark_2);
    STAT_INST(StsExCongMark_3, &stat->ExCongMark_3);
    STAT_INST(StsExCongMark_4, &stat->ExCongMark_4);
    STAT_INST(StsExCongMark_5, &stat->ExCongMark_5);
    STAT_INST(StsExCongMark_6, &stat->ExCongMark_6);
    STAT_INST(StsExCongMark_7, &stat->ExCongMark_7);

    STAT_INST(StsEopCount, &stat->EopCount);
}

/******************************************************************
* rhAsicRxLineToCpuStats - Get RedHawk Line To CPU Statistics
*
* The routine gets the RedHawk Line To CPU statistics
*
* RETURNS: None
*/
void rhAsicRxLineToCpuStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     rxLineToCpuStats *stat /* Structure that holds the statistics */
     )
{
    STAT_INST(StsLineToCpuDataReg0, &stat->DataReg0);
    STAT_INST(StsLineToCpuDataReg1, &stat->DataReg1);
    STAT_INST(StsLineToCpuDataReg2, &stat->DataReg2);
    STAT_INST(StsLineToCpuDataReg3, &stat->DataReg3);
    STAT_INST(StsLineToCpuDataReg4, &stat->DataReg4);
    STAT_INST(StsLineToCpuDataReg5, &stat->DataReg5);
    STAT_INST(StsLineToCpuDataReg6, &stat->DataReg6);
    STAT_INST(StsLineToCpuDataReg7, &stat->DataReg7);
    STAT_INST(StsLineToCpuDataReg8, &stat->DataReg8);
    STAT_INST(StsLineToCpuDataReg9, &stat->DataReg9);
    STAT_INST(StsLineToCpuDataReg10, &stat->DataReg10);
    STAT_INST(StsLineToCpuDataReg11, &stat->DataReg11);
    STAT_INST(StsLineToCpuDataReg12, &stat->DataReg12);
    STAT_INST(StsLineToCPUWritePointer, &stat->WritePointer);
    STAT_INST(StsLineToCPUReadPointer, &stat->ReadPointer);
    STAT_INST(StsLineToCPUCommitPointer, &stat->CommitPointer);
    STAT_INST(StsLineToCpuDropPktCnt, &stat->DropPktCnt);
}

/******************************************************************
* rhAsicEnqueuerStats - Get RedHawk Enqueuer Statistics
*
* The routine gets the RedHawk Enqueuer statistics
*
* RETURNS: None
*/
void rhAsicEnqueuerStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     enqueuerStats *stat    /* Structure that holds the statistics */
     )
{
    STAT_INST(StsIntMemData_0, &stat->IntMemData_0);
    STAT_INST(StsIntMemData_1, &stat->IntMemData_1);
    STAT_INST(StsIntMemData_2, &stat->IntMemData_2);
    STAT_INST(StsIntMemData_3, &stat->IntMemData_3);
    STAT_INST(StsIntMemData_4, &stat->IntMemData_4);
    STAT_INST(StsIntMemData_5, &stat->IntMemData_5);
    STAT_INST(StsIntMemData_6, &stat->IntMemData_6);
    STAT_INST(StsIntMemData_7, &stat->IntMemData_7);
    STAT_INST(StsIntMemCurrentRdAddress, &stat->IntMemCurrentRdAddress);
    STAT_INST(StsIntMemCurrentWrAddress, &stat->IntMemCurrentWrAddress);
    STAT_INST(StsEnqIgrPktCnt, &stat->EnqIgrPktCnt);
    STAT_INST(StsEnqEgrPktCnt, &stat->EnqEgrPktCnt);
    STAT_INST(StsEnqDropPktCnt, &stat->EnqDropPktCnt);
    STAT_INST(StsEnqDropPktCntQNum0, &stat->EnqDropPktCntQNum0);
    STAT_INST(StsEnqDropPktCntQNum1, &stat->EnqDropPktCntQNum1);
    STAT_INST(StsEnqDropPktCntQNum2, &stat->EnqDropPktCntQNum2);
    STAT_INST(StsEnqDropPktCntQNum3, &stat->EnqDropPktCntQNum3);
    STAT_INST(StsEnqDropPktCntQNum4, &stat->EnqDropPktCntQNum4);
    STAT_INST(StsEnqDropPktCntQNum5, &stat->EnqDropPktCntQNum5);
    STAT_INST(StsEnqDropPktCntQNum6, &stat->EnqDropPktCntQNum6);
    STAT_INST(StsEnqDropPktCntQNum7, &stat->EnqDropPktCntQNum7);
}

/******************************************************************
* rhAsicDualMemCtrlStats - Get RedHawk Dual Memory Control Statistics
*
* The routine gets the RedHawk Dual Memory Control statistics
*
* RETURNS: None
*/
void rhAsicDualMemCtlStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     dualMemCtlStats *stat  /* Structure that holds the statistics */
     )
{
    STAT_INST(StsExtMemData_0, &stat->ExtMemData_0);
    STAT_INST(StsExtMemData_1, &stat->ExtMemData_1);
    STAT_INST(StsExtMemData_2, &stat->ExtMemData_2);
    STAT_INST(StsExtMemData_3, &stat->ExtMemData_3);
    STAT_INST(StsExtMemData_4, &stat->ExtMemData_4);
    STAT_INST(StsExtMemData_5, &stat->ExtMemData_5);
    STAT_INST(StsExtMemData_6, &stat->ExtMemData_6);
    STAT_INST(StsExtMemData_7, &stat->ExtMemData_7);
    STAT_INST(StsExtMemCurrentRdAddress, &stat->ExtMemCurrentRdAddress);
    STAT_INST(StsExtMemCurrentWrAddress, &stat->ExtMemCurrentWrAddress);
    STAT_INST(StsInitFCRAM, &stat->InitFCRAM);
    STAT_INST(StsMemAccessInterrupt, &stat->MemAccessInterrupt);
    STAT_INST(StsMemAccessInterruptMask, &stat->MemAccessInterruptMask);
}

/******************************************************************
* rhAsicQueueManagerStats - Get RedHawk Queue Manager Statistics
*
* The routine gets the RedHawk Queue Manager statistics
*
* RETURNS: None
*/
void rhAsicQueueManagerStats (
     reginfo_t *regdb,       /* pointer to the register database */
     int port,               /* port number */
     queueManagerStats *stat /* Structure that holds the statistics */
     )
{
    int i;
    STAT_INST(StsMaxPageCountRd, &stat->MaxPageCountRd);
    STAT_INST(StsRsvdPageCountRd, &stat->RsvdPageCountRd);
    STAT_INST(StsRsvdPoolPagePntr, &stat->RsvdPoolPagePntr);
    STAT_INST(StsFreePoolPagePntr, &stat->FreePoolPagePntr);
    STAT_INST(StsMemoryFullCount, &stat->MemoryFullCount);

    /* Update the QFill Counters */
    regSet (regdb, CfgQueueManagerEnable, port, 1);
    for (i=0; i<8; i++) {
        regSet (regdb, CfgQueueFillReadQnum, port, i);
        regGet (regdb, StsQueueFillLevel, port, &stat->qfillCount[i]);
    }

    /* Update the Used PAGE Counters */
    regSet (regdb, CfgQueueManagerEnable, port, 2);
    for (i=0; i<8; i++) {
        regSet (regdb, CfgUsedPageCountRdQnum, port, i);
        regGet (regdb, StsUsedPageCountRd, port, &stat->usedPageCount[i]);
    }

    /* Disabling the Queue Mananger */
    regSet (regdb, CfgQueueManagerEnable, port, 0);
}

/******************************************************************
* rhAsicDequeuerStats - Get RedHawk Dequeuer Statistics
*
* The routine gets the RedHawk Dequeuer statistics
*
* RETURNS: None
*/
void rhAsicDequeuerStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     DequeuerStats *stat    /* Structure that holds the statistics */
     )
{
    STAT_INST(StsDeqTailDropCount, &stat->TailDropCount);
    STAT_INST(StsDeqEOFCount, &stat->EOFCount);
    STAT_INST(StsDeqLpbkEOFCount, &stat->LpbkEOFCount);
    STAT_INST(StsDeqPktCountQ0, &stat->PktCountQ0);
    STAT_INST(StsDeqPktCountQ1, &stat->PktCountQ1);
    STAT_INST(StsDeqPktCountQ2, &stat->PktCountQ2);
    STAT_INST(StsDeqPktCountQ3, &stat->PktCountQ3);
    STAT_INST(StsDeqPktCountQ4, &stat->PktCountQ4);
    STAT_INST(StsDeqPktCountQ5, &stat->PktCountQ5);
    STAT_INST(StsDeqPktCountQ6, &stat->PktCountQ6);
    STAT_INST(StsDeqPktCountQ7, &stat->PktCountQ7);
    STAT_INST(StsDeqExcessLatencyDropCountQ0, &stat->ExcessLatencyDropCountQ0);
    STAT_INST(StsDeqExcessLatencyDropCountQ1, &stat->ExcessLatencyDropCountQ1);
    STAT_INST(StsDeqExcessLatencyDropCountQ2, &stat->ExcessLatencyDropCountQ2);
    STAT_INST(StsDeqExcessLatencyDropCountQ3, &stat->ExcessLatencyDropCountQ3);
    STAT_INST(StsDeqExcessLatencyDropCountQ4, &stat->ExcessLatencyDropCountQ4);
    STAT_INST(StsDeqExcessLatencyDropCountQ5, &stat->ExcessLatencyDropCountQ5);
    STAT_INST(StsDeqExcessLatencyDropCountQ6, &stat->ExcessLatencyDropCountQ6);
    STAT_INST(StsDeqExcessLatencyDropCountQ7, &stat->ExcessLatencyDropCountQ7);
}

/******************************************************************
* rhAsicRxpSpiStats - Get RedHawk receive Primary SPI Statistics
*
* The routine gets the RedHawk receive Primary SPI statistics
*
* RETURNS: None
*/
void rhAsicRxpSpiStats (
     reginfo_t *regdb,      /* pointer to the register database */
     rxpSpiStats *stat      /* Structure that holds the statistics */
     )
{
    int i;

    STAT(StsRpSpiPLLLockDet, &stat->RpSpiPLLLockDet);
    STAT(StsRegRxpSpiInFifoEopCnt, &stat->RxpSpiInFifoEopCnt);

    /* These registers have more than 2 instances */
    for (i=0; i<5; i++) {
        regGet(regdb, StsRegRxpSpiSopCount, i, &stat->RxpSpiSopCount[i]);
        regGet(regdb, StsRegRxpSpiEop1Count, i, &stat->RxpSpiEop1Count[i]);
        regGet(regdb, StsRegRxpSpiEop2Count, i, &stat->RxpSpiEop2Count[i]);
        regGet(regdb, StsRegRxpSpiEopACount, i, &stat->RxpSpiEopACount[i]);
        regGet(regdb, StsRegRxpSpiMdrrCreditCntr, i, &stat->RxpSpiMdrrCreditCntr[i]);
        regGet(regdb, StsRegRxpSpiPortBurstCntr, i, &stat->RxpSpiPortBurstCntr[i]);
    }

    STAT(StsRegRxpSpiTrainingCount, &stat->RxpSpiTrainingCount);
    STAT(StsRegRxpSpiPerFetchFifoUFlow, &stat->RxpSpiPerFetchFifoUFlow);
    STAT(StsRegRxpSpiDiag, &stat->RxpSpiDiag);
}

/******************************************************************
* rhAsicRxSSpiStats - Get RedHawk receive Secondary SPI Statistics
*
* The routine gets the RedHawk receive Secondary SPI statistics
*
* RETURNS: None
*/
void rhAsicRxSSpiStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     rxSSpiStats *stat      /* Structure that holds the statistics */
     )
{
    STAT(StsRsSpiPLLLockDet, &stat->RsSpiPLLLockDet);
    STAT(StsRegRxsSpiInFifoEopCnt, &stat->RxsSpiInFifoEopCnt);
    STAT_INST(StsRegRxsSpiSopCount, &stat->RxsSpiSopCount);
    STAT_INST(StsRegRxsSpiEop1Count, &stat->RxsSpiEop1Count);
    STAT_INST(StsRegRxsSpiEop2Count, &stat->RxsSpiEop2Count);
    STAT_INST(StsRegRxsSpiEopACount, &stat->RxsSpiEopACount);
    STAT(StsRegRxsSpiTrainingCount, &stat->RxsSpiTrainingCount);
    STAT_INST(StsRegRxsSpiMdrrCreditCntr, &stat->RxsSpiMdrrCreditCntr);
    STAT_INST(StsRegRxsSpiPortBurstCntr, &stat->RxsSpiPortBurstCntr);
    STAT(StsRegRxsSpiDiag, &stat->RxsSpiDiag);
    STAT(StsRegRxsSpiPerFetchFifoUFlow, &stat->RxsSpiPerFetchFifoUFlow);
    STAT(StsRegRxsSpiDip2ErrCount, &stat->RxsSpiDip2ErrCount);
}

/******************************************************************
* rhAsicRxXauiXMacStats - Get RedHawk receive XAUI XMAC Statistics
*
* The routine gets the RedHawk receive XAUI XMAC statistics
*
* RETURNS: None
*/
void rhAsicRxXauiXMacStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     rxXauiXMacStats *stat  /* Structure that holds the statistics */
     )
{
    STAT_INST(StsRxXauiXmacSopInCnt, &stat->RxXauiXmacSopInCnt);
    STAT_INST(StsRxXauiXmacEopInCnt, &stat->RxXauiXmacEopInCnt);
    STAT_INST(StsRxXauiXmacSopOutCnt, &stat->RxXauiXmacSopOutCnt);
    STAT_INST(StsRxXauiXmacEopOutCnt, &stat->RxXauiXmacEopOutCnt);
    STAT_INST(StsRegLsbRxXauiXmacByteCount, &stat->LsbRxXauiXmacByteCount);
    STAT_INST(StsRegMsbRxXauiXmacByteCount, &stat->MsbRxXauiXmacByteCount);
    STAT_INST(StsRegRxXauiXmacFrames, &stat->RxXauiXmacFrames);
    STAT_INST(StsRegRxXauiXmacErroredFrames, &stat->RxXauiXmacErroredFrames);
    STAT_INST(StsRegRxRSInterrupt, &stat->RxRSInterrupt);
    STAT_INST(StsRegRxRSInterruptMask, &stat->RxRSInterruptMask);
}

/******************************************************************
* rhAsicTxMacStats - Get RedHawk transmit MAC Statistics
*
* The routine gets the RedHawk transmit MAC statistics
*
* RETURNS: None
*/
void rhAsicTxMacStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     txMacStats *stat       /* Structure that holds the statistics */
     )
{
    STAT_INST(StsRegLsbTxGoodByteCount, &stat->LsbGoodByteCount);
    STAT_INST(StsRegMsbTxGoodByteCount, &stat->MsbGoodByteCount);
    STAT_INST(StsRegLsbTxErrorByteCount, &stat->LsbErrorByteCount);
    STAT_INST(StsRegMsbTxErrorByteCount, &stat->MsbErrorByteCount);
    STAT_INST(StsRegGoodTxFrames, &stat->GoodFrames);
    STAT_INST(StsRegTxBCASTFrames, &stat->BCASTFrames);
    STAT_INST(StsRegTxMCASTFrames, &stat->MCASTFrames);
    STAT_INST(StsRegTxControlFrames, &stat->ControlFrames);
    STAT_INST(StsRegTxVLANFrames, &stat->VLANFrames);
    STAT_INST(StsRegTxPauseFrames, &stat->PauseFrames);
    STAT_INST(StsRegTx64BFrames, &stat->Frames64B);
    STAT_INST(StsRegTx65to127BFrames, &stat->Frames65to127B);
    STAT_INST(StsRegTx128to255BFrames, &stat->Frames128to255B);
    STAT_INST(StsRegTx256to511BFrames, &stat->Frames256to511B);
    STAT_INST(StsRegTx512to1023BFrames, &stat->Frames512to1023B);
    STAT_INST(StsRegTx1024to1518BFrames, &stat->Frames1024to1518B);
    STAT_INST(StsRegTxOver1518BFrames, &stat->Over1518BFrames);
    STAT_INST(StsRegTxErroredFrames, &stat->ErroredFrames);
    STAT_INST(StsRegTxFilterDropFrames, &stat->FilterDropFrames);
    STAT_INST(StsRegTxMcastFilterDrop, &stat->McastFilterDrop);
    STAT_INST(StsRegTxBcastFilterDrop, &stat->BcastFilterDrop);
    STAT_INST(StsRegTxTooLongFrames, &stat->TooLongFrames);
    STAT_INST(StsRegTxDroppedFrames, &stat->DroppedFrames);
    STAT_INST(StsRegTxJumboFrames, &stat->JumboFrames);
    STAT_INST(StsRegTxFCSError, &stat->FCSError);
    STAT_INST(StsRegTxMACInterrupt, &stat->MACInterrupt);
    STAT_INST(StsRegTxMACInterruptMask, &stat->MACInterruptMask);
    STAT_INST(StsRegTxDiagPort, &stat->DiagPort);
}

/******************************************************************
* rhAsicTxVlanCtrlStats - Get RedHawk transmit VLAN Control Statistics
*
* The routine gets the RedHawk transmit VLAN Control statistics
*
* RETURNS: None
*/
void rhAsicTxVlanCtrlStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     txVlanCtrlStats *stat  /* Structure that holds the statistics */
     )
{
    STAT_INST(StsRdDataTxVlanCtrlTblRamReg, &stat->RdDataTxVlanCtrlTblRamReg);
    STAT_INST(StsRdDataVlanTagRamReg, &stat->RdDataVlanTagRamReg);
    STAT_INST(StsTxVlanCtrlSopInCnt, &stat->TxVlanCtrlSopInCnt);
    STAT_INST(StsTxVlanCtrlEopInCnt, &stat->TxVlanCtrlEopInCnt);
    STAT_INST(StsTxVlanCtrlSopOutCnt, &stat->TxVlanCtrlSopOutCnt);
    STAT_INST(StsTxVlanCtrlEopOutCnt, &stat->TxVlanCtrlEopOutCnt);
    STAT_INST(StsMPLSUnicastFrameCount, &stat->MPLSUnicastFrameCount);
    STAT_INST(StsMPLSMulticastFrameCount, &stat->MPLSMulticastFrameCount);
    STAT_INST(StsMPLSFrameOctetsEgressed, &stat->MPLSFrameOctetsEgressed);
    STAT_INST(StsNoVLANTagFrameCount, &stat->NoVLANTagFrameCount);
    STAT_INST(StsSingleVLANTagFrameCount, &stat->SingleVLANTagFrameCount);
    STAT_INST(StsDoubleVLANTagFrameCount, &stat->DoubleVLANTagFrameCount);
    STAT_INST(StsVLANControlTableFrameCount, &stat->VLANControlTableFrameCount);
    STAT_INST(StsDefaultVLANControlTableFrameCount, &stat->DefaultVLANControlTableFrameCount);
    STAT_INST(StsVLANControlTableTagOperationFrameCount, &stat->VLANControlTableTagOperationFrameCount);
    STAT_INST(StsEfhTagOperationFrameCount, &stat->EfhTagOperationFrameCount);
    STAT_INST(StsPreservedFrameCount, &stat->PreservedFrameCount);
}

/******************************************************************
* rhAsicTxMemManagerStats - Get RedHawk transmit Memory Manager Statistics
*
* The routine gets the RedHawk transmit Memory Manager statistics
*
* RETURNS: None
*/
void rhAsicTxMemManagerStats (
     reginfo_t *regdb,       /* pointer to the register database */
     int port,               /* port number */
     txMemManagerStats *stat /* Structure that holds the statistics */
     )
{
    STAT_INST(StsTxMemMgrEgrPktCnt, &stat->MemMgrEgrPktCnt);
    STAT_INST(StsTxMemMgrDropPktCnt, &stat->MemMgrDropPktCnt);
    STAT_INST(StsTxVlanCtrlPktCrcErrCnt, &stat->VlanCtrlPktCrcErrCnt);
    STAT_INST(StsEgressSpiErrDropCnt, &stat->EgressSpiErrDropCnt);
    STAT_INST(StsTxMemMgrOneLinePktsDropedCnt, &stat->MemMgrOneLinePktsDropedCnt);
    STAT_INST(StsTxVlanCtrlEfhFcsErrCnt, &stat->VlanCtrlEfhFcsErrCnt);
    STAT_INST(StsRedHawkIdMisMatchCnt, &stat->RedHawkIdMisMatchCnt);
}

/******************************************************************
* rhAsicTxMemCommonStats - Get RedHawk transmit Memory Common Statistics
*
* The routine gets the RedHawk transmit Memory Common statistics
*
* RETURNS: None
*/
void rhAsicTxMemCommonStats (
     reginfo_t *regdb,      /* pointer to the register database */
     txMemCommonStats *stat /* Structure that holds the statistics */
     )
{
    STAT(StsWidConSopEopSameLineDropCntP0, &stat->WidConSopEopSameLineDropCntP0);
    STAT(StsWidConSopEopSameLineDropCntP1, &stat->WidConSopEopSameLineDropCntP1);
    STAT(StsTxMemMgrSPIMaxSzPktDrpCntPrt0, &stat->TxMemMgrSPIMaxSzPktDrpCntPrt0);
    STAT(StsTxMemMgrSPIMaxSzPktDrpCntPrt1, &stat->TxMemMgrSPIMaxSzPktDrpCntPrt1);
    STAT(StsTxMemMgrSPIMinSzPktDrpCntPrt0, &stat->TxMemMgrSPIMinSzPktDrpCntPrt0);
    STAT(StsTxMemMgrSPIMinSzPktDrpCntPrt1, &stat->TxMemMgrSPIMinSzPktDrpCntPrt1);
}

/******************************************************************
* rhAsicTxCpuToLineStats - Get RedHawk transmit CPU To Line Statistics
*
* The routine gets the RedHawk transmit CPU To Line statistics
*
* RETURNS: None
*/
void rhAsicTxCpuToLineStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     txCpuToLineStats *stat /* Structure that holds the statistics */
     )
{
    STAT_INST(StsCpuToLineDropPktCnt, &stat->DropPktCnt);
    STAT_INST(StsCpuToLineWritePointer, &stat->WritePointer);
    STAT_INST(StsCpuToLineReadPointer, &stat->ReadPointer);
    STAT_INST(StsCpuToLineCommitPointer, &stat->CommitPointer);
}

/******************************************************************
* rhAsicTxpSpiStats - Get RedHawk transmit Primary SPI Statistics
*
* The routine gets the RedHawk transmit Primary SPI statistics
*
* RETURNS: None
*/
void rhAsicTxpSpiStats (
     reginfo_t *regdb,      /* pointer to the register database */
     txpSpiStats *stat      /* Structure that holds the statistics */
     )
{
    STAT(StsRegTSpiTrainingCount, &stat->TSpiTrainingCount);
    STAT(StsRegTSpiSopCount, &stat->TSpiSopCount);
    STAT(StsRegTSpiEopCount, &stat->TSpiEopCount);
    STAT(StsRegTSpiExtEopACount, &stat->TSpiExtEopACount);
    STAT(StsRegTSpiIntEopACount, &stat->TSpiIntEopACount);
    STAT(StsRegTSpiDip4ErrCount, &stat->TSpiDip4ErrCount);
    STAT(StsRegTSpiProtViolCount, &stat->TSpiProtViolCount);
    STAT(StsRegTSpiInterrupt, &stat->TSpiInterrupt);
    STAT(StsRegTSpiInterruptMask, &stat->TSpiInterruptMask);
    STAT(StsRegTSpiFifoOverFlow, &stat->TSpiFifoOverFlow);
    STAT(StsRegTSpiDiag, &stat->TSpiDiag);
    STAT(StsTxPSpiDPGStatus, &stat->PSpiDPGStatus);
    STAT(StsTxPSpiDPVBitCnt, &stat->PSpiDPVBitCnt);
    STAT(StsTxPSpiDPVErrorCnt, &stat->PSpiDPVErrorCnt);
    STAT(StsTxPSpiDPVCRCErrorCnt, &stat->PSpiDPVCRCErrorCnt);
    STAT(StsTxPSpiDPVGoodPktCnt, &stat->PSpiDPVGoodPktCnt);
    STAT(StsTxPSpiDPVSyncOnCnt, &stat->PSpiDPVSyncOnCnt);
    STAT(StsTxPSpiDPVEopCnt, &stat->PSpiDPVEopCnt);
    STAT(StsTxPSpiCh0DropCount, &stat->PSpiCh0DropCount);
    STAT(StsTxPSpiCh1DropCount, &stat->PSpiCh1DropCount);
    STAT(StsTxPSpiLpbkPktDropCount, &stat->PSpiLpbkPktDropCount);
    STAT(StsTxPSpiXauiPktDropCount, &stat->PSpiXauiPktDropCount);
    STAT(StsTxPSpiEopCountCh0, &stat->PSpiEopCountCh0);
    STAT(StsTxPSpiEopCountCh1, &stat->PSpiEopCountCh1);
    STAT(StsTxPSpiEopCountCh2, &stat->PSpiEopCountCh2);
    STAT(StsTxPSpiEopCountCh3, &stat->PSpiEopCountCh3);
}

/******************************************************************
* rhAsicTxsSpiStats - Get RedHawk transmit Secondary SPI Statistics
*
* The routine gets the RedHawk Shadow statistics
*
* RETURNS: None
*/
void rhAsicTxsSpiStats (
     reginfo_t *regdb,      /* pointer to the register database */
     txsSpiStats *stat      /* Structure that holds the statistics */
     )
{
    STAT(StsRegTxSSpiTrainingCount, &stat->SSpiTrainingCount);
    STAT(StsRegTxSSpiSopCount, &stat->SSpiSopCount);
    STAT(StsRegTxSSpiEopCount, &stat->SSpiEopCount);
    STAT(StsRegTxSSpiExtEopACount, &stat->SSpiExtEopACount);
    STAT(StsRegTxSSpiIntEopACount, &stat->SSpiIntEopACount);
    STAT(StsRegTxSSpiDip4ErrCount, &stat->SSpiDip4ErrCount);
    STAT(StsRegTxSSpiProtViolCount, &stat->SSpiProtViolCount);
    STAT(StsRegTxSSpiInterrupt, &stat->SSpiInterrupt);
    STAT(StsRegTxSSpiInterruptMask, &stat->SSpiInterruptMask);
    STAT(StsRegTxSSpiFifoOverFlow, &stat->SSpiFifoOverFlow);
    STAT(StsRegTxSSpiDiag, &stat->SSpiDiag);
    STAT(StsTxSSpiDPGStatus, &stat->SSpiDPGStatus);
    STAT(StsTxSSpiDPVBitCnt, &stat->SSpiDPVBitCnt);
    STAT(StsTxSSpiDPVErrorCnt, &stat->SSpiDPVErrorCnt);
    STAT(StsTxSSpiDPVCRCErrorCnt, &stat->SSpiDPVCRCErrorCnt);
    STAT(StsTxSSpiDPVGoodPktCnt, &stat->SSpiDPVGoodPktCnt);
    STAT(StsTxSSpiDPVSyncOnCnt, &stat->SSpiDPVSyncOnCnt);
    STAT(StsTxSSpiDPVEopCnt, &stat->SSpiDPVEopCnt);
    STAT(StsTxSSpiCh0PktDropCount, &stat->SSpiCh0PktDropCount);
    STAT(StsTxSSpiCh1PktDropCount, &stat->SSpiCh1PktDropCount);
    STAT(StsTxSSpiLpbkPktDropCount, &stat->SSpiLpbkPktDropCount);
    STAT(StsTxSSpiEopCountCh0, &stat->SSpiEopCountCh0);
    STAT(StsTxSSpiEopCountCh1, &stat->SSpiEopCountCh1);
    STAT(StsTxSSpiEopCountCh2, &stat->SSpiEopCountCh2);
}

/******************************************************************
* rhAsicTxXauiXMacStats - Get RedHawk transmit XAUI XMAC Statistics
*
* The routine gets the RedHawk transmit XAUI XMAC statistics
*
* RETURNS: None
*/
void rhAsicTxXauiXMacStats (
     reginfo_t *regdb,      /* pointer to the register database */
     int port,              /* port number */
     txXauiXMacStats *stat  /* Structure that holds the statistics */
     )
{
    STAT_INST(StsRegTxXauiXmacSopInCnt, &stat->XauiXmacSopInCnt);
    STAT_INST(StsRegTxXauiXmacEopInCnt, &stat->XauiXmacEopInCnt);
    STAT_INST(StsRegTxXauiXmacSopOutCnt, &stat->XauiXmacSopOutCnt);
    STAT_INST(StsRegTxXauiXmacEopOutCnt, &stat->XauiXmacEopOutCnt);
    STAT_INST(StsRegLsbTxXauiXmacByteCount, &stat->LsbTxXauiXmacByteCount);
    STAT_INST(StsRegMsbTxXauiXmacByteCount, &stat->MsbTxXauiXmacByteCount);
    STAT_INST(StsRegTxXauiXmacFrames, &stat->XauiXmacFrames);
    STAT_INST(StsRegTxXauiXmacErroredFrames, &stat->XauiXmacErroredFrames);
}

/******************************************************************
* rhAsicTxsSpiMtuAccessStats - Get RedHawk transmit Secondary SPI MTU Access Statistics
*
* The routine gets the RedHawk transmit Secondary SPI MTU Access statistics
*
* RETURNS: None
*/
void rhAsicTxsSpiMtuAccessStats (
     reginfo_t *regdb,          /* pointer to the register database */
     txsSpiMtuAccessStats *stat /* Structure that holds the statistics */
     )
{
    STAT(StsRegTailDropCount1, &stat->TailDropCount1);
}

/* VLAN Routines */
void rhAsicConfigVlanId (
	int portNum
	)
{
	int initialId = 0x82000001;
	int numLoc, tempId;

	for (numLoc=0; numLoc<64; numLoc++) {
		tempId = numLoc + initialId;
		regSet (redHawkRegs, CfgVLANIDData, portNum, tempId);
		regSet (redHawkRegs, CfgVLANID__Addr, portNum, numLoc);
		regSet (redHawkRegs, CfgVLANID__Wr, portNum, 1);
	}
	regSet (redHawkRegs, CfgVLANID__Wr, portNum, 0);
}

void rhAsicConfigVlanEType (
	int portNum
	)
{
    /* 8100 to 810f Ethertype configuration */
    regSet (redHawkRegs, CfgVLANEtherTypeE0, portNum, 0x00028100);
    regSet (redHawkRegs, CfgVLANEtherTypeE1, portNum, 0x00028101);
    regSet (redHawkRegs, CfgVLANEtherTypeE2, portNum, 0x00028102);
    regSet (redHawkRegs, CfgVLANEtherTypeE3, portNum, 0x00028103);
    regSet (redHawkRegs, CfgVLANEtherTypeE4, portNum, 0x00028104);
    regSet (redHawkRegs, CfgVLANEtherTypeE5, portNum, 0x00028105);
    regSet (redHawkRegs, CfgVLANEtherTypeE6, portNum, 0x00028106);
    regSet (redHawkRegs, CfgVLANEtherTypeE7, portNum, 0x00028107);
    regSet (redHawkRegs, CfgVLANEtherTypeE8, portNum, 0x00028108);
    regSet (redHawkRegs, CfgVLANEtherTypeE9, portNum, 0x00028109);
    regSet (redHawkRegs, CfgVLANEtherTypeE10, portNum, 0x0002810A);
    regSet (redHawkRegs, CfgVLANEtherTypeE11, portNum, 0x0002810B);
    regSet (redHawkRegs, CfgVLANEtherTypeE12, portNum, 0x0002810C);
    regSet (redHawkRegs, CfgVLANEtherTypeE13, portNum, 0x0002810D);
    regSet (redHawkRegs, CfgVLANEtherTypeE14, portNum, 0x0002810E);
    regSet (redHawkRegs, CfgVLANEtherTypeE15, portNum, 0x0002810F);
}

void rhAsicConfigIVLANTable (
	int portNum,
	int opId
	)
{
	regSet (redHawkRegs, CfgNoVLANCtrl1, portNum, 0x00000080);
	regSet (redHawkRegs, CfgFilters__VLANEtherTypeFilterEn, portNum, 1);
	regSet (redHawkRegs, CfgFilters__TpLenFieldFilterEn, portNum, 1);
	regSet (redHawkRegs, CfgFilters__LengthCheckEn, portNum, 1);
	regSet (redHawkRegs, CfgFilters__InnerVLANEn, portNum, 1);
	if (opId == 0) {
		/* No Tag operation TagOp = 0 */
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000001);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10000000);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000003);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10200000);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000005);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10400000);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000007);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10600000);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000009);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10800000);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000b);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10a00000);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000d);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10c00000);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000f);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10e00000);
	} else if (opId == 1) {
		/* Pop Tag operation TagOp = 1 */
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000001);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10000600);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000003);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10200600);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000005);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10400600);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000007);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10600600);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000009);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10800600);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000b);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10a00600);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000d);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10c00600);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000f);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10e00600);
	} else if (opId == 3) {
		/* Push Tag operation TagOp = 'd3 */
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000001);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10000C00);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000003);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10200C00);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000005);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10400C00);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000007);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10600C00);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000009);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10800C00);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000b);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10a00C00);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000d);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10c00C00);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000f);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10e00C00);
	} else if (opId == 6) {
		/* SWAP Tag operation TagOp = 'd6 */
		/* Index I is configured 0 thru 7  */
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000001);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10001800);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000003);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10203800);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000005);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10405800);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000007);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10607800);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000009);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10809800);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000b);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10a0B800);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000d);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10c0D800);
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x0000000f);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x10e0F800);
	}
}

void rhAsicConfigOVLANTable (
	int portNum,
	int opId
	)
{
	regSet (redHawkRegs, CfgNoVLANCtrl1, portNum, 0x00000080);
	regSet (redHawkRegs, CfgFilters__OuterVLANEn, portNum, 1);

	if (opId == 0) {
		/* No Tag operation TagOp = 0 */
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000001);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10000000);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000003);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10200000);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000005);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10400000);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000007);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10600000);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000009);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10800000);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000b);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10a00000);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000d);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10c00000);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000f);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10e00000);
	} else if (opId == 1) {
		/* Single Pop Tag operation TagOp = 1 */
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000001);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10000600);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000003);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10200600);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000005);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10400600);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000007);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10600600);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000009);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10800600);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000b);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10a00600);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000d);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10c00600);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000f);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10e00600);
	} else if (opId == 2) {
		/* Double POP Tag operation TagOp = 'd2 */
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000001);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10000400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000003);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10200400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000005);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10400400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000007);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10600400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000009);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10800400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000b);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10a00400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000d);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10c00400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000f);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10e00400);
	} else if (opId == 6) {
		/* SWAP OUTER Tag operation TagOp = 'd6 */
		/* Index I is configured 0 thru 7  */
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000001);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10001800);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000003);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10203800);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000005);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10405800);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000007);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10607800);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000009);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10809800);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000b);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10a0B800);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000d);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10c0D800);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000f);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10e0F800);
	} else if (opId == 5) {
		/* SWAP INNER Tag operation TagOp = 'd5 */
		/* Index I is configured 0 thru 7  */
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000001);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10001400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000003);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10203400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000005);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10405400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000007);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10607400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000009);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10809400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000b);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10a0B400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000d);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10c0D400);
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x0000000f);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x10e0F400);
	}
}

void rhAsicConfigOVLAN (
	int portNum,
	int opId
	)
{
	rhAsicConfigVlanEType (portNum);
	rhAsicConfigVlanId (portNum);
	rhAsicConfigOVLANTable (portNum, opId);
	rhAsicConfigIVLANTable (portNum, 0);
}

void rhAsicConfigIVLAN (
	int portNum,
	int opId
	)
{
	rhAsicConfigVlanEType (portNum);
	rhAsicConfigVlanId (portNum);
	rhAsicConfigIVLANTable (portNum, opId);
}

void rhAsic8021POVLANConfiguration (
	int portNum
	)
{
	int addr;
	unsigned int regVal;

	/* NoVLAN */
	regSet (redHawkRegs, CfgNoVLANCtrl0, portNum, 0);
	regSet (redHawkRegs, CfgNoVLANCtrl1__Enable, portNum, 1);

	/* Outer VLAN  */
	regSet (redHawkRegs, CfgFilters__OuterVLANEn, portNum, 1);

	/* {111_110_101_100_011_010_000_001} */
	/* rearranging */
	/* {1111_1010_1100_0110_1000_0001} */
	regSet (redHawkRegs, CfgIngressPrioMap0, portNum, 0xFAC681);
	regSet (redHawkRegs, CfgIngressPrioMap1, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap2, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap3, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap4, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap5, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap6, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap7, portNum, 0xFFFFFF);

	regSet (redHawkRegs, CfgIngressPrioMap8, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap9, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap10, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap11, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap12, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap13, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap14, portNum, 0xFFFFFF);

	regSet (redHawkRegs, CfgIngressExtdPrioMap0, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressExtdPrioMap1, portNum, 0xFFFFFF);

	/* Programming all 4096 locations */
	for (addr=0; addr<4096; addr++) {
		regVal = (addr << 1) + 1; // Addr[12:1]; WriteBit[0]
		regSet (redHawkRegs, CfgOVLANCtrl, portNum, regVal);
		regSet (redHawkRegs, CfgOVLANCtrlData, portNum, 0x16000000);
	}

	/* Reset the write bit */
	regSet (redHawkRegs, CfgOVLANCtrl, portNum, 0x00000000);
}

void rhAsic8021PIVLANConfiguration (
	int portNum
	)
{
	int addr;
	unsigned int regVal;

	/* NoVLAN */
	regSet (redHawkRegs, CfgNoVLANCtrl0, portNum, 0x00000000);
	regSet (redHawkRegs, CfgNoVLANCtrl1__Enable, portNum, 1);

	/* Inner VLAN  */
	regSet (redHawkRegs, CfgFilters__InnerVLANEn, portNum, 1);

	/* {111_110_101_100_011_010_000_001} */
	/* rearranging */
	/* {1111_1010_1100_0110_1000_0001} */
	regSet (redHawkRegs, CfgIngressPrioMap0, portNum, 0xFAC681);
	regSet (redHawkRegs, CfgIngressPrioMap1, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap2, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap3, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap4, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap5, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap6, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap7, portNum, 0xFFFFFF);

	regSet (redHawkRegs, CfgIngressPrioMap8, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap9, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap10, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap11, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap12, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap13, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressPrioMap14, portNum, 0xFFFFFF);

	regSet (redHawkRegs, CfgIngressExtdPrioMap0, portNum, 0xFFFFFF);
	regSet (redHawkRegs, CfgIngressExtdPrioMap1, portNum, 0xFFFFFF);

	/* Programming all 4096 locations */
	for (addr=0; addr<4096; addr++) {
		regVal = (addr << 1) + 1; // Addr[12:1]; WriteBit[0]
		regSet (redHawkRegs, CfgIVLANCtrl, portNum, regVal);
		regSet (redHawkRegs, CfgIVLANCtrlData, portNum, 0x14000000);
	}

	/* Reset the write bit */
	regSet (redHawkRegs, CfgIVLANCtrl, portNum, 0x00000000);
}

/*************************************************************************
 *
 * RedHawk ASIC MDIO Functions
 *
 *************************************************************************/

/******************************************************************
* rhAsicMdioRead - Read Xenpak, internal XAUI and XFI Cores using RedHawk MDIO
*
* This routine is used for reading XENPAK, internal XAUI and XFI core register using RedHawk MDIO
*
* RETURNS: Status of the MDIO operation; OK or ERROR
*/
int rhAsicMdioRead (
    unsigned int portAddr,  /* PHY address */
    unsigned int regAddr,   /* register address */
    unsigned int devAddr,   /* device address */
    unsigned int *regVal    /* Data Read */
    )
{
    unsigned int cmd;
    unsigned int mdioBusy;
    unsigned int data;
    reginfo_t *regdb;           /* RedHawk register database */
    int status;

    /* Waiting for Initiali MDIO transaction to get completed */
    while (1) {
        if (!mdioInterfaceBusy) {
            mdioInterfaceBusy = 1;
            break;
        }
    }

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* activate MDIO */
    regGet(regdb, StsRegMDIOInterrupt, 0, &data); /* Clearing the interrupts */

    /* Address Phase for the MDIO */
    cmd = 0 | (MDIO_OP_ADDR << 2) | (portAddr << 4) | (devAddr << 9) | (regAddr << 14) ;
    regSet(regdb, VarRegMDIOCommand, 0, cmd);

    /* Wait for the Command done interrupt */
    data = 0;
    while (data == 0)
        regGet(regdb, StsRegMDIOInterrupt, 0, &data);

    /* Data Phase for the MDIO */
    cmd = 0 | (MDIO_OP_READ << 2) | (portAddr << 4) | (devAddr << 9);
    regSet(regdb, VarRegMDIOCommand, 0, cmd);

    /* Wait for the Command done interrupt */
    data = 0;
    while (data == 0)
        regGet(regdb, StsRegMDIOInterrupt, 0, &data);

    /* generate MDIO read */
    mdioBusy = 1;
    while (mdioBusy)
        regGet(regdb, StsRegMDIOBusy, 0, &mdioBusy);

    *regVal = 0; /* Variable for holding the MDIO Data */

    status = regGet(regdb, StsRegMDIOData, 0, regVal);

#ifdef NOTNOW
    osPrintf("MDIO READ : Value read from %d is 0x%.4x\n", regAddr, *regVal);
#endif

    mdioInterfaceBusy = 0;
    return(status);
}

/******************************************************************
* rhAsicMdioWrite - Write to a XENPAK, Internal XAUI and XFI core register using RedHawk MDIO
*
* This routine is used for writing to a XENPAK, Internal XAUI and XFI core register using RedHawk MDIO
*
* RETURNS: None
*/
int rhAsicMdioWrite (
    unsigned int portAddr, /* PHY address */
    unsigned int regAddr,  /* register address */
    unsigned int devAddr,  /* device address */
    unsigned short regVal  /* data to write */
    )
{
    unsigned int cmd;
    unsigned int data;
    reginfo_t *regdb;           /* RedHawk register database */

    /* Waiting for Initiali MDIO transaction to get completed */
    while (1) {
        if (!mdioInterfaceBusy) {
            mdioInterfaceBusy = 1;
            break;
        }
    }

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* activate MDIO */
    regGet(regdb, StsRegMDIOInterrupt, 0, &data); /* Clearing the interrupts */

    /* Address Phase for the MDIO */
    cmd = 0 | (MDIO_OP_ADDR << 2) | (portAddr << 4) | (devAddr << 9) | (regAddr << 14) ;
    regSet(regdb, VarRegMDIOCommand, 0, cmd);

    /* Wait for the Command done interrupt */
    data = 0;
    while (data == 0)
        regGet(regdb, StsRegMDIOInterrupt, 0, &data);

    /* Data Phase for the MDIO */
    cmd = 0 | (MDIO_OP_WRITE << 2) | (portAddr << 4) | (devAddr << 9) | (regVal << 14);
    regSet(regdb, VarRegMDIOCommand, 0, cmd);

    /* Wait for the Command done interrupt */
    data = 0;
    while (data == 0)
        regGet(regdb, StsRegMDIOInterrupt, 0, &data);

#ifdef NOTNOW
    osPrintf("MDIO WRITE : Value written to %d is 0x%.4x\n", regAddr, regVal);
#endif

    mdioInterfaceBusy = 0;

    return OK;
}

/******************************************************************
* ConfigMDIOMode - Configures the MDIO mode
*
* This routine is used for configuring the MDIO mode for accessing the
* registers of XAUI/ XFI modules.
*
* RETURNS: None
*/
void rhAsicConfigMDIOMode (
     int slave_type,  /* External/ Internal -- 1/ 0*/
     int slave_name,  /* XFI/ XAUI -- 1/ 0*/
     int port         /* Port Number */
     )
{
    /* Setting the CfgRegCoMDIOMode */
    if (slave_type == 0) {
        /* Change the clock of the MDIO */
        regSet(redHawkRegs, CfgRegCoClockDiv0__MDIOClk, 0, 0xe);

        /* Internal mode MDIO */
        if (slave_name == 0) {
            /* Settings for the XAUI module */
            if (port == 0)
                regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_2);
            else
                regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_3);
        } else {
            /* Settings for the XFI module */
            if (port == 0)
                regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_6);
            else
                regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_7);
        }
    } else {
        /* Checking for the xfi_mode */
        if (slave_name == 1) {
            osPrintf("ERROR : Don't support Internal Master, External Slave mode for XFI\n");
            return;
        }

        /* Change the clock of the MDIO */
        regSet(redHawkRegs, CfgRegCoClockDiv0__MDIOClk, 0, 0x1f);

        /* External mode MDIO */
        if (port == 0)
            regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_8);
        else
            regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_9);
    }
}

/*
 * mdioWrite - Basic MDIO write
 * Writes the value passed to the VarRegMDIOCommand register
 * Waits for the interrupt done and returns back
 * Used in the Configuration functions
 */
void mdioWrite ( unsigned int regVal )
{
    /* Write the regVal value to the VarRegMDIOCommand register */
    regSet(redHawkRegs, VarRegMDIOCommand, 0, regVal);

    regVal = 0;
    while (regVal == 0) {
        regGet(redHawkRegs, StsRegMDIOInterrupt, 0, &regVal);
    }

    osDelay(1000);
}

/*************************************************************************
 *
 * RedHawk ASIC Two Wire Interface Functions
 *
 *************************************************************************/

/******************************************************************
* rhAsicTwoWireSerialWrite - Write to the external XFP register using RedHawk Two
* Wire Interface
*
* This routine is used for writing an external XFP register using RedHawk Two
* Wire Interface
*
* RETURNS:
*    OK    : On Success
*    ERROR : On Failure
*/
int rhAsicTwoWireSerialWrite(
    int portNum,       /* Port Number */
    int address,       /* Register Address */
    unsigned int data  /* Data value */
    )
{
    int regAddr;
    int twsiBusy, twsiErr, tempBusy;
    int interruptMask;
    reginfo_t *regdb;           /* RedHawk register database */

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Check the port number and assign the values accordingly */
    if (portNum == 0) {
        twsiBusy = 1;
        twsiErr = 4;
        interruptMask = 2;
    } else /* if (portNum == 1) */ {
        twsiBusy = 2;
        twsiErr = 8;
        interruptMask = 1;
    }

    /* activate Two Wire Interface Interrupts */
    regSet(regdb, StsRegCo2wiremasterInterruptMask, 0, interruptMask);

    /* Get the address for the first byte and write data to the address */
    if (portNum == 0)
        regAddr = regdb[TwoWireMasterBaseAddress0].addr + address;
    else
        regAddr = regdb[TwoWireMasterBaseAddress1].addr + address;
    data = data & 0xff;
    if ((address & 0x3) == 2)
        data = data << 8;
    if ((address & 0x3) == 1)
        data = data << 16;
    if ((address & 0x3) == 0)
        data = data << 24;
    writeAddress(regAddr, data);

    /* Check for the Busy Signal */
    tempBusy = twsiBusy;
    while(tempBusy == twsiBusy)
        regGet(regdb, StsRegCo2wiremaster, 0, (unsigned int *)&tempBusy);

    /* Check for any error */
    if (tempBusy == twsiErr) {
        osPrintf("Error: External Wire Slave occured on XFI 2-Wire\n");
        return ERROR;
    }

    return OK;
}

/******************************************************************
* rhAsicTwoWireSerialRead - Read from an external XFP register using RedHawk Two
* Wire Interface
*
* This routine is used for reading an external XFP register using RedHawk Two
* Wire Interface
*
* RETURNS:
*    OK    : On Success
*    ERROR : On Failure
*/
int rhAsicTwoWireSerialRead (
    int portNum,       /* Port Number */
    int address,       /* Register Address */
    unsigned int *data /* Data value */
    )
{
    int regAddr;
    int twsiBusy, twsiErr, tempBusy;
    int interruptMask;
    int tempData;
    reginfo_t *regdb;           /* RedHawk register database */

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;
    *data = 0;

    /* Check the port number and assign the values accordingly */
    if (portNum == 0) {
        twsiBusy = 1;
        twsiErr = 4;
        interruptMask = 2;
    } else /* if (portNum == 1) */ {
        twsiBusy = 2;
        twsiErr = 8;
        interruptMask = 1;
    }

    /* activate Two Wire Interface Interrupts */
    regSet(regdb, StsRegCo2wiremasterInterruptMask, 0, interruptMask);

    /* Get the address for the first byte and write data to the address */
    if (portNum == 0)
        regAddr = regdb[TwoWireMasterBaseAddress0].addr + address;
    else
        regAddr = regdb[TwoWireMasterBaseAddress1].addr + address;
    readAddress(regAddr);

    /* Check for the Busy Signal */
    tempBusy = twsiBusy;
    while(tempBusy == twsiBusy)
        regGet(regdb, StsRegCo2wiremaster, 0, (unsigned int *)&tempBusy);

    /* Check for any error */
    if (tempBusy == twsiErr) {
        osPrintf("Error: External Wire Slave occured on XFI 2-Wire\n");
        return ERROR;
    }

    /* Get the specific read address and read the valid data */
    if (portNum == 0)
        regAddr = regdb[TwoWireMasterBaseAddress0].addr + 0x200;
    else
        regAddr = regdb[TwoWireMasterBaseAddress1].addr + 0x200;
    tempData = 0;
    tempData = readAddress(regAddr);
    if ((address & 0x3) == 0) {
        tempData = tempData & 0xff000000;
        *data = tempData >> 24;
    }
    if ((address & 0x3) == 1) {
        tempData = tempData & 0x00ff0000;
        *data = tempData >> 16;
    }
    if ((address & 0x3) == 2) {
        tempData = tempData & 0x0000ff00;
        *data = tempData >> 8;
    }
    if ((address & 0x3) == 3) {
        tempData = tempData & 0x000000ff;
        *data = tempData;
    }

    return OK;
}

/*************************************************************************
 *
 * RedHawk ASIC Memory Access Functions
 *
 *************************************************************************/

/******************************************************************
* rhAsicWriteDeqMem - Write to Dequeuer Memory Location
*
* This routine is used for writing to a Dequeuer Memory location
*
* RETURNS:
*     OK : On Success
*     ERROR : On Failure
*/
int rhAsicWriteDeqMem (
    int portNum,         /* Port Number */
    unsigned int addr,   /* Address */
    unsigned char *data  /* Data Value */
    )
{
    unsigned int tempData;
    reginfo_t *regdb;           /* RedHawk register database */

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Incorrect port number\n");
        return ERROR;
    }

    /* Enabling the CPUAccess bit in the register */
    regSet(regdb, CfgDeqCPUAccess, portNum, 1);

    /* Writing data to the respective registers */
    tempData = 0 | (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];
    regSet(regdb, CfgDeqCPUWriteData_0, portNum, tempData);

    tempData = 0 | (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];
    regSet(regdb, CfgDeqCPUWriteData_1, portNum, tempData);

    tempData = 0 | (data[8] << 24) | (data[9] << 16) | (data[10] << 8) | data[11];
    regSet(regdb, CfgDeqCPUWriteData_2, portNum, tempData);

    tempData = 0 | (data[12] << 24) | (data[13] << 16) | (data[14] << 8) | data[15];
    regSet(regdb, CfgDeqCPUWriteData_3, portNum, tempData);

    tempData = 0 | (data[16] << 24) | (data[17] << 16) | (data[18] << 8) | data[19];
    regSet(regdb, CfgDeqCPUWriteData_4, portNum, tempData);

    tempData = 0 | (data[20] << 24) | (data[21] << 16) | (data[22] << 8) | data[23];
    regSet(regdb, CfgDeqCPUWriteData_5, portNum, tempData);

    tempData = 0 | (data[24] << 24) | (data[25] << 16) | (data[26] << 8) | data[27];
    regSet(regdb, CfgDeqCPUWriteData_6, portNum, tempData);

    tempData = 0 | (data[28] << 24) | (data[29] << 16) | (data[30] << 8) | data[31];
    regSet(regdb, CfgDeqCPUWriteData_7, portNum, tempData);

    tempData = 0 | (data[32]<<8) | data[33];
    regSet(regdb, CfgDeqCPUWriteData_8, portNum, tempData);

    /* Writing the address to the respective register */
    regSet(regdb, CfgDeqCPUWriteAddress, portNum, addr);

    /* Enabling the Write bit in the CPU Access register */
    regSet(regdb, CfgDeqCPUAccess, portNum, 3);

    return OK;
}

/*
 * Routine sets the Commit pointer in the Dequeuer memory
 * Parameters :
 *     Port Number - Specifies for which port number the action has to be taken
 *     Address - Specifies the address to which the commit pointer to be set
 *
 * Returns :
 *     OK on success
 *     ERROR on failure
 */
int deqCommitPtr(int portNum, unsigned int addr)
{
    reginfo_t *regdb;  /* RedHawk register database */

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Incorrect port number\n");
        return ERROR;
    }

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Setting the commit pointer */
    addr = addr + 1; /* Incrementing the address by one */
    regSet(regdb, CfgDeqCPUCommitPointer, portNum, addr);

    /* Enabling the CPU Access and CPU commit ptr field */
    regSet(regdb, CfgDeqCPUAccess, portNum, 9);

    /* Disabling the CPU Access */
    regSet(regdb, CfgDeqCPUAccess, portNum, 0);

    return OK;
}

/******************************************************************
* rhAsicReadDeqMem - Read from a Dequeuer Memory Location
*
* This routine is used for reading a Dequeuer Memory location
*
* RETURNS:
*     OK : On Success
*     ERROR : On Failure
*/
int rhAsicReadDeqMem (
    int portNum,         /* Port Number */
    unsigned int addr,   /* Address */
    unsigned char *data  /* Data Value */
    )
{
    unsigned int tempData;
    reginfo_t *regdb;           /* RedHawk register database */
    unsigned int commPtr;

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Incorrect port number\n");
        return ERROR;
    }

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Enable the CPU Access bit */
    regSet(regdb, CfgDeqCPUAccess, portNum, 1);

    /* Read the commit pointer */
    regGet(regdb, StsDeqCommitPointer, portNum, &commPtr);

    /* Check for the addr validity as it can't be greater than the commit
       pointer. Write the CPU address to the register */
    if (addr < commPtr) {
        /* Write the CPU address and enable the CPU enable bit */
        regSet(regdb, CfgDeqCPUReadAddress, portNum, addr);
        regSet(regdb, CfgDeqCPUAccess, portNum, 5);

        /* Read the data from the respective registers */
        tempData = 0;
        if (regGet(regdb, StsDeqCPUReadData_0, portNum, &tempData) == OK) {
            data[0] = (tempData & 0xFF000000) >> 24;
            data[1] = (tempData & 0x00FF0000) >> 16;
            data[2] = (tempData & 0x0000FF00) >> 8;
            data[3] = tempData & 0xFF;
        } else {
            osPrintf("StsDeqCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsDeqCPUReadData_1, portNum, &tempData) == OK) {
            data[4] = (tempData & 0xFF000000) >> 24;
            data[5] = (tempData & 0x00FF0000) >> 16;
            data[6] = (tempData & 0x0000FF00) >> 8;
            data[7] = tempData & 0xFF;
        } else {
            osPrintf("StsDeqCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsDeqCPUReadData_2, portNum, &tempData) == OK) {
            data[8]  = (tempData & 0xFF000000) >> 24;
            data[9]  = (tempData & 0x00FF0000) >> 16;
            data[10] = (tempData & 0x0000FF00) >> 8;
            data[11] = tempData & 0xFF;
        } else {
            osPrintf("StsDeqCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsDeqCPUReadData_3, portNum, &tempData) == OK) {
            data[12] = (tempData & 0xFF000000) >> 24;
            data[13] = (tempData & 0x00FF0000) >> 16;
            data[14] = (tempData & 0x0000FF00) >> 8;
            data[15] = tempData & 0xFF;
        } else {
            osPrintf("StsDeqCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsDeqCPUReadData_4, portNum, &tempData) == OK) {
            data[16] = (tempData & 0xFF000000) >> 24;
            data[17] = (tempData & 0x00FF0000) >> 16;
            data[18] = (tempData & 0x0000FF00) >> 8;
            data[19] = tempData & 0xFF;
        } else {
            osPrintf("StsDeqCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsDeqCPUReadData_5, portNum, &tempData) == OK) {
            data[20] = (tempData & 0xFF000000) >> 24;
            data[21] = (tempData & 0x00FF0000) >> 16;
            data[22] = (tempData & 0x0000FF00) >> 8;
            data[23] = tempData & 0xFF;
        } else {
            osPrintf("StsDeqCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsDeqCPUReadData_6, portNum, &tempData) == OK) {
            data[24] = (tempData & 0xFF000000) >> 24;
            data[25] = (tempData & 0x00FF0000) >> 16;
            data[26] = (tempData & 0x0000FF00) >> 8;
            data[27] = tempData & 0xFF;
        } else {
            osPrintf("StsDeqCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsDeqCPUReadData_7, portNum, &tempData) == OK) {
            data[28] = (tempData & 0xFF000000) >> 24;
            data[29] = (tempData & 0x00FF0000) >> 16;
            data[30] = (tempData & 0x0000FF00) >> 8;
            data[31] = tempData & 0xFF;
        } else {
            osPrintf("StsDeqCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsDeqCPUReadData_8, portNum, &tempData) == OK) {
            data[32] = (tempData & 0x0000FF00) >> 8;
            data[33] = tempData & 0x07; /* Only 11 bits are valid in the last word */
        } else {
            osPrintf("StsDeqCPUReadData error\n");
            return ERROR;
        }
    } else {
        osPrintf("ERROR : Address %d is not less than Commit Pointer %d\n", addr, commPtr);
        return ERROR;
    }

    /* Disble the CPU Access bit and the read bit */
    regSet(regdb, CfgDeqCPUAccess, portNum, 0);

    return OK;
}

/******************************************************************
* rhAsicWriteDrpCtrlMem - Write to Drop Control Memory Location
*
* This routine is used for writing to a Drop Control Memory location
*
* RETURNS:
*     OK : On Success
*     ERROR : On Failure
*/
int rhAsicWriteDrpCtrlMem (
    int portNum,         /* Port Number */
    unsigned int addr,   /* Address */
    unsigned char *data  /* Data Value */
    )
{
    unsigned int tempData;
    reginfo_t *regdb;           /* RedHawk register database */

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Drop Control Mem Write : Incorrect port number\n");
        return ERROR;
    }

    /* Enabling the CPUAccess bit in the register */
    regSet(regdb, CfgMiscCPUAccess, portNum, 1);

    /* Writing data to the respective registers */
    tempData = 0 | (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];
    regSet(regdb, CfgMiscCPUWriteData_0, portNum, tempData);

    tempData = 0 | (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];
    regSet(regdb, CfgMiscCPUWriteData_1, portNum, tempData);

    tempData = 0 | (data[8] << 8) | data[9];
    regSet(regdb, CfgMiscCPUWriteData_2, portNum, tempData);

    /* Writing the address to the respective register */
    regSet(regdb, CfgMiscCPUWriteAddress, portNum, addr);

    /* Enabling the Write bit in the CPU Access register */
    regSet(regdb, CfgMiscCPUAccess, portNum, 3);

    return OK;
}

/*
 * Routine sets the Commit pointer in the Drop Control memory
 * Parameters :
 *     Port Number - Specifies for which port number the action has to be taken
 *     Address - Specifies the address to which the commit pointer to be set
 *
 * Returns :
 *     OK on success
 *     ERROR on failure
 */
int drpCtrlCommitPtr(int portNum, unsigned int addr)
{
    reginfo_t *regdb;           /* RedHawk register database */

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Setting the commit pointer */
    addr = addr + 1; /* Incrementing the address by one */
    regSet(regdb, CfgMiscCPUCommitPointer, portNum, addr);

    /* Enabling the CPU Access and CPU commit ptr field */
    regSet(regdb, CfgMiscCPUAccess, portNum, 9);

    /* Disabling the CPU Access */
    regSet(regdb, CfgMiscCPUAccess, portNum, 0);

    return OK;
}

/******************************************************************
* rhAsicReadDrpCtrlMem - Read from a Drop Controller Memory Location
*
* This routine is used for reading a Drop Controller Memory location
*
* RETURNS:
*     OK : On Success
*     ERROR : On Failure
*/
int rhAsicReadDrpCtrlMem (
    int portNum,         /* Port Number */
    unsigned int addr,   /* Address */
    unsigned char *data  /* Data Value */
    )
{
    unsigned int tempData;
    reginfo_t *regdb;           /* RedHawk register database */
    unsigned int commPtr;

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Enable the CPU Access bit */
    regSet(regdb, CfgMiscCPUAccess, portNum, 1);

    /* Read the commit pointer */
    regGet(regdb, StsMiscCommitPointer, portNum, &commPtr);

    /* Check for the addr validity as it can't be greater than the commit
       pointer. Write the CPU address to the register */
    if (addr < commPtr) {
        /* Write the CPU address and enable the CPU enable bit */
        regSet(regdb, CfgMiscCPUReadAddress, portNum, addr);
        regSet(regdb, CfgMiscCPUAccess, portNum, 5);

        /* Read the data from the respective registers */
        tempData = 0;
        if (regGet(regdb, StsMiscCPUReadData_0, portNum, &tempData) == OK) {
            data[0] = (tempData & 0xFF000000) >> 24;
            data[1] = (tempData & 0x00FF0000) >> 16;
            data[2] = (tempData & 0x0000FF00) >> 8;
            data[3] = tempData & 0xFF;
        } else {
            osPrintf("StsMiscCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsMiscCPUReadData_1, portNum, &tempData) == OK) {
            data[4] = (tempData & 0xFF000000) >> 24;
            data[5] = (tempData & 0x00FF0000) >> 16;
            data[6] = (tempData & 0x0000FF00) >> 8;
            data[7] = tempData & 0xFF;
        } else {
            osPrintf("StsMiscCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsMiscCPUReadData_2, portNum, &tempData) == OK) {
            data[8]  = (tempData & 0x0000FF00) >> 8;
            data[9] = tempData & 0x0F;
        } else {
            osPrintf("StsMiscCPUReadData error\n");
            return ERROR;
        }
    } else {
        osPrintf("ERROR : Address %d is not less than Commit Pointer %d\n", addr, commPtr);
        return ERROR;
    }

    /* Disble the CPU Access bit and the read bit */
    regSet(regdb, CfgMiscCPUAccess, portNum, 0);

    return OK;
}

/******************************************************************
* rhAsicWriteTxSpiMem - Write to Transmit SPI Memory Location
*
* This routine is used for writing to a Transmit SPI Memory location
*
* RETURNS:
*     OK : On Success
*     ERROR : On Failure
*/
int rhAsicWriteTxSpiMem (
    int portNum,         /* Port Number */
    unsigned int addr,   /* Address */
    unsigned char *data  /* Data Value */
    )
{
    unsigned int tempData;
    reginfo_t *regdb;           /* RedHawk register database */

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Incorrect Buffer Number\n");
        return ERROR;
    }

    /* Check for the buffer number */
    if (portNum == 0) {

        /* Enabling the CPUAccess bit in the register */
        regSet(regdb, CfgMiscCPUAccess0, 0, 1);

        /* Writing data to the respective registers */
        tempData = 0 | (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];
        regSet(regdb, CfgMiscCPUWriteData0, 0, tempData);

        tempData = 0 | (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];
        regSet(regdb, CfgMiscCPUWriteData0, 1, tempData);

        tempData = 0 | (data[8] << 24) | (data[9] << 16) | (data[10] << 8) | data[11];
        regSet(regdb, CfgMiscCPUWriteData0, 2, tempData);

        tempData = 0 | (data[12] << 24) | (data[13] << 16) | (data[14] << 8) | data[15];
        regSet(regdb, CfgMiscCPUWriteData0, 3, tempData);

        tempData = 0 | (data[16] << 24) | (data[17] << 16) | (data[18] << 8) | data[19];
        regSet(regdb, CfgMiscCPUWriteData0, 4, tempData);

        tempData = 0 | (data[20] << 24) | (data[21] << 16) | (data[22] << 8) | data[23];
        regSet(regdb, CfgMiscCPUWriteData0, 5, tempData);

        tempData = 0 | (data[24] << 24) | (data[25] << 16) | (data[26] << 8) | data[27];
        regSet(regdb, CfgMiscCPUWriteData0, 6, tempData);

        tempData = 0 | (data[28] << 24) | (data[29] << 16) | (data[30] << 8) | data[31];
        regSet(regdb, CfgMiscCPUWriteData0, 7, tempData);

        tempData = 0 | (data[32]<<24) | (data[33] << 16) | (data[34] << 8) | data[35];
        regSet(regdb, CfgMiscCPUWriteData0, 8, tempData);

        /* Writing the address to the respective register */
        regSet(regdb, CfgMiscCPUWriteAddress0, 0, addr);

        /* Enabling the Write bit in the CPU Access register */
        regSet(regdb, CfgMiscCPUAccess0, 0, 3);
    } else {

        /* Enabling the CPUAccess bit in the register */
        regSet(regdb, CfgMiscCPUAccess1, 0, 1);

        /* Writing data to the respective registers */
        tempData = 0 | (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];
        regSet(regdb, CfgMiscCPUWriteData1, 0, tempData);

        tempData = 0 | (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];
        regSet(regdb, CfgMiscCPUWriteData1, 1, tempData);

        tempData = 0 | (data[8] << 24) | (data[9] << 16) | (data[10] << 8) | data[11];
        regSet(regdb, CfgMiscCPUWriteData1, 2, tempData);

        tempData = 0 | (data[12] << 24) | (data[13] << 16) | (data[14] << 8) | data[15];
        regSet(regdb, CfgMiscCPUWriteData1, 3, tempData);

        tempData = 0 | (data[16] << 24) | (data[17] << 16) | (data[18] << 8) | data[19];
        regSet(regdb, CfgMiscCPUWriteData1, 4, tempData);

        tempData = 0 | (data[20] << 24) | (data[21] << 16) | (data[22] << 8) | data[23];
        regSet(regdb, CfgMiscCPUWriteData1, 5, tempData);

        tempData = 0 | (data[24] << 24) | (data[25] << 16) | (data[26] << 8) | data[27];
        regSet(regdb, CfgMiscCPUWriteData1, 6, tempData);

        tempData = 0 | (data[28] << 24) | (data[29] << 16) | (data[30] << 8) | data[31];
        regSet(regdb, CfgMiscCPUWriteData1, 7, tempData);

        tempData = 0 | (data[32]<<24) | (data[33] << 16) | (data[34] << 8) | data[35];
        regSet(regdb, CfgMiscCPUWriteData1, 8, tempData);

        /* Writing the address to the respective register */
        regSet(regdb, CfgMiscCPUWriteAddress1, 0, addr);

        /* Enabling the Write bit in the CPU Access register */
        regSet(regdb, CfgMiscCPUAccess1, 0, 3);
    }

    return OK;
}

/*
 * Routine sets the Commit pointer in the Tx SPI memory
 * Parameters :
 *     Port Number - Specifies for which port number the action has to be taken
 *     Address - Specifies the address to which the commit pointer to be set
 *
 * Returns :
 *     OK on success
 *     ERROR on failure
 */
int txSpiCommitPtr(int bufNum, unsigned int addr)
{
    reginfo_t *regdb;           /* RedHawk register database */

    /* Validating the port number received */
    if (bufNum < 0 || bufNum > 1) {
        osPrintf("Incorrect port number\n");
        return ERROR;
    }

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Setting the commit pointer */
    addr = addr + 1; /* Incrementing the address by one */

    /* Check for the buffer number */
    if (bufNum == 0) {

        regSet(regdb, CfgMiscCPUCommitPointer0, 0, addr);

        /* Enabling the CPU Access and CPU commit ptr field */
        regSet(regdb, CfgMiscCPUAccess0, 0, 9);

        /* Disabling the CPU Access */
        regSet(regdb, CfgMiscCPUAccess0, 0, 0);
    } else {

        regSet(regdb, CfgMiscCPUCommitPointer1, 0, addr);

        /* Enabling the CPU Access and CPU commit ptr field */
        regSet(regdb, CfgMiscCPUAccess1, 0, 9);

        /* Disabling the CPU Access */
        regSet(regdb, CfgMiscCPUAccess1, 0, 0);
    }

    return OK;
}

/******************************************************************
* rhAsicReadTxSpiMem - Read from a Transmit SPI Memory Location
*
* This routine is used for reading a Transmit SPI Memory location
*
* RETURNS:
*     OK : On Success
*     ERROR : On Failure
*/
int rhAsicReadTxSpiMem (
    int portNum,         /* Port Number */
    unsigned int addr,   /* Address */
    unsigned char *data  /* Data Value */
    )
{
    unsigned int tempData;
    reginfo_t *regdb;           /* RedHawk register database */
    unsigned int commPtr;

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Incorrect port number\n");
        return ERROR;
    }

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Check for the buffer number */
    if (portNum == 0) {

        /* Enable the CPU Access bit */
        regSet(regdb, CfgMiscCPUAccess0, 0, 1);

        /* Read the commit pointer */
        regGet(regdb, StsMiscCommitPointer0, 0, &commPtr);

        /* Check for the addr validity as it can't be greater than the commit
           pointer. Write the CPU address to the register */
        if (addr < commPtr) {
            /* Write the CPU address and enable the CPU enable bit */
            regSet(regdb, CfgMiscCPUReadAddress0, 0, addr);
            regSet(regdb, CfgMiscCPUAccess0, 0, 5);

            /* Read the data from the respective registers */
            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData0, 0, &tempData) == OK) {
                data[0] = (tempData & 0xFF000000) >> 24;
                data[1] = (tempData & 0x00FF0000) >> 16;
                data[2] = (tempData & 0x0000FF00) >> 8;
                data[3] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData0, 1, &tempData) == OK) {
                data[4] = (tempData & 0xFF000000) >> 24;
                data[5] = (tempData & 0x00FF0000) >> 16;
                data[6] = (tempData & 0x0000FF00) >> 8;
                data[7] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData0, 2, &tempData) == OK) {
                data[8]  = (tempData & 0xFF000000) >> 24;
                data[9]  = (tempData & 0x00FF0000) >> 16;
                data[10] = (tempData & 0x0000FF00) >> 8;
                data[11] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData0, 3, &tempData) == OK) {
                data[12] = (tempData & 0xFF000000) >> 24;
                data[13] = (tempData & 0x00FF0000) >> 16;
                data[14] = (tempData & 0x0000FF00) >> 8;
                data[15] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData0, 4, &tempData) == OK) {
                data[16] = (tempData & 0xFF000000) >> 24;
                data[17] = (tempData & 0x00FF0000) >> 16;
                data[18] = (tempData & 0x0000FF00) >> 8;
                data[19] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData0, 5, &tempData) == OK) {
                data[20] = (tempData & 0xFF000000) >> 24;
                data[21] = (tempData & 0x00FF0000) >> 16;
                data[22] = (tempData & 0x0000FF00) >> 8;
                data[23] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData0, 6, &tempData) == OK) {
                data[24] = (tempData & 0xFF000000) >> 24;
                data[25] = (tempData & 0x00FF0000) >> 16;
                data[26] = (tempData & 0x0000FF00) >> 8;
                data[27] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData0, 7, &tempData) == OK) {
                data[28] = (tempData & 0xFF000000) >> 24;
                data[29] = (tempData & 0x00FF0000) >> 16;
                data[30] = (tempData & 0x0000FF00) >> 8;
                data[31] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData0, 8, &tempData) == OK) {
                data[32] = (tempData & 0xFF000000) >> 24;
                data[33] = (tempData & 0x00FF0000) >> 16;
                data[34] = (tempData & 0x0000FF00) >> 8;
                data[35] = tempData & 0xFF; /* Only 11 bits are valid in the last byte */
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }
        } else {
            osPrintf("ERROR : Address %d is not less than Commit Pointer %d\n", addr, commPtr);
            return ERROR;
        }

        /* Disble the CPU Access bit and the read bit */
        regSet(regdb, CfgMiscCPUAccess0, 0, 0);
    } else {
        /* For Buffer Number 1 */
        /* Enable the CPU Access bit */
        regSet(regdb, CfgMiscCPUAccess1, 0, 1);

        /* Read the commit pointer */
        regGet(regdb, StsMiscCommitPointer1, 0, &commPtr);

        /* Check for the addr validity as it can't be greater than the commit
           pointer. Write the CPU address to the register */
        if (addr < commPtr) {
            /* Write the CPU address and enable the CPU enable bit */
            regSet(regdb, CfgMiscCPUReadAddress1, 0, addr);
            regSet(regdb, CfgMiscCPUAccess1, 0, 5);

            /* Read the data from the respective registers */
            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData1, 0, &tempData) == OK) {
                data[0] = (tempData & 0xFF000000) >> 24;
                data[1] = (tempData & 0x00FF0000) >> 16;
                data[2] = (tempData & 0x0000FF00) >> 8;
                data[3] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData1, 1, &tempData) == OK) {
                data[4] = (tempData & 0xFF000000) >> 24;
                data[5] = (tempData & 0x00FF0000) >> 16;
                data[6] = (tempData & 0x0000FF00) >> 8;
                data[7] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData1, 2, &tempData) == OK) {
                data[8]  = (tempData & 0xFF000000) >> 24;
                data[9]  = (tempData & 0x00FF0000) >> 16;
                data[10] = (tempData & 0x0000FF00) >> 8;
                data[11] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData1, 3, &tempData) == OK) {
                data[12] = (tempData & 0xFF000000) >> 24;
                data[13] = (tempData & 0x00FF0000) >> 16;
                data[14] = (tempData & 0x0000FF00) >> 8;
                data[15] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData1, 4, &tempData) == OK) {
                data[16] = (tempData & 0xFF000000) >> 24;
                data[17] = (tempData & 0x00FF0000) >> 16;
                data[18] = (tempData & 0x0000FF00) >> 8;
                data[19] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData1, 5, &tempData) == OK) {
                data[20] = (tempData & 0xFF000000) >> 24;
                data[21] = (tempData & 0x00FF0000) >> 16;
                data[22] = (tempData & 0x0000FF00) >> 8;
                data[23] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData1, 6, &tempData) == OK) {
                data[24] = (tempData & 0xFF000000) >> 24;
                data[25] = (tempData & 0x00FF0000) >> 16;
                data[26] = (tempData & 0x0000FF00) >> 8;
                data[27] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData1, 7, &tempData) == OK) {
                data[28] = (tempData & 0xFF000000) >> 24;
                data[29] = (tempData & 0x00FF0000) >> 16;
                data[30] = (tempData & 0x0000FF00) >> 8;
                data[31] = tempData & 0xFF;
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }

            tempData = 0;
            if (regGet(regdb, StsMiscCPUReadData1, 8, &tempData) == OK) {
                data[32] = (tempData & 0xFF000000) >> 24;
                data[33] = (tempData & 0x00FF0000) >> 16;
                data[34] = (tempData & 0x0000FF00) >> 8;
                data[35] = tempData & 0xFF; /* Only 11 bits are valid in the last byte */
            } else {
                osPrintf("StsMiscCPUReadData0 error\n");
                return ERROR;
            }
        } else {
            osPrintf("ERROR : Address %d is not less than Commit Pointer %d\n", addr, commPtr);
            return ERROR;
        }

        /* Disble the CPU Access bit and the read bit */
        regSet(regdb, CfgMiscCPUAccess1, 0, 0);
    }

    return OK;
}

/******************************************************************
* rhAsicWriteTxMem - Write to Transmit Memory Location
*
* This routine is used for writing to a Transmit Memory location
*
* RETURNS:
*     OK : On Success
*     ERROR : On Failure
*/
int rhAsicWriteTxMem (
    int portNum,         /* Port Number */
    unsigned int addr,   /* Address */
    unsigned char *data  /* Data Value */
    )
{
    unsigned int tempData;
    reginfo_t *regdb;           /* RedHawk register database */

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Incorrect port number\n");
        return ERROR;
    }

    /* Enabling the CPUAccess bit in the register */
    regSet(regdb, CfgTxMemMgrCPUAccess, portNum, 1);

    /* Writing data to the respective registers */
    tempData = 0 | (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];
    regSet(regdb, CfgTxMemMgrCPUWriteData_0, portNum, tempData);

    tempData = 0 | (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];
    regSet(regdb, CfgTxMemMgrCPUWriteData_1, portNum, tempData);

    tempData = 0 | (data[8] << 24) | (data[9] << 16) | (data[10] << 8) | data[11];
    regSet(regdb, CfgTxMemMgrCPUWriteData_2, portNum, tempData);

    tempData = 0 | (data[12] << 24) | (data[13] << 16) | (data[14] << 8) | data[15];
    regSet(regdb, CfgTxMemMgrCPUWriteData_3, portNum, tempData);

    tempData = 0 | data[16];
    regSet(regdb, CfgTxMemMgrCPUWriteData_4, portNum, tempData);

    /* Writing the address to the respective register */
    regSet(regdb, CfgDeqCPUWriteAddress, portNum, addr);

    /* Enabling the Write bit in the CPU Access register */
    regSet(regdb, CfgTxMemMgrCPUAccess, portNum, 3);

    return OK;
}

/*
 * Routine sets the Commit pointer in the Tx memory
 * Parameters :
 *     Port Number - Specifies for which port number the action has to be taken
 *     Address - Specifies the address to which the commit pointer to be set
 *
 * Returns :
 *     OK on success
 *     ERROR on failure
 */
int txMemCommitPtr(int portNum, unsigned int addr)
{
    reginfo_t *regdb;           /* RedHawk register database */

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Incorrect port number\n");
        return ERROR;
    }

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Setting the commit pointer */
    addr = addr + 1; /* Incrementing the address by one */
    regSet(regdb, CfgTxMemMgrCPUCommitPointer, portNum, addr);

    /* Enabling the CPU Access and CPU commit ptr field */
    regSet(regdb, CfgTxMemMgrCPUAccess, portNum, 9);

    /* Disabling the CPU Access */
    regSet(regdb, CfgTxMemMgrCPUAccess, portNum, 0);

    return OK;
}

/******************************************************************
* rhAsicReadTxMem - Read from a Transmit Memory Location
*
* This routine is used for reading a Transmit Memory location
*
* RETURNS:
*     OK : On Success
*     ERROR : On Failure
*/
int rhAsicReadTxMem (
    int portNum,         /* Port Number */
    unsigned int addr,   /* Address */
    unsigned char *data  /* Data Value */
    )
{
    unsigned int tempData;
    reginfo_t *regdb;           /* RedHawk register database */
    unsigned int commPtr;

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Incorrect port number\n");
        return ERROR;
    }

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Enable the CPU Access bit */
    regSet(regdb, CfgTxMemMgrCPUAccess, portNum, 1);

    /* Read the commit pointer */
    regGet(regdb, StsTxMemMgrCommitPointer, portNum, &commPtr);

    /* Check for the addr validity as it can't be greater than the commit
       pointer. Write the CPU address to the register */
    if (addr < commPtr) {
        /* Write the CPU address and enable the CPU enable bit */
        regSet(regdb, CfgTxMemMgrCPUReadAddress, portNum, addr);
        regSet(regdb, CfgTxMemMgrCPUAccess, portNum, 5);

        /* Read the data from the respective registers */
        tempData = 0;
        if (regGet(regdb, StsTxMemMgrCPUReadData_0, portNum, &tempData) == OK) {
            data[0] = (tempData & 0xFF000000) >> 24;
            data[1] = (tempData & 0x00FF0000) >> 16;
            data[2] = (tempData & 0x0000FF00) >> 8;
            data[3] = tempData & 0xFF;
        } else {
            osPrintf("StsTxMemMgrCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsTxMemMgrCPUReadData_1, portNum, &tempData) == OK) {
            data[4] = (tempData & 0xFF000000) >> 24;
            data[5] = (tempData & 0x00FF0000) >> 16;
            data[6] = (tempData & 0x0000FF00) >> 8;
            data[7] = tempData & 0xFF;
        } else {
            osPrintf("StsTxMemMgrCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsTxMemMgrCPUReadData_2, portNum, &tempData) == OK) {
            data[8]  = (tempData & 0xFF000000) >> 24;
            data[9]  = (tempData & 0x00FF0000) >> 16;
            data[10] = (tempData & 0x0000FF00) >> 8;
            data[11] = tempData & 0xFF;
        } else {
            osPrintf("StsTxMemMgrCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsTxMemMgrCPUReadData_3, portNum, &tempData) == OK) {
            data[12] = (tempData & 0xFF000000) >> 24;
            data[13] = (tempData & 0x00FF0000) >> 16;
            data[14] = (tempData & 0x0000FF00) >> 8;
            data[15] = tempData & 0xFF;
        } else {
            osPrintf("StsTxMemMgrCPUReadData error\n");
            return ERROR;
        }

        tempData = 0;
        if (regGet(regdb, StsTxMemMgrCPUReadData_4, portNum, &tempData) == OK) {
            data[16] = tempData && 0xFF;
        } else {
            osPrintf("StsTxMemMgrCPUReadData error\n");
            return ERROR;
        }
    } else {
        osPrintf("ERROR : Address %d is not less than Commit Pointer %d\n", addr, commPtr);
        return ERROR;
    }

    /* Disble the CPU Access bit and the read bit */
    regSet(regdb, CfgTxMemMgrCPUAccess, portNum, 0);

    return OK;
}

/******************************************************************
* rhAsicWriteExtMem - Write to FCRAM Memory Location
*
* This routine is used for writing to a FCRAM Memory location
*
* RETURNS:
*     OK : On Success
*     ERROR : On Failure
*/
int rhAsicWriteExtMem (
    int portNum,         /* Port Number */
    int bank,            /* FCRAM bank */
    unsigned int addr,   /* Address */
    unsigned char *data  /* Data Value */
    )
{
    unsigned int tempData;
    reginfo_t *regdb;           /* RedHawk register database */
    unsigned int regVal;

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Incorrect port number\n");
        return ERROR;
    }

    /* Clear the interrupts */
    regGet(regdb, StsMemAccessInterrupt, portNum, &regVal);

    /* Unmask the interrupts */
    regSet(regdb, StsMemAccessInterruptMask, portNum, 0);

    /* Write the data to the Cfg registers */
    tempData = 0 | (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];
    regSet(regdb, CfgExtMemData_0, portNum, tempData);

    tempData = 0 | (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];
    regSet(regdb, CfgExtMemData_1, portNum, tempData);

    tempData = 0 | (data[8] << 24) | (data[9] << 16) | (data[10] << 8) | data[11];
    regSet(regdb, CfgExtMemData_2, portNum, tempData);

    tempData = 0 | (data[12] << 24) | (data[13] << 16) | (data[14] << 8) | data[15];
    regSet(regdb, CfgExtMemData_3, portNum, tempData);

    tempData = 0 | (data[16] << 24) | (data[17] << 16) | (data[18] << 8) | data[19];
    regSet(regdb, CfgExtMemData_4, portNum, tempData);

    tempData = 0 | (data[20] << 24) | (data[21] << 16) | (data[22] << 8) | data[23];
    regSet(regdb, CfgExtMemData_5, portNum, tempData);

    tempData = 0 | (data[24] << 24) | (data[25] << 16) | (data[26] << 8) | data[27];
    regSet(regdb, CfgExtMemData_6, portNum, tempData);

    tempData = 0 | (data[28] << 24) | (data[29] << 16) | (data[30] << 8) | data[31];
    regSet(regdb, CfgExtMemData_7, portNum, tempData);

    /* Set the address to which the data has to be written */
    /* First generate the command */
    tempData = 0 | (addr << 3) | (bank << 1);

    /* Write to the command register */
    regSet(regdb, CfgMemAccessCommand, portNum, tempData);

    /* Wait for the register */
    tempData = 0;
    while (tempData == 0) {
        regGet(regdb, StsMemAccessInterrupt, portNum, &tempData);
    }

    return OK;
}

/******************************************************************
* rhAsicReadExtMem - Read from a FCRAM Memory Location
*
* This routine is used for reading a FCRAM Memory location
*
* RETURNS:
*     OK : On Success
*     ERROR : On Failure
*/
int rhAsicReadExtMem (
    int portNum,         /* Port Number */
    int bank,            /* FCRAM bank */
    unsigned int addr,   /* Address */
    unsigned char *data  /* Data Value */
    )
{
    unsigned int tempData;
    reginfo_t *regdb;           /* RedHawk register database */
    unsigned int regVal;

    /* Pointing to the RedHawk register database */
    regdb = redHawkRegs;

    /* Validating the port number received */
    if (portNum < 0 || portNum > 1) {
        osPrintf("Incorrect port number\n");
        return ERROR;
    }

    /* Clear the interrupts */
    regGet(regdb, StsMemAccessInterrupt, portNum, &regVal);

    /* Unmask the interrupts */
    regSet(regdb, StsMemAccessInterruptMask, portNum, 0);

    /* Form the read command */
    tempData = 0 | (bank << 1) | (addr << 3);
    tempData = tempData | 0x1; /* Enabling the read command */

    /* Write the command to the register */
    regSet(regdb, CfgMemAccessCommand, portNum, tempData);

    /* Wait for the interrupt */
    tempData = 0;
    while (tempData != 0x2) {
        regGet(regdb, StsMemAccessInterrupt, portNum, &tempData);
        tempData = tempData & 0x2;
    }

    /* Read the data */
    tempData = 0;
    if (regGet(regdb, StsExtMemData_0, portNum, &tempData) == OK) {
        data[0] = (tempData & 0xFF000000) >> 24;
        data[1] = (tempData & 0x00FF0000) >> 16;
        data[2] = (tempData & 0x0000FF00) >> 8;
        data[3] = tempData & 0xFF;
    } else {
        osPrintf("StsExtMemData_0 error\n");
        return ERROR;
    }

    tempData = 0;
    if (regGet(regdb, StsExtMemData_1, portNum, &tempData) == OK) {
        data[4] = (tempData & 0xFF000000) >> 24;
        data[5] = (tempData & 0x00FF0000) >> 16;
        data[6] = (tempData & 0x0000FF00) >> 8;
        data[7] = tempData & 0xFF;
    } else {
        osPrintf("StsExtMemData_1 error\n");
        return ERROR;
    }

    tempData = 0;
    if (regGet(regdb, StsExtMemData_2, portNum, &tempData) == OK) {
        data[8]  = (tempData & 0xFF000000) >> 24;
        data[9]  = (tempData & 0x00FF0000) >> 16;
        data[10] = (tempData & 0x0000FF00) >> 8;
        data[11] = tempData & 0xFF;
    } else {
        osPrintf("StsExtMemData_2 error\n");
        return ERROR;
    }

    tempData = 0;
    if (regGet(regdb, StsExtMemData_3, portNum, &tempData) == OK) {
        data[12] = (tempData & 0xFF000000) >> 24;
        data[13] = (tempData & 0x00FF0000) >> 16;
        data[14] = (tempData & 0x0000FF00) >> 8;
        data[15] = tempData & 0xFF;
    } else {
        osPrintf("StsExtMemData_3 error\n");
        return ERROR;
    }

    tempData = 0;
    if (regGet(regdb, StsExtMemData_4, portNum, &tempData) == OK) {
        data[16] = (tempData & 0xFF000000) >> 24;
        data[17] = (tempData & 0x00FF0000) >> 16;
        data[18] = (tempData & 0x0000FF00) >> 8;
        data[19] = tempData & 0xFF;
    } else {
        osPrintf("StsExtMemData_4 error\n");
        return ERROR;
    }

    tempData = 0;
    if (regGet(regdb, StsExtMemData_5, portNum, &tempData) == OK) {
        data[20] = (tempData & 0xFF000000) >> 24;
        data[21] = (tempData & 0x00FF0000) >> 16;
        data[22] = (tempData & 0x0000FF00) >> 8;
        data[23] = tempData & 0xFF;
    } else {
        osPrintf("StsExtMemData_5 error\n");
        return ERROR;
    }

    tempData = 0;
    if (regGet(regdb, StsExtMemData_6, portNum, &tempData) == OK) {
        data[24] = (tempData & 0xFF000000) >> 24;
        data[25] = (tempData & 0x00FF0000) >> 16;
        data[26] = (tempData & 0x0000FF00) >> 8;
        data[27] = tempData & 0xFF;
    } else {
        osPrintf("StsExtMemData_6 error\n");
        return ERROR;
    }

    tempData = 0;
    if (regGet(regdb, StsExtMemData_7, portNum, &tempData) == OK) {
        data[28] = (tempData & 0xFF000000) >> 24;
        data[29] = (tempData & 0x00FF0000) >> 16;
        data[30] = (tempData & 0x0000FF00) >> 8;
        data[31] = tempData & 0xFF;
    } else {
        osPrintf("StsExtMemData_7 error\n");
        return ERROR;
    }

    return OK;
}

/*
 * FreePage Table Initialization Routine
 * Called from the RedHawk Configuration routines
 */
void rh_init_freepage_table (void)
{
    unsigned int regVal;

    regSet(redHawkRegs, CfgFreePageTableInit, 0, 0x00000001);
    regSet(redHawkRegs, CfgFreePageTableInit, 1, 0x00000001);

    /* Check for the FreePageTableInit done interrupt for both the instances
     * */
    regVal = 0;
    while (regVal == 0) {
        regGet(redHawkRegs, StsFreePageTableInitDone, 0, &regVal);
    }

    regVal = 0;
    while (regVal == 0) {
        regGet(redHawkRegs, StsFreePageTableInitDone, 1, &regVal);
    }
}

/*
 * FC RAM Initialization routines
 * Inputs
 * ram_type - 1; X18_MEM
 * ram_type - 2; X36_MEM
 * ram_type - 3; X36_MEM_576
 * port_num - Port Number for which the configuration has to be made
 */
void comm_fcram_init(int port_num, int ram_type)
{

    /* Common Slave configurations */
    if (ram_type == 1) {
        if (port_num == 0)
            regSet(redHawkRegs, CfgRegCoMemoryMode__CfgMemModeP0, 0, 5);
        else
            regSet(redHawkRegs, CfgRegCoMemoryMode__CfgMemModeP1, 0, 5);
    }

    if (ram_type == 2) {
        if (port_num == 0)
            regSet(redHawkRegs, CfgRegCoMemoryMode__CfgMemModeP0, 0, 6);
        else
            regSet(redHawkRegs, CfgRegCoMemoryMode__CfgMemModeP1, 0, 6);
    }

    if (ram_type == 3) {
        if (port_num == 0)
            regSet(redHawkRegs, CfgRegCoMemoryMode__CfgMemModeP0, 0, 5);
        else
            regSet(redHawkRegs, CfgRegCoMemoryMode__CfgMemModeP1, 0, 5);
    }

    if (port_num == 0) {
        regSet( redHawkRegs, VarRegCoFunctionActivate1__VarRxFCRAMHmEnP0, 0, 1);
        regSet( redHawkRegs, CfgRegCoFCRAMIOConfig__FC0_PowerDownN, 0, 1);
    } else {
        regSet( redHawkRegs, VarRegCoFunctionActivate1__VarRxFCRAMHmEnP1, 0, 1);
        regSet( redHawkRegs, CfgRegCoFCRAMIOConfig__FC1_PowerDownN, 0, 1);
    }

    regSet(redHawkRegs, CfgInitEMSAddr, port_num, 0x45);
    regSet(redHawkRegs, CfgStartFreePoolPagePntr, port_num, 0x1fff);
    if (ram_type == 1 || ram_type == 3) {
        regSet(redHawkRegs, CfgPageFullPntr, port_num, 0x1ff);
    } else {
        regSet(redHawkRegs, CfgPageFullPntr, port_num, 0x0ff);
    }
}

void fcram_init(int port_num, int ram_type)
{
    unsigned int regVal;

    regSet(redHawkRegs, StsMemAccessInterrupt, port_num, 0);
    regSet(redHawkRegs, StsMemAccessInterruptMask, port_num, 3);
    regVal = 0;
    regGet(redHawkRegs, VarRegCoFunctionActivate0, 0, &regVal);
    if (port_num == 0)
        regVal = regVal | BIT_9;
    else
        regVal = regVal | BIT_22;
    regSet(redHawkRegs, VarRegCoFunctionActivate0, 0, regVal);

    regVal = 0;
    while (regVal != 0x4) {
        regGet(redHawkRegs, StsMemAccessInterrupt, port_num, &regVal);
        regVal = regVal & 0x4;
    }
    regSet(redHawkRegs, CfgBankTrc, port_num, 6);
}

/*
 * Programs the SPI Calendar Memory
 * Parameters :
 *      memType = 0; sets the Tx Primary SPI memory
 *      memType = 1; sets the Tx Secondary SPI memory
 *      memType = 2; sets the Rx Primary SPI memory
 *      memType = 3; sets the Rx Secondary SPI memory
 */
void rh_program_calendar_mem (int memType)
{
    unsigned int regVal, i;

    if (memType > 3) {
        printf("Invalid Memtype; Valid range is 0 - 3\n");
        return;
    }

    switch (memType) {
        case 0:
            for (i=0; i<128; i++) {
                regVal = 0;
                regSet(redHawkRegs, CfgMemTSpiCal, i, regVal);
            }
            break;
        case 1:
            for (i=0; i<128; i++) {
                regVal = i%2;
                regVal = !regVal;
                regSet(redHawkRegs, CfgMemTxSSpiCal, i, regVal);
            }
            break;
        case 2:
            for (i=0; i<128; i++) {
                regVal = 0;
                regSet(redHawkRegs, CfgMemRxpSpiCalPri, i, regVal);
            }
            break;
        case 3:
            for (i=0; i<128; i++) {
                regVal = i%2;
                regSet(redHawkRegs, CfgMemRxsSpiCalPri, i, regVal);
            }
            break;
        default:
            break;
    }
}

/*************************************************************************
 *
 * RedHawk ASIC Diagnostic Test Functions
 *
 *************************************************************************/

/*
 * common_defChk - Checks the COMMON Slave registers for the default values
 */
int common_defChk (void) {
    checkDefVal(CfgRegCoRedHawkID, 0x00000000);
    checkDefVal(VarRegCoGlobalSoftReset, 0x00000000);
    checkDefVal(VarRegCoFunctionActivate0, 0x00000000);
    checkDefVal(VarRegCoFunctionActivate1, 0x00000000);
    checkDefVal(CfgRegCoCPUMode, 0x00000000);
    checkDefVal(CfgRegCoClockDiv0, 0x1f1f0101);
    checkDefVal(CfgRegCoClockDiv1, 0x00063232);
    checkDefVal(CfgRegCoLoopbackMode, 0x00000000);
    checkDefVal(CfgRegCoMemoryMode, 0x00000000);
    checkDefVal(CfgRegCoSystemInterfaceMode, 0x00000005);
    checkDefVal(CfgRegCoLineInterfaceMode, 0x00000005);
    checkDefVal(CfgRegCoOversubscriptionMode, 0x00000001);
    checkDefVal(CfgRegCoCascadeHarrierMode, 0x00000000);
    checkDefVal(CfgRegCoAPSMode, 0x00000000);
    checkDefVal(CfgRegCoCutThruMode, 0x00000000);
    checkDefVal(CfgRegCoMDIOMode, 0x00000300);
    checkDefVal(CfgRegCoMDIOSlaveSetup, 0x00000000);
    checkDefVal(CfgRegCoDiagSel, 0x00000000);
    checkDefVal(CfgRegCoDiagExtBitSel, 0x00000000);
    checkDefVal(CfgRegCoClkSelect, 0x0000000c);
    checkDefVal(CfgRegCoClkPowerDown, 0x00000000);
    checkDefVal(CfgRegCoSpiSetup, 0x00300550);
    checkDefVal(CfgRegCoRxpSpiHMPLLReg, 0x0006ca54);
    checkDefVal(CfgRegCoRxsSpiHMPLLReg, 0x0006ca54);
    checkDefVal(CfgRegCoTxPSpiHMPLLReg, 0x0013a3ac);
    checkDefVal(CfgRegCoTxSSpiHMPLLReg, 0x0013a3ac);
    checkDefVal(CfgRegCoXFISetup, 0x00000000);
    checkDefVal(CfgRegCoXAUISetup0, 0x01420500);
    checkDefVal(CfgRegCoXAUISetup1, 0x0f000f00);
    checkDefVal(CfgRegCoXAUISetup2, 0x00033009);
    checkDefVal(CfgRegCoLSIPortSelect, 0x00000000);
    checkDefVal(CfgRegCoXAUIIOConfig, 0x00007070);
    checkDefVal(CfgRegCoXFIIOConfig, 0x000001c0);
    checkDefVal(CfgRegCoFCPLLConfig, 0x00000039);
    checkDefVal(CfgRegCoFCRAMIOConfig, 0x38007000);
    checkDefVal(CfgRegCoFCRAMHardMacroConfig, 0x00000000);
    checkDefVal(CfgRegCoSPIIOConfig, 0x00000000);
    checkDefVal(CfgRegCo2wiremasterSetup, 0x00002850);
    checkDefVal(CfgRegCoMisc, 0x00000000);
    return OK;
}

/*
 * dequeuer_defChk - Checks the Dequeuer Slave registers for the default values
 */
int dequeuer_defChk (void) {
    checkDefVal(CfgDeqMdrrCreditQ0, 0x0000000a);
    checkDefVal(CfgDeqMdrrCreditQ1, 0x0000000a);
    checkDefVal(CfgDeqMdrrCreditQ2, 0x0000000a);
    checkDefVal(CfgDeqMdrrCreditQ3, 0x0000000a);
    checkDefVal(CfgDeqMdrrCreditQ4, 0x0000000a);
    checkDefVal(CfgDeqMdrrCreditQ5, 0x0000000a);
    checkDefVal(CfgDeqMdrrCreditQ6, 0x0000000a);
    checkDefVal(CfgDeqMdrrCreditQ7, 0x0000000a);
    checkDefVal(CfgDeqMdrrStrictPriorityMode, 0x00000000);
    checkDefVal(CfgDeqFullPacketMode, 0x00000001);
    checkDefVal(CfgDeqReadOnThreshold, 0x00000002);
    checkDefVal(CfgDeqReadOffThreshold, 0x00000000);
    checkDefVal(CfgDeqReadTimerValue, 0x00000064);
    checkDefVal(CfgDeqDisableRead, 0x00000000);
    checkDefVal(CfgDeqDisableDrop, 0x00000001);
    checkDefVal(CfgDeqTailDropEn, 0x00000000);
    checkDefVal(CfgDeqDisableEccCheck, 0x00000000);
    checkDefVal(CfgDeqLoopbackMode, 0x00000000);
    checkDefVal(CfgDeqLoopbackVlan0, 0x00000000);
    checkDefVal(CfgDeqLoopbackVlan1, 0x00000000);
    checkDefVal(CfgDeqLoopbackVlan2, 0x00000000);
    checkDefVal(CfgDeqLoopbackVlan3, 0x00000000);
    checkDefVal(CfgDeqLpbkEgressHeader0, 0x80000000);
    checkDefVal(CfgDeqLpbkEgressHeader1, 0x00000000);
    checkDefVal(CfgDeqTimeStampControl, 0x00000004);
    checkDefVal(CfgDeqExcessLatencyControl0, 0x00000000);
    checkDefVal(CfgDeqExcessLatencyControl1, 0x00000000);
    checkDefVal(CfgDeqHeaderStripControl, 0x00000000);
    checkDefVal(CfgDeqIngressHeaderBigEndian, 0x00000001);
    checkDefVal(CfgDeqEOPAbortEn, 0x00000001);
    checkDefVal(CfgDeqCPUAccess, 0x00000000);
    checkDefVal(CfgDeqCPUWriteAddress, 0x00000000);
    checkDefVal(CfgDeqCPUReadAddress, 0x00000000);
    checkDefVal(CfgDeqCPUCommitPointer, 0x00000000);
    checkDefVal(CfgDeqCPUWriteData_0, 0x00000000);
    checkDefVal(CfgDeqCPUWriteData_1, 0x00000000);
    checkDefVal(CfgDeqCPUWriteData_2, 0x00000000);
    checkDefVal(CfgDeqCPUWriteData_3, 0x00000000);
    checkDefVal(CfgDeqCPUWriteData_4, 0x00000000);
    checkDefVal(CfgDeqCPUWriteData_5, 0x00000000);
    checkDefVal(CfgDeqCPUWriteData_6, 0x00000000);
    checkDefVal(CfgDeqCPUWriteData_7, 0x00000000);
    checkDefVal(CfgDeqCPUWriteData_8, 0x00000000);
    checkDefVal(CfgDeqMTUFullnessThreshold, 0x000001c2);
    checkDefVal(CfgDeqOutputToNpuIsPSD, 0x00000000);
    checkDefVal(CfgDeqPauseFrameOnThreshold, 0x000001bd);
    checkDefVal(CfgDeqPauseFrameOffThreshold, 0x000001b8);
    return OK;
}

/*
 * dualmemctl_defChk - Checks the Dual Memory Controller Slave registers for the default values
 */
int dualmemctl_defChk (void) {
    checkDefVal(CfgInitFCRAM, 0xc8659154);
    checkDefVal(CfgInitEMSAddr, 0x00000040);
    checkDefVal(CfgInitMRSAddr, 0x00000042);
    checkDefVal(CfgBankTrc, 0x00000005);
    checkDefVal(CfgRefreshDiv, 0x0000000f);
    checkDefVal(CfgMemAccessCommand, 0x00000000);
    checkDefVal(CfgExtMemData_0, 0x00000000);
    checkDefVal(CfgExtMemData_1, 0x00000000);
    checkDefVal(CfgExtMemData_2, 0x00000000);
    checkDefVal(CfgExtMemData_3, 0x00000000);
    checkDefVal(CfgExtMemData_4, 0x00000000);
    checkDefVal(CfgExtMemData_5, 0x00000000);
    checkDefVal(CfgExtMemData_6, 0x00000000);
    checkDefVal(CfgExtMemData_7, 0x00000000);
    return OK;
}

/*
 * enqueuer_defChk - Checks the Enqueuer Slave registers for the default values
 */
int enqueuer_defChk (void) {
    checkDefVal(CfgBurstSize, 0x0000000f);
    checkDefVal(CfgIntMemAccessCommand, 0x00000000);
    checkDefVal(CfgIntMemData_0, 0x00000000);
    checkDefVal(CfgIntMemData_1, 0x00000000);
    checkDefVal(CfgIntMemData_2, 0x00000000);
    checkDefVal(CfgIntMemData_3, 0x00000000);
    checkDefVal(CfgIntMemData_4, 0x00000000);
    checkDefVal(CfgIntMemData_5, 0x00000000);
    checkDefVal(CfgIntMemData_6, 0x00000000);
    checkDefVal(CfgIntMemData_7, 0x00000000);
    checkDefVal(CfgDMECCErrorMode, 0x00000000);
    checkDefVal(CfgDMDisableEccCheck, 0x00000000);
    return OK;
}

/*
 * led_defChk - Checks the LED Slave registers for the default values
 */
int led_defChk (void) {
    checkDefVal(CfgStatusPEnables, 0x00000000);
    checkDefVal(CfgStatusNEnables, 0x00000000);
    checkDefVal(CfgStatusSwOverRide, 0x00000000);
    checkDefVal(CfgGlitchCatchPeriod, 0xffffffff);
    checkDefVal(CfgLedOnPeriod, 0xffffffff);
    checkDefVal(CfgLedOffPeriod, 0xffffffff);
    checkDefVal(CfgEventPEnables, 0x00000000);
    checkDefVal(CfgEventNEnables, 0x00000000);
    checkDefVal(CfgWinkCtrlOnTimer, 0x03ffffff);
    checkDefVal(CfgWinkCtrlOffTimer, 0x03ffffff);
    checkDefVal(CfgExcessChkMsbTimer, 0x00000000);
    checkDefVal(CfgExcessChkLsbTimer, 0xffffffff);
    checkDefVal(CfgEventSwOverRide, 0x00000000);
    checkDefVal(CfgEventOperation, 0x00000000);
    checkDefVal(CfgEventSw, 0x00000000);
    checkDefVal(CfgOnPolarityForStatusLeds, 0x00000002);
    checkDefVal(CfgOnPolarityForEventLeds, 0x00000002);
    return OK;
}

/*
 * mdio_defChk - Checks the MDIO Slave registers for the default values
 */
int mdio_defChk (void) {
    checkDefVal(VarRegMDIOCommand, 0x00000000);
    checkDefVal(CfgRegMDIOMode, 0x00000001);
    checkDefVal(CfgRegMDIOAutoScan, 0x00078420);
    return OK;
}

/*
 * queuemanager_defChk - Checks the Queue Manager Slave registers for the default values
 */
int queuemanager_defChk (void) {
    checkDefVal(CfgFreePageTableInit, 0x00000000);
    checkDefVal(CfgQueueManagerReadDisable, 0x00000000);
    checkDefVal(CfgPageFullPntr, 0x0000001f);
    checkDefVal(CfgQueueManagerEnable, 0x00000000);
    checkDefVal(CfgMaxPageCountWrQnum, 0x00000000);
    checkDefVal(CfgMaxPageCountWr, 0x00001fff);
    checkDefVal(CfgMaxPageCountRdQnum, 0x00000000);
    checkDefVal(CfgRsvdPageCountWrQnum, 0x00000000);
    checkDefVal(CfgRsvdPageCountWr, 0x00000002);
    checkDefVal(CfgTotalRsvdPageCount, 0x00000010);
    checkDefVal(CfgRsvdPageCountRdQnum, 0x00000000);
    checkDefVal(CfgUsedPageCountRdQnum, 0x00000000);
    checkDefVal(CfgStartRsvdPoolPagePntr, 0x00000008);
    checkDefVal(CfgStartFreePoolPagePntr, 0x000000ff);
    checkDefVal(CfgQueueFillReadQnum, 0x00000000);
    checkDefVal(CfgPauseFrameOnThreshold, 0x00000005);
    checkDefVal(CfgPauseFrameOffThreshold, 0x00000007);
    checkDefVal(CfgQmFptDisableEccCheck, 0x00000000);
    checkDefVal(CfgQmPltDisableEccCheck, 0x00000000);
    return OK;
}

/*
 * rxdropcontrol_defChk - Checks the Rx Drop Control Slave registers for the default values
 */
int rxdropcontrol_defChk (void) {
    checkDefVal(CfgMcastWindowSize, 0x00009502);
    checkDefVal(CfgBcastWindowSize, 0x00009502);
    checkDefVal(CfgMcastLimitCount, 0x00000000);
    checkDefVal(CfgBcastLimitCount, 0x00000000);
    checkDefVal(CfgLimitMacAddrLsb0, 0xffffffff);
    checkDefVal(CfgLimitMacAddrMsb0, 0x0000ffff);
    checkDefVal(CfgLimitMacAddrLsb1, 0xffffffff);
    checkDefVal(CfgLimitMacAddrMsb1, 0x0000ffff);
    checkDefVal(CfgLimitMacAddrLsb2, 0xffffffff);
    checkDefVal(CfgLimitMacAddrMsb2, 0x0000ffff);
    checkDefVal(CfgLimitMacAddrLsb3, 0xffffffff);
    checkDefVal(CfgLimitMacAddrMsb3, 0x0000ffff);
    checkDefVal(CfgCtrlMacAddrLsb0, 0xffffffff);
    checkDefVal(CfgCtrlMacAddrMsb0, 0x0000ffff);
    checkDefVal(CfgCtrlMacAddrLsb1, 0xffffffff);
    checkDefVal(CfgCtrlMacAddrMsb1, 0x0000ffff);
    checkDefVal(CfgLimitMaskMacAddrLsb0, 0xffffffff);
    checkDefVal(CfgLimitMaskMacAddrMsb0, 0x0000ffff);
    checkDefVal(CfgLimitMaskMacAddrLsb1, 0xffffffff);
    checkDefVal(CfgLimitMaskMacAddrMsb1, 0x0000ffff);
    checkDefVal(CfgLimitMaskMacAddrLsb2, 0xffffffff);
    checkDefVal(CfgLimitMaskMacAddrMsb2, 0x0000ffff);
    checkDefVal(CfgLimitMaskMacAddrLsb3, 0xffffffff);
    checkDefVal(CfgLimitMaskMacAddrMsb3, 0x0000ffff);
    checkDefVal(CfgMaskControlMacAddrLsb0, 0xffffffff);
    checkDefVal(CfgMaskControlMacAddrMsb0, 0x0000ffff);
    checkDefVal(CfgMaskControlMacAddrLsb1, 0xffffffff);
    checkDefVal(CfgMaskControlMacAddrMsb1, 0x0000ffff);
    checkDefVal(CfgMaxFrmSize, 0x00002580);
    checkDefVal(CfgMinFrmSize, 0x00000040);
    checkDefVal(CfgDefault, 0x00000010);
    checkDefVal(CfgFilters, 0x00007000);
    checkDefVal(CfgMPLSCtrl0, 0x02884700);
    checkDefVal(CfgMPLSCtrl1, 0x02884800);
    checkDefVal(CfgMPLSCtrl2, 0x00000000);
    checkDefVal(CfgMPLSCtrl3, 0x00000000);
    checkDefVal(CfgMPLSCtrlD, 0x00000200);
    checkDefVal(CfgMPLSLLSPMask0, 0xfffff000);
    checkDefVal(CfgMPLSLLSPMask1, 0xfffff000);
    checkDefVal(CfgMPLSLLSPMask2, 0xfffff000);
    checkDefVal(CfgMPLSLLSPMask3, 0xfffff000);
    checkDefVal(CfgMPLSLLSPMask4, 0xfffff000);
    checkDefVal(CfgMPLSLLSPMask5, 0xfffff000);
    checkDefVal(CfgMPLSLLSPMask6, 0xfffff000);
    checkDefVal(CfgMPLSLLSPMask7, 0xfffff000);
    checkDefVal(CfgMPLSLLSPMatch0, 0x00000000);
    checkDefVal(CfgMPLSLLSPMatch1, 0x00001000);
    checkDefVal(CfgMPLSLLSPMatch2, 0x00002000);
    checkDefVal(CfgMPLSLLSPMatch3, 0x00003000);
    checkDefVal(CfgMPLSLLSPMatch4, 0x00004000);
    checkDefVal(CfgMPLSLLSPMatch5, 0x00005000);
    checkDefVal(CfgMPLSLLSPMatch6, 0x00006000);
    checkDefVal(CfgMPLSLLSPMatch7, 0x00007000);
    checkDefVal(CfgMPLSLLSPCtrl0, 0x00000000);
    checkDefVal(CfgMPLSLLSPCtrl1, 0x00000000);
    checkDefVal(CfgMPLSLLSPCtrl2, 0x00000000);
    checkDefVal(CfgMPLSLLSPCtrl3, 0x00000000);
    checkDefVal(CfgMPLSLLSPCtrl4, 0x00000000);
    checkDefVal(CfgMPLSLLSPCtrl5, 0x00000000);
    checkDefVal(CfgMPLSLLSPCtrl6, 0x00000000);
    checkDefVal(CfgMPLSLLSPCtrl7, 0x00000000);
    checkDefVal(CfgMPLSLLSPCtrlD, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE0, 0x00028100);
    checkDefVal(CfgVLANEtherTypeE1, 0x000288a8);
    checkDefVal(CfgVLANEtherTypeE2, 0x00028200);
    checkDefVal(CfgVLANEtherTypeE3, 0x00029100);
    checkDefVal(CfgVLANEtherTypeE4, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE5, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE6, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE7, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE8, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE9, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE10, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE11, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE12, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE13, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE14, 0x00000000);
    checkDefVal(CfgVLANEtherTypeE15, 0x00000000);
    checkDefVal(CfgSVLANEtherType, 0x00000000);
    checkDefVal(CfgSVLANCtrl, 0x00040000);
    checkDefVal(CfgNoVLANCtrl0, 0x00000000);
    checkDefVal(CfgNoVLANCtrl1, 0x00000000);
    checkDefVal(CfgIngressPrioMap0, 0x00000000);
    checkDefVal(CfgIngressPrioMap1, 0x00000000);
    checkDefVal(CfgIngressPrioMap2, 0x00000000);
    checkDefVal(CfgIngressPrioMap3, 0x00000000);
    checkDefVal(CfgIngressPrioMap4, 0x00000000);
    checkDefVal(CfgIngressPrioMap5, 0x00000000);
    checkDefVal(CfgIngressPrioMap6, 0x00000000);
    checkDefVal(CfgIngressPrioMap7, 0x00000000);
    checkDefVal(CfgIngressPrioMap8, 0x00000000);
    checkDefVal(CfgIngressPrioMap9, 0x00000000);
    checkDefVal(CfgIngressPrioMap10, 0x00000000);
    checkDefVal(CfgIngressPrioMap11, 0x00000000);
    checkDefVal(CfgIngressPrioMap12, 0x00000000);
    checkDefVal(CfgIngressPrioMap13, 0x00000000);
    checkDefVal(CfgIngressPrioMap14, 0x00000000);
    checkDefVal(CfgIngressExtdPrioMap0, 0x00000000);
    checkDefVal(CfgIngressExtdPrioMap1, 0x00000000);
    checkDefVal(CfgMACDAMatchLSB0, 0xc2000000);
    checkDefVal(CfgMACDAMatchMSB0, 0x00000180);
    checkDefVal(CfgMACDAMatchLSB1, 0xffffffff);
    checkDefVal(CfgMACDAMatchMSB1, 0x0000ffff);
    checkDefVal(CfgMACDAMatchLSB2, 0x00000000);
    checkDefVal(CfgMACDAMatchMSB2, 0x00000000);
    checkDefVal(CfgMACDAMatchLSB3, 0x00000000);
    checkDefVal(CfgMACDAMatchMSB3, 0x00000000);
    checkDefVal(CfgMACDAMatchLSB4, 0x00000000);
    checkDefVal(CfgMACDAMatchMSB4, 0x00000000);
    checkDefVal(CfgMACDAMatchLSB5, 0x00000000);
    checkDefVal(CfgMACDAMatchMSB5, 0x00000000);
    checkDefVal(CfgMACDAMatchLSB6, 0x00000000);
    checkDefVal(CfgMACDAMatchMSB6, 0x00000000);
    checkDefVal(CfgMACDAMatchLSB7, 0x00000000);
    checkDefVal(CfgMACDAMatchMSB7, 0x00000000);
    checkDefVal(CfgMACDAMaskLSB0, 0xff000000);
    checkDefVal(CfgMACDAMaskMSB0, 0x0000ffff);
    checkDefVal(CfgMACDAMaskLSB1, 0xffffffff);
    checkDefVal(CfgMACDAMaskMSB1, 0x0000ffff);
    checkDefVal(CfgMACDAMaskLSB2, 0x00000000);
    checkDefVal(CfgMACDAMaskMSB2, 0x00000000);
    checkDefVal(CfgMACDAMaskLSB3, 0x00000000);
    checkDefVal(CfgMACDAMaskMSB3, 0x00000000);
    checkDefVal(CfgMACDAMaskLSB4, 0x00000000);
    checkDefVal(CfgMACDAMaskMSB4, 0x00000000);
    checkDefVal(CfgMACDAMaskLSB5, 0x00000000);
    checkDefVal(CfgMACDAMaskMSB5, 0x00000000);
    checkDefVal(CfgMACDAMaskLSB6, 0x00000000);
    checkDefVal(CfgMACDAMaskMSB6, 0x00000000);
    checkDefVal(CfgMACDAMaskLSB7, 0x00000000);
    checkDefVal(CfgMACDAMaskMSB7, 0x00000000);
    checkDefVal(CfgMACDACtrl0, 0x00000000);
    checkDefVal(CfgMACDACtrl1, 0x00000000);
    checkDefVal(CfgMACDACtrl2, 0x00000000);
    checkDefVal(CfgMACDACtrl3, 0x00000000);
    checkDefVal(CfgMACDACtrl4, 0x00000000);
    checkDefVal(CfgMACDACtrl5, 0x00000000);
    checkDefVal(CfgMACDACtrl6, 0x00000000);
    checkDefVal(CfgMACDACtrl7, 0x00000000);
    checkDefVal(CfgHashSel, 0x00000001);
    checkDefVal(CfgTypeCtrl0, 0x00100100);
    checkDefVal(CfgTypeCtrl1, 0x00100d00);
    checkDefVal(CfgTypeCtrl2, 0x00c00300);
    checkDefVal(CfgTypeCtrl3, 0x00c00500);
    checkDefVal(CfgTypeCtrl4, 0x00c00700);
    checkDefVal(CfgTypeCtrl5, 0x00c00900);
    checkDefVal(CfgTypeCtrl6, 0x00c00b00);
    checkDefVal(CfgTypeCtrl7, 0x00c00d00);
    checkDefVal(CfgTypeCtrl8, 0x01006b00);
    checkDefVal(CfgTypeCtrl9, 0x01007100);
    checkDefVal(CfgTypeCtrl10, 0x01007b00);
    checkDefVal(CfgTypeCtrl11, 0x01007f00);
    checkDefVal(CfgTypeCtrl12, 0x01013700);
    checkDefVal(CfgTypeCtrl13, 0x0101e700);
    checkDefVal(CfgTypeCtrl14, 0x01026f00);
    checkDefVal(CfgTypeCtrl15, 0x010dbb00);
    checkDefVal(CfgTypeCtrl16, 0x01101100);
    checkDefVal(CfgTypeCtrl17, 0x01101300);
    checkDefVal(CfgTypeCtrl18, 0x0110e100);
    checkDefVal(CfgTypeCtrl19, 0x0110cf00);
    checkDefVal(CfgTypeCtrl20, 0x0110d100);
    checkDefVal(CfgTypeCtrl21, 0x00000100);
    checkDefVal(CfgTypeCtrl22, 0x00000100);
    checkDefVal(CfgTypeCtrl23, 0x00000100);
    checkDefVal(CfgTypeCtrlD, 0x00000100);
    checkDefVal(CfgNetBIOSCtrl, 0x00000100);
    checkDefVal(CfgIPXCtrl, 0x00000100);
    checkDefVal(CfgAppleTalkCtrl, 0x00000100);
    checkDefVal(CfgOtherLLCCtrl, 0x00000100);
    checkDefVal(Cfg8021HBTCtrl, 0x00000100);
    checkDefVal(CfgUnknownProCtrl, 0x00000100);
    checkDefVal(CfgPureLLCCtrl0, 0x00000d00);
    checkDefVal(CfgPureLLCCtrl1, 0x00008500);
    checkDefVal(CfgPureLLCCtrl2, 0x0001c100);
    checkDefVal(CfgPureLLCCtrl3, 0x0001fd00);
    checkDefVal(CfgDSCPTypeMatch0, 0x00010800);
    checkDefVal(CfgDSCPTypeMatch1, 0x000286dd);
    checkDefVal(CfgDSCPTypeMatch2, 0x00038847);
    checkDefVal(CfgDSCPTypeMatch3, 0x00038848);
    checkDefVal(CfgDSCPTypeMatch4, 0x00000000);
    checkDefVal(CfgDSCPTypeMatch5, 0x00000000);
    checkDefVal(CfgDSCPTypeMatch6, 0x00000000);
    checkDefVal(CfgDSCPTypeMatch7, 0x00000000);
    checkDefVal(CfgZFieldEncode0, 0x00000000);
    checkDefVal(CfgDSCPDefaultMatch, 0x00000400);
    checkDefVal(CfgDSCPVerMismatchCtrl, 0x00000400);
    checkDefVal(CfgIPCtrl0, 0x00001a00);
    checkDefVal(CfgIPCtrl1, 0x00004600);
    checkDefVal(CfgIPCtrl2, 0x00000a00);
    checkDefVal(CfgIPCtrl3, 0x00000600);
    checkDefVal(CfgIPCtrlD, 0x00000200);
    checkDefVal(CfgMisc, 0x00000202);
    checkDefVal(CfgMiscReadOnThreshold, 0x00000002);
    checkDefVal(CfgMiscReadOffThreshold, 0x00000000);
    checkDefVal(CfgMiscReadTimerValue, 0x00000064);
    checkDefVal(CfgMiscCPUAccess, 0x00000000);
    checkDefVal(CfgMiscCPUWriteAddress, 0x00000000);
    checkDefVal(CfgMiscCPUReadAddress, 0x00000000);
    checkDefVal(CfgMiscCPUCommitPointer, 0x00000000);
    checkDefVal(CfgMiscCPUWriteData_0, 0x00000000);
    checkDefVal(CfgMiscCPUWriteData_1, 0x00000000);
    checkDefVal(CfgMiscCPUWriteData_2, 0x00000000);
    checkDefVal(CfgAsynFIFOFullThreshold, 0x00000005);
    return OK;
}

/*
 * rxdropcontrolstat_defChk - Checks the Receive Drop Controller Statistics Slave registers for the default values
 */
int rxdropcontrolstat_defChk (void) {
    checkDefVal(CfgOVLANCtrl, 0x00000000);
    checkDefVal(CfgOVLANCtrlData, 0x00000000);
    checkDefVal(CfgIVLANCtrl, 0x00000000);
    checkDefVal(CfgIVLANCtrlData, 0x00000000);
    checkDefVal(CfgVLANID, 0x00000000);
    checkDefVal(CfgVLANIDData, 0x00000000);
    checkDefVal(CfgRd256x32RxVlanTagRamReg, 0x00000000);
    checkDefVal(CfgHashCtrl, 0x00000000);
    checkDefVal(CfgDSCPAssign, 0x00000000);
    checkDefVal(CfgProgBitIDA, 0x00000000);
    checkDefVal(CfgFunnel, 0x00000000);
    checkDefVal(CfgSourcePort, 0x00000000);
    checkDefVal(CfgDestinationPort, 0x00000000);
    checkDefVal(CfgProgRegIDE, 0x00000000);
    checkDefVal(CfgOVLANRdCtrl, 0x00000000);
    checkDefVal(CfgIVLANRdCtrl, 0x00000000);
    checkDefVal(CfgVLANIDRd, 0x00000000);
    checkDefVal(CfgHashRdCtrl, 0x00000000);
    checkDefVal(CfgDSCPAssignRd, 0x00000000);
    return OK;
}

/*
 * rxdropcontrolwred_defChk - Checks the Rx Drop Controller WRED Slave registers for the default values
 */
int rxdropcontrolwred_defChk (void) {
    checkDefVal(CfgWREDMode, 0xffffff00);
    checkDefVal(CfgWREDQSmoothingMode, 0x00000000);
    checkDefVal(CfgWREDMaxThrQ_0, 0x00000000);
    checkDefVal(CfgWREDMaxThrQ_1, 0x00000000);
    checkDefVal(CfgWREDMaxThrQ_2, 0x00000000);
    checkDefVal(CfgWREDMaxThrQ_3, 0x00000000);
    checkDefVal(CfgWREDMaxThrQ_4, 0x00000000);
    checkDefVal(CfgWREDMaxThrQ_5, 0x00000000);
    checkDefVal(CfgWREDMaxThrQ_6, 0x00000000);
    checkDefVal(CfgWREDMaxThrQ_7, 0x00000000);
    checkDefVal(CfgWREDMinThrFactorQ_0, 0x00000000);
    checkDefVal(CfgWREDMinThrFactorQ_1, 0x00000000);
    checkDefVal(CfgWREDMinThrFactorQ_2, 0x00000000);
    checkDefVal(CfgWREDMinThrFactorQ_3, 0x00000000);
    checkDefVal(CfgWREDMinThrFactorQ_4, 0x00000000);
    checkDefVal(CfgWREDMinThrFactorQ_5, 0x00000000);
    checkDefVal(CfgWREDMinThrFactorQ_6, 0x00000000);
    checkDefVal(CfgWREDMinThrFactorQ_7, 0x00000000);
    checkDefVal(CfgBPDUThreshold_0, 0x00040000);
    checkDefVal(CfgBPDUThreshold_1, 0x00040000);
    checkDefVal(CfgBPDUThreshold_2, 0x00040000);
    checkDefVal(CfgBPDUThreshold_3, 0x00040000);
    checkDefVal(CfgBPDUThreshold_4, 0x00040000);
    checkDefVal(CfgBPDUThreshold_5, 0x00040000);
    checkDefVal(CfgBPDUThreshold_6, 0x00040000);
    checkDefVal(CfgBPDUThreshold_7, 0x00040000);
    checkDefVal(CfgTailDropThreshold_0, 0x00080000);
    checkDefVal(CfgTailDropThreshold_1, 0x00080000);
    checkDefVal(CfgTailDropThreshold_2, 0x00080000);
    checkDefVal(CfgTailDropThreshold_3, 0x00080000);
    checkDefVal(CfgTailDropThreshold_4, 0x00080000);
    checkDefVal(CfgTailDropThreshold_5, 0x00080000);
    checkDefVal(CfgTailDropThreshold_6, 0x00080000);
    checkDefVal(CfgTailDropThreshold_7, 0x00080000);
    checkDefVal(CfgWREDAvgFctQ_0, 0x00000000);
    checkDefVal(CfgWREDAvgFctQ_1, 0x00000000);
    checkDefVal(CfgWREDAvgFctQ_2, 0x00000000);
    checkDefVal(CfgWREDAvgFctQ_3, 0x00000000);
    checkDefVal(CfgWREDAvgFctQ_4, 0x00000000);
    checkDefVal(CfgWREDAvgFctQ_5, 0x00000000);
    checkDefVal(CfgWREDAvgFctQ_6, 0x00000000);
    checkDefVal(CfgWREDAvgFctQ_7, 0x00000000);
    checkDefVal(CfgTimerBasedAvgLenEn, 0x00000000);
    checkDefVal(CfgWREDAvgQSizeTimer_0, 0x000004b0);
    checkDefVal(CfgWREDAvgQSizeTimer_1, 0x000004b0);
    checkDefVal(CfgWREDAvgQSizeTimer_2, 0x000004b0);
    checkDefVal(CfgWREDAvgQSizeTimer_3, 0x000004b0);
    checkDefVal(CfgWREDAvgQSizeTimer_4, 0x000004b0);
    checkDefVal(CfgWREDAvgQSizeTimer_5, 0x000004b0);
    checkDefVal(CfgWREDAvgQSizeTimer_6, 0x000004b0);
    checkDefVal(CfgWREDAvgQSizeTimer_7, 0x000004b0);
    checkDefVal(CfgWREDProbabilityTable, 0x00000000);
    checkDefVal(CfgWREDDropProbability, 0x00000000);
    checkDefVal(CfgWREDGreenThreshold, 0x00000000);
    checkDefVal(CfgWREDYellowThreshold, 0x00000000);
    checkDefVal(CfgWREDOrangeThreshold, 0x00000000);
    checkDefVal(CfgWREDRedThreshold, 0x00000000);
    checkDefVal(CfgEccCheckEn, 0x00000001);
    checkDefVal(CfgInsertEccErrorMode, 0x00000000);
    return OK;
}

/*
 * rxlinetocpu_defChk - Checks the Receiver Line to CPU Slave registers for the default values
 */
int rxlinetocpu_defChk (void) {
    checkDefVal(CfgLineToCpuFullPacketMode, 0x00000000);
    checkDefVal(CfgLineToCpuDisableRead, 0x00000000);
    checkDefVal(CfgLineToCpuNearFullThresh, 0x00000044);
    checkDefVal(CfgLineToCpuNearEmptyThresh, 0x00000002);
    checkDefVal(CfgLineToCpuEccChkDis, 0x00000000);
    checkDefVal(CfgLineToCpuDropEn, 0x000000ff);
    checkDefVal(CfgLineToCpuFifoTailDropEn, 0x00000001);
    checkDefVal(CfgLineToCpuPktDropEn, 0x00000001);
    return OK;
}

/*
 * rxmac_defChk - Checks the Receive MAC Slave registers for the default values
 */
int rxmac_defChk (void) {
    checkDefVal(CfgRegRxMACModes, 0x00d05e37);
    checkDefVal(CfgRegRxMaxFSize, 0x0000fff0);
    checkDefVal(CfgRegRxDAValLSB, 0x00000000);
    checkDefVal(CfgRegRxDAValMSB, 0x00000000);
    checkDefVal(CfgRegRxSAValLSB, 0x00000000);
    checkDefVal(CfgRegRxSAValMSB, 0x00000000);
    checkDefVal(CfgRegRxCPUValLSB, 0x00000000);
    checkDefVal(CfgRegRxCPUValMSB, 0x00000000);
    checkDefVal(CfgRegRxMCASTPassFilterLSB, 0x00000000);
    checkDefVal(CfgRegRxMCASTPassFilterMSB, 0x00000000);
    checkDefVal(CfgRegRxVLANTagValue, 0x00000000);
    checkDefVal(CfgRegRxPauseMaxFSize, 0x000005ee);
    checkDefVal(CfgRegRxPauseMinFSize, 0x00000040);
    return OK;
}

/*
 * rxpspiprical_defChk - Checks the Receive Primary SPI Slave registers for the default values
 */
int rxpspiprical_defChk (void) {
    checkDefVal(CfgMemRxpSpiCalPri, 0x00000000);
    return OK;
}

/*
 * rxpspishdwcal_defChk - Checks the Receive Primary SPI Slave registers for the default values
 */
int rxpspishdwcal_defChk (void) {
    checkDefVal(CfgMemRxpSpiCalShadow, 0x00000000);
    return OK;
}

/*
 * rxpspi_defChk - Checks the Receive Primary SPI Slave registers for the default values
 */
int rxpspi_defChk (void) {
    checkDefVal(CfgRegRxpSpiSetup, 0x00000000);
    checkDefVal(CfgRegRxpSpiLocalPortMaxBurst, 0x00004444);
    checkDefVal(CfgRegRxpSpiCascadePortMaxBurst, 0x00004444);
    checkDefVal(CfgRegRxpSpiMaintPortMaxBurst, 0x00004444);
    checkDefVal(CfgRegRxpSpiLocalBWMeterWin, 0x000002bc);
    checkDefVal(CfgRegRxpSpiLocalMinMaxCredit, 0x23281b58);
    checkDefVal(CfgRegRxpSpiCascadeBWMeterWin, 0x000002bc);
    checkDefVal(CfgRegRxpSpiCascadeMinMaxCredit, 0x23281b58);
    checkDefVal(CfgRegRxpSpiMaintBWMeterWin, 0x000002bc);
    checkDefVal(CfgRegRxpSpiMaintMinMaxCredit, 0x23281b58);
    checkDefVal(CfgRegRxpSpiAddressMap, 0x00000000);
    checkDefVal(CfgRegRxpSpiAlpha, 0x00000100);
    checkDefVal(CfgRegRxpSpiDataMaxTLsb, 0x00000000);
    checkDefVal(CfgRegRxpSpiDataMaxTMsb, 0x00000000);
    checkDefVal(CfgRegRxpSpiIntFifoThr, 0x000000a0);
    checkDefVal(CfgRegRxpSpiOutFifoThr, 0x000001c6);
    checkDefVal(CfgRegRxpSpiMinMdrrWindow, 0x01000100);
    checkDefVal(CfgRegRxpSpiMinMdrrCredit, 0x00003e80);
    checkDefVal(CfgRegRxpSpiMaxMdrrWindow, 0x01000100);
    checkDefVal(CfgRegRxpSpiMaxMdrrCredit, 0x00007d00);
    checkDefVal(CfgRegRxpspiInPipeBurstCnt, 0x00000025);
    checkDefVal(CfgRegRxpSpiMaxPacketSize, 0x00022580);
    checkDefVal(CfgRegRxpSpiHarMdrrStopThr, 0x080003e8);
    checkDefVal(CfgRegRxpSpiHMMisc, 0x00000000);
    checkDefVal(CfgRegRxpSpiDESKEWMisc, 0x00000002);
    checkDefVal(CfgRegRxpSpiDESKEWTraPat0, 0x000ffc00);
    checkDefVal(CfgRegRxpSpiDESKEWTraPat1, 0x000003ff);
    checkDefVal(CfgRegRxpSpiDESKEWReg0, 0x00000000);
    checkDefVal(CfgRegRxpSpiDESKEWReg1, 0x00000000);
    checkDefVal(CfgRegRxpSpiIntLBFifoRdThresh, 0x00000008);
    return OK;
}

/*
 * rxpspistat_defChk - Checks the Receive SPI Primary Statistics Slave registers for the default values
 */
int rxpspistat_defChk (void) {
    checkDefVal(CfgRegRxpSpiCalSetup, 0x00000000);
    checkDefVal(CfgRegRxpSpiDip2Thr, 0x00000f1e);
    return OK;
}

/*
 * rxsspiprical_defChk - Checks the Receive Secondary SPI Slave registers for the default values
 */
int rxsspiprical_defChk (void) {
    checkDefVal(CfgMemRxsSpiCalPri, 0x00000000);
    return OK;
}

/*
 * rxsspishdwcal_defChk - Checks the Receive Secondary SPI Slave registers for the default values
 */
int rxsspishdwcal_defChk (void) {
    checkDefVal(CfgMemRxsSpiCalShadow, 0x00000000);
    return OK;
}

/*
 * rxsspi_defChk - Checks the Receive Secondary SPI Slave registers for the default values
 */
int rxsspi_defChk (void) {
    checkDefVal(CfgRegRxsSpiSetup, 0x00000000);
    checkDefVal(CfgRegRxsSpiLocalPortMaxBurst, 0x00004444);
    checkDefVal(CfgRegRxsSpiCascadePortMaxBurst, 0x00004444);
    checkDefVal(CfgRegRxsSpiLocalBWMeterWin, 0x000002bc);
    checkDefVal(CfgRegRxsSpiLocalMinMaxCredit, 0x23281b58);
    checkDefVal(CfgRegRxsSpiCascadeBWMeterWin, 0x000002bc);
    checkDefVal(CfgRegRxsSpiCascadeMinMaxCredit, 0x23281b58);
    checkDefVal(CfgRegRxsSpiAddressMap, 0x00000000);
    checkDefVal(CfgRegRxsSpiAlpha, 0x00000100);
    checkDefVal(CfgRegRxsSpiDataMaxTLsb, 0x00000000);
    checkDefVal(CfgRegRxsSpiDataMaxTMsb, 0x00000000);
    checkDefVal(CfgRegRxsSpiThr, 0x000000a0);
    checkDefVal(CfgRegRxsSpiOutFifoThr, 0x000001c6);
    checkDefVal(CfgRegRxsSpiMinMdrrWindow, 0x01000100);
    checkDefVal(CfgRegRxsSpiMinMdrrCredit, 0x00003e80);
    checkDefVal(CfgRegRxsSpiMaxMdrrWindow, 0x01000100);
    checkDefVal(CfgRegRxsSpiMaxMdrrCredit, 0x00007d00);
    checkDefVal(CfgRegRxsSpiMaxPacketSize, 0x00022580);
    checkDefVal(CfgRegRxsspiInPipeBurstCnt, 0x00000025);
    checkDefVal(CfgRegRxsSpiHMMisc, 0x00000000);
    checkDefVal(CfgRegRxsSpiDESKEWMisc, 0x00000002);
    checkDefVal(CfgRegRxsSpiDESKEWTraPat0, 0x000ffc00);
    checkDefVal(CfgRegRxsSpiDESKEWTraPat1, 0x000003ff);
    checkDefVal(CfgRegRxsSpiDESKEWReg0, 0x00000000);
    checkDefVal(CfgRegRxsSpiDESKEWReg1, 0x00000000);
    checkDefVal(CfgRegRxsSpiIntLBFifoRdThresh, 0x00000008);
    return OK;
}

/*
 * rxsspistat_defChk - Checks the Receive Secondary SPI Slave registers for the default values
 */
int rxsspistat_defChk (void) {
    checkDefVal(CfgRegRxsSpiCalSetup, 0x00000000);
    checkDefVal(CfgRegRxsSpiDip2Thr, 0x00000f1e);
    return OK;
}

/*
 * rxxauixmac_defChk - Checks the Receive XAUI XMAC Slave registers for the default values
 */
int rxxauixmac_defChk (void) {
    checkDefVal(CfgRxXauiXmac, 0x00000000);
    checkDefVal(CfgRegRxRSNoPrmbleReplace, 0x00000000);
    checkDefVal(CfgDontRemovePreAmble, 0x00000000);
    return OK;
}

/*
 * shadowregs_defChk - Checks the Shadow Slave registers for the default values
 */
int shadowregs_defChk (void) {
    checkDefVal(CfgShadowEventTrigSource, 0x00000001);
    checkDefVal(CfgCpuShadowEvent, 0x00000000);
    checkDefVal(CfgShadowTimerMsb, 0x00000000);
    checkDefVal(CfgShadowTimerLsb, 0x00ffffff);
    return OK;
}

/*
 * txcputoline_defChk - Checks the Transmit CPU To Line Slave registers for the default values
 */
int txcputoline_defChk (void) {
    checkDefVal(CfgCpuToLineEccChkDis, 0x00000001);
    checkDefVal(CfgCpuToLineBusEn, 0x00000001);
    checkDefVal(CfgCpuToLineFullPacketMode, 0x00000000);
    checkDefVal(CfgCpuToLineDisableRead, 0x00000000);
    checkDefVal(CfgCpuToLineCpuWrData0, 0x00000000);
    checkDefVal(CfgCpuToLineCpuWrData1, 0x00000000);
    checkDefVal(CfgCpuToLineCpuWrData2, 0x00000000);
    checkDefVal(CfgCpuToLineCpuWrDataDone, 0x00000000);
    checkDefVal(CfgCpuToLineReadOnThresh, 0x00000000);
    checkDefVal(CfgCpuToLineReadOffThresh, 0x00000000);
    checkDefVal(CfgCpuToLinePktDropEn, 0x00000001);
    checkDefVal(CfgCpuToLineFifoTailDropEn, 0x00000001);
    checkDefVal(CfgCpuToLineReadTimerValue, 0x0000000a);
    return OK;
}

/*
 * txmaccfg_defChk - Checks the Transmit MAC Slave registers for the default values
 */
int txmaccfg_defChk (void) {
    checkDefVal(CfgRegTxMACModes, 0x0000000e);
    checkDefVal(CfgRegTxMaxFSize, 0x00002580);
    checkDefVal(CfgRegTxDAValLSB, 0x00000000);
    checkDefVal(CfgRegTxDAValMSB, 0x00000000);
    checkDefVal(CfgRegTxSAValLSB, 0x00000000);
    checkDefVal(CfgRegTxSAValMSB, 0x00000000);
    checkDefVal(CfgRegTxPauseTimerValue, 0x0000ffff);
    checkDefVal(CfgTxDebugEopCharacter, 0x000001fe);
    checkDefVal(CfgRegTxRSFaultTrafficBP, 0x00000001);
    checkDefVal(CfgRegTxRSLocalFaultEn, 0x00000001);
    checkDefVal(CfgRegTxRSLocalFaultMode, 0x00000002);
    checkDefVal(CfgRegTxRSRemoteFaultEn, 0x00000001);
    checkDefVal(CfgRegTxRSLinkFaultRecoveryMode, 0x00000001);
    checkDefVal(CfgRegTxRSCPUFaultRecovery, 0x00000000);
    checkDefVal(CfgProgIPGCount, 0x00000000);
    return OK;
}

/*
 * txmemcommon_defChk - Checks the Transmit Memory Slave registers for the default values
 */
int txmemcommon_defChk (void) {
    checkDefVal(CfgEgressHeaderBigEndian_P0, 0x00000001);
    checkDefVal(CfgEgressHeaderBigEndian_P1, 0x00000001);
    checkDefVal(CfgTxMemInsertHdr_P0, 0x00000000);
    checkDefVal(CfgTxMemHdrValMSB_P0, 0x80000000);
    checkDefVal(CfgTxMemHdrValLSB_P0, 0x00000000);
    checkDefVal(CfgTxMemInsertHdr_P1, 0x00000000);
    checkDefVal(CfgInputFrmNpuIsPED_P0, 0x00000001);
    checkDefVal(CfgInputFrmNpuIsPED_P1, 0x00000001);
    checkDefVal(CfgTxMemHdrValMSB_P1, 0x80000000);
    checkDefVal(CfgTxMemHdrValLSB_P1, 0x00000000);
    checkDefVal(CfgTxMemMgrMaxPktSzPrt0, 0x00002580);
    checkDefVal(CfgTxMemMgrMaxPktSzPrt1, 0x00002580);
    checkDefVal(CfgTxMemMgrMinPktSzPrt0, 0x00000021);
    checkDefVal(CfgTxMemMgrMinPktSzPrt1, 0x00000021);
    checkDefVal(CfgTxMemMgrDisMaxPktSzFilterPrt0, 0x00000000);
    checkDefVal(CfgTxMemMgrDisMaxPktSzFilterPrt1, 0x00000000);
    checkDefVal(CfgTxMemMgrDisMinPktSzFilterPrt0, 0x00000000);
    checkDefVal(CfgTxMemMgrDisMinPktSzFilterPrt1, 0x00000000);
    return OK;
}

/*
 * txmemmanager_defChk - Checks the Transmit Memory Manager Slave registers for the default values
 */
int txmemmanager_defChk (void) {
    checkDefVal(CfgTxMemMgrCrcChkDis, 0x00000000);
    checkDefVal(CfgTxMemMgrRdDis, 0x00000000);
    checkDefVal(CfgTxMemMgrECCChkDis, 0x00000000);
    checkDefVal(CfgTxMemMgrTailDropEn, 0x00000000);
    checkDefVal(CfgTxMemMgrCrcErrPktDropDis, 0x00000000);
    checkDefVal(CfgTxMemMgrAEopErrPktDropDis, 0x00000000);
    checkDefVal(CfgTxMemMgrNonPktModeONThrsh, 0x0000000a);
    checkDefVal(CfgTxMemMgrNonPktModeOFFThrsh, 0x00000000);
    checkDefVal(CfgTxMemMgrReadTimerValue, 0x00000064);
    checkDefVal(CfgDontDropRedIdMisMatchPkts, 0x00000001);
    checkDefVal(CfgRedHawkIdMatchReg, 0x000000c0);
    checkDefVal(CfgTxMemMgrCPUAccess, 0x00000000);
    checkDefVal(CfgTxMemMgrCPUWriteAddress, 0x00000000);
    checkDefVal(CfgTxMemMgrCPUReadAddress, 0x00000000);
    checkDefVal(CfgTxMemMgrCPUCommitPointer, 0x00000000);
    checkDefVal(CfgTxMemMgrCPUWriteData_0, 0x00000000);
    checkDefVal(CfgTxMemMgrCPUWriteData_1, 0x00000000);
    checkDefVal(CfgTxMemMgrCPUWriteData_2, 0x00000000);
    checkDefVal(CfgTxMemMgrCPUWriteData_3, 0x00000000);
    checkDefVal(CfgTxMemMgrCPUWriteData_4, 0x00000000);
    checkDefVal(CfgTxMemMgrBypassFcsChk, 0x00000000);
    return OK;
}

/*
 * portinterface_defChk - Checks the Transmit Port Slave registers for the default values
 */
int portinterface_defChk (void) {
    checkDefVal(CfgTxPCSBitOrder, 0x00000000);
    checkDefVal(CfgTxPCSLoadX58, 0x00000000);
    checkDefVal(CfgTxPCSSeedX58_3, 0x00000000);
    checkDefVal(CfgTxPCSSeedX58_2, 0x00000000);
    checkDefVal(CfgTxPCSSeedX58_1, 0x00000000);
    checkDefVal(CfgTxPCSSeedX58_0, 0x00000000);
    checkDefVal(CfgTxXFIAlign, 0x00000000);
    checkDefVal(CfgTxXFIAlignChar_3, 0x00000707);
    checkDefVal(CfgTxXFIAlignChar_2, 0x00000707);
    checkDefVal(CfgTxXFIAlignChar_1, 0x00000707);
    checkDefVal(CfgTxXFIAlignChar_0, 0x00000707);
    checkDefVal(CfgRxPCSBitOrder, 0x00000000);
    checkDefVal(CfgRxPcsBerTimerVal, 0x00004eac);
    checkDefVal(CfgRxPcsRXGFifoFullThr, 0x00000008);
    checkDefVal(CfgRxXFIAlign, 0x00000000);
    checkDefVal(CfgRxXFIAlignChar_3, 0x00000707);
    checkDefVal(CfgRxXFIAlignChar_2, 0x00000707);
    checkDefVal(CfgRxXFIAlignChar_1, 0x00000707);
    checkDefVal(CfgRxXFIAlignChar_0, 0x00000707);
    checkDefVal(CfgRxPCSLoadX58, 0x00000000);
    checkDefVal(CfgRxPCSSeedX58_3, 0x00000000);
    checkDefVal(CfgRxPCSSeedX58_2, 0x00000000);
    checkDefVal(CfgRxPCSSeedX58_1, 0x00000000);
    checkDefVal(CfgRxPCSSeedX58_0, 0x00000000);
    checkDefVal(CfgXFIDataBitOrder, 0x00000000);
    checkDefVal(CfgConsiderRemoteFault, 0x00000003);
    checkDefVal(CfgRTLChanges, 0x0000003f);
    return OK;
}

/*
 * txpspiprical_defChk - Checks the Transmit Primary SPI Slave registers for the default values
 */
int txpspiprical_defChk (void) {
    checkDefVal(CfgMemTSpiCal, 0x00000000);
    return OK;
}

/*
 * txpspishdwcal_defChk - Checks the Transmit Primary SPI Slave registers for the default values
 */
int txpspishdwcal_defChk (void) {
    checkDefVal(CfgMemTxpSpiCalShadow, 0x00000000);
    return OK;
}

/*
 * txpspi_defChk - Checks the Transmit Primary SPI Slave registers for the default values
 */
int txpspi_defChk (void) {
    checkDefVal(CfgRegTSpiSetup, 0x00000400);
    checkDefVal(CfgRegTSpiFifoId0, 0x00000000);
    checkDefVal(CfgRegTSpiFifoId1, 0x00000001);
    checkDefVal(CfgRegTSpiFifoId2, 0x00000002);
    checkDefVal(CfgRegTSpiFunnelFifoId0, 0x00000000);
    checkDefVal(CfgRegTSpiFunnelFifoId1, 0x00000001);
    checkDefVal(CfgRegTSpiFunnelFifoId2, 0x00000002);
    checkDefVal(CfgRegTSpiFunnelDefaultFifoId, 0x00000000);
    checkDefVal(CfgRegTSpiDipWindow, 0x00000100);
    checkDefVal(CfgRegTSpiDipErrThr, 0x00000001);
    checkDefVal(VarRegTxPSpiDPGEnable, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPGMode, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPGCRCValue, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPGPacketFixed, 0x00000040);
    checkDefVal(CfgRegTxPSpiDPGPacketNumber, 0x0000000a);
    checkDefVal(CfgRegTxPSpiDPGGap, 0x00000010);
    checkDefVal(CfgRegTxPSpiDPGPatternFixed, 0x0000aaaa);
    checkDefVal(CfgRegTxPSpiPrbsSeed, 0x007fffff);
    checkDefVal(CfgRegTxPSpiDPGSrcL, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPGSrcH, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPGDestL, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPGDestH, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPGVLanTag, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPGPreambleL, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPGPreambleH, 0x00000000);
    checkDefVal(VarRegTxPSpiDPVEnable, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPVMode, 0x00000000);
    checkDefVal(CfgRegTxPSpiDPVHdrCtrl, 0x00000000);
    checkDefVal(CfgRegTxPSpiCRRLoopBWReg0, 0x00000000);
    checkDefVal(CfgRegTxPSpiCRRLoopBWReg1, 0x00000000);
    checkDefVal(CfgRegTxPSpiHMMisc, 0x00000000);
    checkDefVal(CfgRegTxPSPIHMPhaseShift, 0x00000000);
    checkDefVal(CfgRegTSpiThr, 0xa0a5840c);
    checkDefVal(CfgRegEnXAUIFlowCtrl, 0x0000000f);
    return OK;
}

/*
 * txpspistat_defChk - Checks the Transmit Primary SPI Slave registers for the default values
 */
int txpspistat_defChk (void) {
    checkDefVal(CfgRegTSpiCalSetup, 0x00000000);
    checkDefVal(CfgRegTSpiStatusMode, 0x00000000);
    return OK;
}

/*
 * txsspimtuaccess_defChk - Checks the Transmit Secondary SPI Slave registers for the default values
 */
int txsspimtuaccess_defChk (void) {
    checkDefVal(CfgMiscFullPacketMode0, 0x00000000);
    checkDefVal(CfgMiscTailDropEn0, 0x00000000);
    checkDefVal(CfgMiscDisableEcc0, 0x00000000);
    checkDefVal(CfgMiscDisableRead0, 0x00000000);
    checkDefVal(CfgMiscReadOnThreshold0, 0x00000001);
    checkDefVal(CfgMiscReadOffThreshold0, 0x00000000);
    checkDefVal(CfgMiscReadTimerValue0, 0x00000064);
    checkDefVal(CfgMiscCPUAccess0, 0x00000000);
    checkDefVal(CfgMiscCPUWriteAddress0, 0x00000000);
    checkDefVal(CfgMiscCPUReadAddress0, 0x00000000);
    checkDefVal(CfgMiscCPUCommitPointer0, 0x00000000);
    checkDefVal(CfgMiscCPUWriteData0, 0x00000000);
    checkDefVal(CfgMiscDisableEcc1, 0x00000000);
    checkDefVal(CfgMiscDisableRead1, 0x00000000);
    checkDefVal(CfgMiscFullPacketMode1, 0x00000000);
    checkDefVal(CfgMiscTailDropEn1, 0x00000000);
    checkDefVal(CfgMiscReadOnThreshold1, 0x00000001);
    checkDefVal(CfgMiscReadOffThreshold1, 0x00000000);
    checkDefVal(CfgMiscReadTimerValue1, 0x00000064);
    checkDefVal(CfgMiscCPUAccess1, 0x00000000);
    checkDefVal(CfgMiscCPUWriteAddress1, 0x00000000);
    checkDefVal(CfgMiscCPUReadAddress1, 0x00000000);
    checkDefVal(CfgMiscCPUCommitPointer1, 0x00000000);
    checkDefVal(CfgMiscCPUWriteData1, 0x00000000);
    return OK;
}

/*
 * txsspiprical_defChk - Checks the Transmit Secondary SPI Slave registers for the default values
 */
int txsspiprical_defChk (void) {
    checkDefVal(CfgMemTxSSpiCal, 0x00000000);
    return OK;
}

/*
 * txsspishdwcal_defChk - Checks the Transmit Secondary SPI Slave registers for the default values
 */
int txsspishdwcal_defChk (void) {
    checkDefVal(CfgMemTxsSpiCalShadow, 0x00000000);
    return OK;
}

/*
 * txsspi_defChk - Checks the Transmit Secondary SPI Slave registers for the default values
 */
int txsspi_defChk (void) {
    checkDefVal(CfgRegTxSSpiSetup, 0x00000200);
    checkDefVal(CfgRegTxSSpiFifoId0, 0x00000000);
    checkDefVal(CfgRegTxSSpiFifoId1, 0x00000001);
    checkDefVal(CfgRegTxSSpiFifoId2, 0x00000002);
    checkDefVal(CfgRegTxSSpiFunnelFifoId0, 0x00000000);
    checkDefVal(CfgRegTxSSpiFunnelFifoId1, 0x00000001);
    checkDefVal(CfgRegTxSSpiFunnelFifoId2, 0x00000002);
    checkDefVal(CfgRegTxSSpiFunnelDefaultFifoId, 0x00000000);
    checkDefVal(CfgRegTxSSpiDipWindow, 0x00000100);
    checkDefVal(CfgRegTxSSpiDipErrThr, 0x00000001);
    checkDefVal(CfgRegTxSSpiCRRLoopBWReg0, 0x00000000);
    checkDefVal(CfgRegTxSSpiCRRLoopBWReg1, 0x00000000);
    checkDefVal(CfgRegTxSSpiHMMisc, 0x00000000);
    checkDefVal(CfgRegTxSSPIHMPhaseShift, 0x00000000);
    checkDefVal(VarRegTxSSpiDPGEnable, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPGMode, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPGCRCValue, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPGPacketFixed, 0x00000040);
    checkDefVal(CfgRegTxSSpiDPGPacketNumber, 0x0000000a);
    checkDefVal(CfgRegTxSSpiDPGGap, 0x00000010);
    checkDefVal(CfgRegTxSSpiDPGPatternFixed, 0x0000aaaa);
    checkDefVal(CfgRegTxSSpiPrbsSeed, 0x007fffff);
    checkDefVal(CfgRegTxSSpiDPGSrcL, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPGSrcH, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPGDestL, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPGDestH, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPGVLanTag, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPGPreambleL, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPGPreambleH, 0x00000000);
    checkDefVal(VarRegTxSSpiDPVEnable, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPVMode, 0x00000000);
    checkDefVal(CfgRegTxSSpiDPVHdrCtrl, 0x00000000);
    checkDefVal(CfgRegTxSSpiThr, 0x424fa40c);
    checkDefVal(CfgRegTxSSpiMemMgrThr, 0x000af28a);
    return OK;
}

/*
 * txsspistat_defChk - Checks the Transmit Secondary SPI Slave registers for the default values
 */
int txsspistat_defChk (void) {
    checkDefVal(CfgRegTxSSpiCalSetup, 0x00000000);
    checkDefVal(CfgRegTxSSpiStatusMode, 0x00000000);
    return OK;
}

/*
 * txvlanctrl_defChk - Checks the Transmit VLAN Control Slave registers for the default values
 */
int txvlanctrl_defChk (void) {
    checkDefVal(CfgTxVlanCtrlEtherTypeReg0, 0x810088a8);
    checkDefVal(CfgTxVlanCtrlEtherTypeReg1, 0x82009100);
    checkDefVal(CfgTxVlanCtrlEtherTypeReg2, 0x00000000);
    checkDefVal(CfgTxVlanCtrlEtherTypeReg3, 0x00000000);
    checkDefVal(CfgTxVlanCtrlEtherTypeReg4, 0x00000000);
    checkDefVal(CfgTxVlanCtrlEtherTypeReg5, 0x00000000);
    checkDefVal(CfgTxVlanCtrlEtherTypeReg6, 0x00000000);
    checkDefVal(CfgTxVlanCtrlEtherTypeReg7, 0x00000000);
    checkDefVal(CfgMplsTypeReg, 0x88478848);
    checkDefVal(CfgMplsStyle, 0x00000000);
    checkDefVal(CfgDefaultVlanCtrlTblReg0, 0x0000000e);
    checkDefVal(CfgDefaultVlanCtrlTblReg1, 0x81000000);
    checkDefVal(CfgWr4096x12TxVlanCtrlTblRam, 0x00000000);
    checkDefVal(CfgByPassEccCheckfortxvlan4kram, 0x00000000);
    checkDefVal(CfgInsertVplsForConflict, 0x00000001);
    checkDefVal(CfgDisableMplsEncoding, 0x00000000);
    checkDefVal(CfgRd4096x12TxVlanCtrlTblRam, 0x00000000);
    checkDefVal(CfgWr256x32TxVlanTagRamReg0, 0x00000000);
    checkDefVal(CfgWr256x32TxVlanTagRamReg1, 0x81000000);
    checkDefVal(CfgRd256x32TxVlanTagRamReg, 0x00000000);
    checkDefVal(CfgTxVlanDontStripOffEfh, 0x00000000);
    checkDefVal(CfgByPassFcsErrChk, 0x00000000);
    checkDefVal(CfgDisableEfh, 0x00000000);
    return OK;
}

/*
 * txxauixmac_defChk - Checks the Transmit XAUI XMAC Slave registers for the default values
 */
int txxauixmac_defChk (void) {
    checkDefVal(CfgTxXauiXmacModes, 0x00000006);
    checkDefVal(CfgRegTxRSModes, 0x00000000);
    checkDefVal(CfgTxXauiDebugEopCharacter, 0x000001fe);
    checkDefVal(CfgTxXauiProgIPGCount, 0x00000000);
    checkDefVal(CfgTxXauiRegTxRSFaultTrafficBP, 0x00000001);
    checkDefVal(CfgTxXauiRegTxRSLocalFaultEn, 0x00000001);
    checkDefVal(CfgTxXauiRegTxRSLocalFaultMode, 0x00000002);
    checkDefVal(CfgTxXauiRegTxRSRemoteFaultEn, 0x00000001);
    checkDefVal(CfgTxXauiRegTxRSLinkFaultRecoveryMode, 0x00000001);
    checkDefVal(CfgTxXauiRegTxRSCPUFaultRecovery, 0x00000000);
    checkDefVal(CfgDontAddPreAmble, 0x00000000);
    return OK;
}

/******************************************************************
* rhAsicTestDefault - Run RedHawk ASIC register default value test
*
* This is diagnostic test routine to verify RedHawk ASIC registers. The test
* performs soft reset of RedHawk ASIC device, reads set of registers and
* compare registers against their default value.
*
* The register values are not saved and restored by the test and current
* operation/ configuration of RedHawk ASIC is disrupted by the test.
*
* RETURNS: None
*/
int rhAsicTestDefault (void) {
    /* Soft Reset */
    regSet(redHawkRegs, VarRegCoGlobalSoftReset, 0, 1);

    /* Initializing the check_default_flag variable */
    check_default_flag = OK;

    /* Calling the default check routine for Common slave registers */
    common_defChk ();

    /* XFI module; Needs some initialization */
    regSet(redHawkRegs, CfgRegCoFCPLLConfig__FC_PLL_LockResetN, 0, 1);
    regSet(redHawkRegs, CfgRegCoMisc__VarCpuSlaveEn, 0, 1);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP0, 0, 1);
    regSet(redHawkRegs, CfgRxControl, 0, 0x40077234);
    regSet(redHawkRegs, CfgTxControl, 0, 0x4c047234);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP0, 0, 1);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP0, 0, 1);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP0, 0, 1);
    regSet(redHawkRegs, CfgRxControl, 0, 0x400712b0);
    regSet(redHawkRegs, CfgTxControl, 0, 0x4c0012b0);
    regSet(redHawkRegs, CfgStatusControl, 0, 0x20000090);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP1, 0, 1);
    regSet(redHawkRegs, CfgRxControl, 1, 0x40077234);
    regSet(redHawkRegs, CfgTxControl, 1, 0x4c047234);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP1, 0, 1);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP1, 0, 1);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP1, 0, 1);
    regSet(redHawkRegs, CfgRxControl, 1, 0x400712b0);
    regSet(redHawkRegs, CfgTxControl, 1, 0x4c0012b0);
    regSet(redHawkRegs, CfgStatusControl, 1, 0x20000090);
    portinterface_defChk ();

    /* XAUI modules; Needs some initialization */
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP0, 0, 0);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP0, 0, 0);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP0, 0, 0);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP0, 0, 0);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP1, 0, 0);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP1, 0, 0);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP1, 0, 0);
    regSet(redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP1, 0, 0);
    regSet(redHawkRegs, CfgRegCoLineInterfaceMode__XAUIInterfaceP0, 0, 1);
    regSet(redHawkRegs, CfgRegCoClkSelect__XGClkSelectP0, 0, 0);
    regSet(redHawkRegs, CfgRegCoMisc__VarXAUICoreEn0, 0, 1);
    regSet(redHawkRegs, CfgRegCoLineInterfaceMode__XAUIInterfaceP1, 0, 1);
    regSet(redHawkRegs, CfgRegCoClkSelect__XGClkSelectP1, 0, 0);
    regSet(redHawkRegs, CfgRegCoMisc__VarXAUICoreEn1, 0, 1);
    rxxauixmac_defChk ();
    txxauixmac_defChk ();

    /* Calling default check routines for all individual blocks */
    dequeuer_defChk ();
    dualmemctl_defChk ();
    enqueuer_defChk ();
    led_defChk ();
    mdio_defChk ();
    queuemanager_defChk ();
    rxdropcontrol_defChk ();
    rxdropcontrolstat_defChk ();
    rxdropcontrolwred_defChk ();
    rxlinetocpu_defChk ();
    rxmac_defChk ();
    rxpspiprical_defChk ();
    rxpspishdwcal_defChk ();
    rxpspi_defChk ();
    rxpspistat_defChk ();
    rxsspiprical_defChk ();
    rxsspishdwcal_defChk ();
    rxsspi_defChk ();
    rxsspistat_defChk ();
    shadowregs_defChk ();
    txcputoline_defChk ();
    txmaccfg_defChk ();
    txmemcommon_defChk ();
    txmemmanager_defChk ();
    txpspiprical_defChk ();
    txpspishdwcal_defChk ();
    txpspi_defChk ();
    txpspistat_defChk ();
    txsspimtuaccess_defChk ();
    txsspiprical_defChk ();
    txsspishdwcal_defChk ();
    txsspi_defChk ();
    txsspistat_defChk ();
    txvlanctrl_defChk ();

    regSet(redHawkRegs, VarRegCoGlobalSoftReset, 0, 1);

    return (check_default_flag);
}

/*
 * Read the specified register
 * Compare the value read with the defVal passed to this function
 * Print an error message if there is a mismatch
 */
void checkDefVal(int regId, unsigned int defVal)
{
    int numInst, i;
    reginfo_t *regdb;
    unsigned int regVal, regAddr;

    /* Get the redHawk register database */
    regdb = redHawkRegs;

    /* Get the number of instances */
    numInst = regdb[regId].instMax;

    /* Check for all instances */
    for (i=0; i<numInst; i++) {
        regVal = 0;
        regGet(regdb, regId, i, &regVal);
        regAddr = regdb[regId].addr + (i * regdb[regId].instOffset);

        if (regVal != defVal) {
            osPrintf("(0x%.4x) %32s : EXPECTED 0x%.8x, RECEIVED 0x%.8x ---- MISMATCH\n", regAddr, regdb[regId].name, defVal, regVal);
            check_default_flag = ERROR;
        }
    }
}

/*
 * This routine has to be completed by the User. The function in
 * breif starts a thread that calls the rhXfiRfGen with required
 * arguments.
 */
void osThreadCreateXFI0 (
    reginfo_t *regdb,
    int port
    )
{
    REGDB_PORT regdb_info;
    regdb_info.regdb = (reginfo_t *)regdb;
    regdb_info.portNumber = port;

    /*
     * Function that creates a thread and passes the regdb_info
     * structure to the rhXfiRfGen routine
     */
}

void osThreadCreateXFI1 (
    reginfo_t *regdb,
    int port
    )
{
    REGDB_PORT regdb_info;
    regdb_info.regdb = (reginfo_t *)regdb;
    regdb_info.portNumber = port;

    /*
     * Function that creates a thread and passes the regdb_info
     * structure to the rhXfiRfGen routine
     */
}

/*
 * This function implements the polling for XFI interfaces to
 * reconfigure them when the cable is unplugged/plugged.
 *
 * When the cable is unplugged the local link fault interrupt
 * is generated. The register StsRegCoXFIIO is checked for bits
 * 0 and 3 for port0 and bits 4 and 7 for port1 to be cleared.
 * The bits are cleared once the cable is plugged back, then
 * xfi port will be reconfigured.
 *
 * else
 *
 * If the user choses to use XAUI ports or the XFI port will not
 * be used, then the thread will be exited.
 * The function reads CfgRegCoLineInterfaceMode. If the bit 0 or
 * 4 is cleared, which means the XFI ports will no longer
 * be used, exit the thread.
 *
 */
int rhXfiRfGen(void *param)
{
    unsigned int regVal;
    unsigned int lineIfMode;
    unsigned int portNumber;
    reginfo_t * regDb;
    int i;

    REGDB_PORT *regdb_port = (REGDB_PORT *)param;
    portNumber = regdb_port->portNumber;
    regDb = regdb_port->regdb;

    while(1) {
        regVal=0;

        regGet(regDb, CfgRegCoLineInterfaceMode, 0, &lineIfMode);
        regSet(regDb, CfgRegCoClockDiv0__MDIOClk, 0, 0xe);

        if (portNumber == 0) {
            osPrintf ("Port 0 ISR Started\n");
            if((lineIfMode & 0x1) == 0) {
                osPrintf ("ERROR!!! Exiting the port 0 ISR; Configured for XAUI mode\n");
                break;
            }
            /* Configuring the MDIO for accessing the internal XFI core */
            regSet(regDb, CfgRegCoMDIOMode, 0, BIT_6);
            regVal = 0;
            for (i=0; i<3; i++) {
                /* Check for PCS Link Status */
                rhAsicMdioRead(portNumber, 32, 3, &regVal);
                osDelay (1000);
            }
            if (regVal & BIT_12) {/* Link UP condition */
                regSet (regDb, CfgRegTxMACModes__TxLocalFaultInsertEn, portNumber, 0);
                osPrintf ("Exiting the Port 0 ISR; Link is UP for Port 0, so does not require any re-configuration\n");
                break;
            }

            /* Check for Rx LOS up */
            regSet (regDb, CfgRegTxMACModes__TxLocalFaultInsertEn, portNumber, 1);

            /* Wait until Rx LOS is down */
            osPrintf ("Checking for LOS on Port 0\n");
            while (1) {
                regGet (regDb, StsRegCoXFIIO, 0, &regVal);
                if (!(regVal & BIT_3))
                    break;
                osDelay(10);
            }
            osPrintf ("LOS is down for port 0\n");

            /* Configure the Rx XFI */
            osPrintf ("Calling re-config rouitne for port0\n");
            rh_rxxfi_reconfig (regDb, portNumber);
            osPrintf ("Done with the re-config rouitne for port0\n");

            regVal = 0;
            for (i=0; i<3; i++) {
                /* Check for PCS Link Status */
                rhAsicMdioRead(portNumber, 32, 3, &regVal);
                osDelay (1000);
            }

            if (regVal & BIT_12) { /* Link UP condition */
                regSet (regDb, CfgRegTxMACModes__TxLocalFaultInsertEn, portNumber, 0);
                osPrintf ("XFI Link Up for Port 0; Exiting the Thread normally\n");
            } else {
                osPrintf ("ERROR!!! XFI Link not UP for port %d after RxXFI-ReInit. Exiting the Thread\n", portNumber);
            }

            break;
        } else if (portNumber == 1) {
            osPrintf ("Port 1 ISR Started\n");
            if((lineIfMode & 0x4) == 0) {
                osPrintf ("ERROR!!! Exiting the port 1 ISR; Configured for XAUI mode\n");
                break;
            }

            /* Configuring the MDIO for accessing the internal XFI core */
            regSet(regDb, CfgRegCoMDIOMode, 0, BIT_7);
            regVal = 0;
            for (i=0; i<3; i++) {
                /* Check for PCS Link Status */
                rhAsicMdioRead(portNumber, 32, 3, &regVal);
                osDelay (1000);
            }
            if (regVal & BIT_12) {/* Link UP condition */
                regSet (regDb, CfgRegTxMACModes__TxLocalFaultInsertEn, portNumber, 0);
                osPrintf ("Exiting the Port 1 ISR; Link is UP for Port 1, so does not require any re-configuration\n");
                break;
            }

            /* Check for Rx LOS up */
            regSet (regDb, CfgRegTxMACModes__TxLocalFaultInsertEn, portNumber, 1);

            /* Wait until Rx LOS is down */
            osPrintf ("Checking for LOS on Port 1\n");
            while (1) {
                regGet (regDb, StsRegCoXFIIO, 0, &regVal);
                if (!(regVal & BIT_7))
                    break;
                osDelay(10);
            }
            osPrintf ("LOS is down for port 1\n");

            /* Configure the Rx XFI */
            osPrintf ("Calling re-config routine on port1\n");
            rh_rxxfi_reconfig (regDb, portNumber);
            osPrintf ("Done with the re-config rouitne for port1\n");

            regVal = 0;
            for (i=0; i<3; i++) {
                /* Check for PCS Link Status */
                rhAsicMdioRead(portNumber, 32, 3, &regVal);
                osDelay (1000);
            }

            if (regVal & BIT_12) { /* Link UP condition */
                regSet (regDb, CfgRegTxMACModes__TxLocalFaultInsertEn, 1, 0);
                osPrintf ("XFI Link Up for Port 1; Exiting the Thread normally\n");
            } else {
                osPrintf ("ERROR!!! XFI Link not UP for port %d after RxXFI-ReInit, Exiting the Thread\n", portNumber);
            }

            break;
        }
    }


    /* Unmask the Sync Status Changed Interrupt */
    if (portNumber == 0)
        syncStatusChangedThreadP0 = 0;
    else
        syncStatusChangedThreadP1 = 0;

    return 0;
}

/******************************************************************
 *
 * RedHawk ASIC Interrupt Handler Functions
 *
 ******************************************************************/

/* statistics variables */
struct rhAsicInterrupts_ rhAsicInterrupts;

/* Routine which handles the Common Interrupt */
/* Checks for the interrupt type and calls the concerned routine */
/* Clears the interrupt by reading it */
void rhAsicCommonIntr(reginfo_t *regdb)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.commonInt.total++;

    /* Read the CoClkInterrupt register and check for the interrupts */
    regVal = 0;
    regGet(regdb, StsRegCoClkMonInterrupt, 0, &regVal);

    if (regVal & COCLKMON_SPIRSCLK1){
        osPrintf("Primary SPI Rs Clock Activity Status changed\n");
        rhAsicInterrupts.commonInt.SpiRsClk1++;
    }

    if (regVal & COCLKMON_SPIRSCLK0) {
        osPrintf("Secondary SPI Rs Clock Activity Status changed\n");
        rhAsicInterrupts.commonInt.SpiRsClk0++;
    }

    if (regVal & COCLKMON_RXXFI66CLK1) {
        osPrintf("Rx XFI 66 Clock Activity Status changed for port 1\n");
        rhAsicInterrupts.commonInt.RxXfi66Clk1++;
    }

    if (regVal & COCLKMON_RXXFI66CLK0) {
        osPrintf("Rx XFI 66 Clock Activity Status changed for port 0\n");
        rhAsicInterrupts.commonInt.RxXfi66Clk0++;
    }

    if (regVal & COCLKMON_TXXFI66CLK1) {
        osPrintf("Tx XFI 66 Clock Activity Status changed for port 1\n");
        rhAsicInterrupts.commonInt.TxXfi66Clk1++;
    }

    if (regVal & COCLKMON_TXXFI66CLK0) {
        osPrintf("Tx XFI 66 Clock Activity Status changed for port 0\n");
        rhAsicInterrupts.commonInt.TxXfi66Clk0++;
    }

    if (regVal & COCLKMON_RXXFI64CLK1) {
        osPrintf("Rx XFI 64 Clock Activity Status changed for port 1\n");
        rhAsicInterrupts.commonInt.RxXfi64Clk1++;
    }

    if (regVal & COCLKMON_RXXFI64CLK0) {
        osPrintf("Rx XFI 64 Clock Activity Status changed for port 0\n");
        rhAsicInterrupts.commonInt.RxXfi64Clk1++;
    }

    if (regVal & COCLKMON_TXXFI64CLK1) {
        osPrintf("Tx XFI 64 Clock Activity Status changed for port 1\n");
        rhAsicInterrupts.commonInt.TxXfi64Clk1++;
    }

    if (regVal & COCLKMON_TXXFI64CLK0) {
        osPrintf("Tx XFI 64 Clock Activity Status changed for port 0\n");
        rhAsicInterrupts.commonInt.TxXfi64Clk0++;
    }

    if (regVal & COCLKMON_SPIRDCLK1) {
        osPrintf("Primary SPI RD Clock Activity Status changed\n");
        rhAsicInterrupts.commonInt.SpiRdClk1++;
    }

    if (regVal & COCLKMON_SPIRDCLK0) {
        osPrintf("Secondary SPI RD Clock Activity Status changed\n");
        rhAsicInterrupts.commonInt.SpiRdClk0++;
    }

    if (regVal & COCLKMON_XAUICLK1) {
        osPrintf("XAUI Clock Activity Status changed for port 1\n");
        rhAsicInterrupts.commonInt.XauiClk1++;
    }

    if (regVal & COCLKMON_XAUICLK0) {
        osPrintf("XAUI Clock Activity Status changed for port 0\n");
        rhAsicInterrupts.commonInt.XauiClk0++;
    }

    if (regVal & COCLKMON_SYSCLK) {
        osPrintf("System Clock Activity Status changed\n");
        rhAsicInterrupts.commonInt.SysClk++;
    }

    /* Looking for XAUI Byte Sync Interrupt */
    regGet(regdb, StsRegCoXAUIInterrupt, 0, &regVal);
    if (regVal & COXAUI_BYTESYNC_P1) {
        osPrintf("PORT 1 XAUI Byte Sync Status changed\n");
        rhAsicInterrupts.commonInt.xauiByteSyncStatusChangeP1++;
    }

    if (regVal & COXAUI_BYTESYNC_P0) {
        osPrintf("PORT 0 XAUI Byte Sync Status changed\n");
        rhAsicInterrupts.commonInt.xauiByteSyncStatusChangeP0++;
    }

    /* Looking for XFI Interrupt */
    regGet(regdb, StsRegCoXFIInterrupt, 0, &regVal);
    if (regVal & COXFI_INTR_P1) {
        osPrintf("XFI_INTR input for PORT 1 is set to 1\n");
        rhAsicInterrupts.commonInt.xfiintr1++;
    }

    if (regVal & COXFI_INTR_P0) {
        osPrintf("XFI_INTR input for PORT 0 is set to 1\n");
        rhAsicInterrupts.commonInt.xfiintr0++;
    }

    /* Looking for the 2 Wire Interface Interrupt */
    regVal = 0;
    regGet(regdb,StsRegCo2wiremasterInterrupt, 0, &regVal);

    if (regVal & WIREMASTER_INTR_P1) {
        osPrintf("XFI Port 1 Interrupt\n");
        rhAsicInterrupts.commonInt.wiremaster1++;
    }

    if (regVal & WIREMASTER_INTR_P0) {
        osPrintf("XFI Port 0 Interrupt\n");
        rhAsicInterrupts.commonInt.wiremaster0++;
    }
}

void rhAsicRxMacIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.rxMac[port].total++;

    /* Read the RX MAC Interrupt register and Check for the interrupts */
    regGet(regdb, StsRegRxMACInterrupt, port, &regVal);
    if (regVal & RXMAC_VLDPAUSEFRM) {
        osPrintf("RXMAC: Valid PAUSE Frame recieved\n");
        rhAsicInterrupts.rxMac[port].vldPauseFrmRcvd++;
    }

    if (regVal & RXMAC_PREAMBLEMISMATCH) {
        osPrintf("RXMAC: Reserved Interrupt\n");
        rhAsicInterrupts.rxMac[port].preambleMismatch++;
    }

    if (regVal & RXMAC_FIFODRYTIMEOUT) {
        osPrintf("RXMAC: Reserved Interrupt\n");
        rhAsicInterrupts.rxMac[port].fifoDryTimeOut++;
    }

    if (regVal & RXMAC_FIFOFULL) {
        osPrintf("RXMAC: FIFO Full; Receiving back pressure\n");
        rhAsicInterrupts.rxMac[port].fifoFull++;
    }

    if (regVal & RXMAC_CPUFRAME) {
        osPrintf("RXMAC: Reserved Interrupt\n");
        rhAsicInterrupts.rxMac[port].cpuFrame++;
    }

    if (regVal & RXMAC_REMOTELINKFAULTSTATUS) {
        osPrintf("RXMAC: Remote Fault detected\n");
        rhAsicInterrupts.rxMac[port].remoteLinkFaultStatus++;
    }

    if (regVal & RXMAC_LOCALLINKFAULTSTATUS) {
        osPrintf("RXMAC: Local Fault detected\n");
        rhAsicInterrupts.rxMac[port].localLinkFaultStatus++;
    }
}

void rhAsicTxMacIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.txMac[port].total++;

    regGet(regdb, StsRegTxMACInterrupt, port, &regVal);
    if (regVal & TXMAC_PAUSEFRMSENT) {
        osPrintf("TXMAC: Generated the requested PAUSE Frame\n");
        rhAsicInterrupts.txMac[port].pauseFrmSent++;
    }

    if (regVal & TXMAC_FIFOFULLTIMEOUT) {
        osPrintf("TXMAC: Reserved Interrupt\n");
        rhAsicInterrupts.txMac[port].fifoFullTimeOut++;
    }

    if (regVal & TXMAC_FIFODRY) {
        osPrintf("TXMAC: Reserved Interrupt\n");
        rhAsicInterrupts.txMac[port].fifoDry++;
    }

    if (regVal & TXMAC_CRCERROR) {
        osPrintf("TXMAC: Received a frame with incorrect CRC\n");
        rhAsicInterrupts.txMac[port].crcErr++;
    }
}

void rhAsicRxSpiIntr(reginfo_t *regdb, int rxpSpiInt)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.rxSpi.total++;

    /* Check for the RxpSpiInt */
    if(rxpSpiInt == 1) {
        regVal = 0;

        regGet(regdb, StsRegRxpSpiInterrupt, 0, &regVal);

        if (regVal) {
            osPrintf("RXPSPI: LOS\n");
            rhAsicInterrupts.rxSpi.rxpSpi++;
        }
    } else {
        regVal = 0;

        regGet(regdb, StsRegRxsSpiInterrupt, 0, &regVal);

        if (regVal) {
            osPrintf("RXSSPI: LOS\n");
            rhAsicInterrupts.rxSpi.rxsSpi++;
        }
    }
}

void rhAsicDatabaseMgrIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.databaseMgr[port].total++;

    regVal = 0;
    regGet(regdb, StsTotalRsvdPageCountInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("Queue Mgr: CfgTotalRcvdPageCnt value set to value greater than the pages available\n");
        rhAsicInterrupts.databaseMgr[port].totalRsvdPageCount++;
    }

    regVal = 0;
    regGet(regdb, StsPageFifoOverflowInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("Queue Mgr: Page FIFO Full\n");
        rhAsicInterrupts.databaseMgr[port].pageFifoOverflow++;
    }

    regVal = 0;
    regGet(regdb, StsQmFptEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("Queue Mgr: Free Page Table Pointer has an ECC error\n");
        rhAsicInterrupts.databaseMgr[port].qmFptEccErr++;
    }

    regVal = 0;
    regGet(regdb, StsQmFptEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("Queue Mgr: Free Page Table Pointer has a single correctable ECC error\n");
        rhAsicInterrupts.databaseMgr[port].qmFptEccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsQmFptEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("Queue Mgr: Free Page Table Pointer has a double uncorrectable ECC error\n");
        rhAsicInterrupts.databaseMgr[port].qmFptEccDoubleErr++;
    }

    regVal = 0;
    regGet(regdb, StsQmPltEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("Queue Mgr: Page Link Table Pointer has an ECC error\n");
        rhAsicInterrupts.databaseMgr[port].qmPltEccErr++;
    }

    regVal = 0;
    regGet(regdb, StsQmPltEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("Queue Mgr: Page Link Table Pointer has a Single correctable ECC error\n");
        rhAsicInterrupts.databaseMgr[port].qmPltEccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsQmPltEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("Queue Mgr: Page Link Table Pointer has a Double uncorrectable ECC error\n");
        rhAsicInterrupts.databaseMgr[port].qmPltEccDoubleErr++;
    }
}

void rhAsicExtMemIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.extMem[port].total++;

    regVal = 0;
    regGet(regdb, StsMemAccessInterrupt, port, &regVal);
    if (regVal & EXTMEM_FCRAMINTR) {
        osPrintf("FCRAM: Status interrupt for PLL lock\n");
        rhAsicInterrupts.extMem[port].initFcram++;
    }

    if (regVal & EXTMEM_READINTR) {
        osPrintf("FCRAM: CPU Read performed\n");
        rhAsicInterrupts.extMem[port].read++;
    }

    if (regVal & EXTMEM_WRITEINTR) {
        osPrintf("FCRAM: CPU Write to FCRAM performed\n");
        rhAsicInterrupts.extMem[port].write++;
    }
}

void rhAsicRxDeqIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.rxDeq[port].total++;

    regVal = 0;
    regGet(regdb, StsDeqQnumFifoOverflowInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: QNum Fifo in the dequeuer is full\n");
        rhAsicInterrupts.rxDeq[port].qnumFifoOverflow++;
    }

    regVal = 0;
    regGet(regdb, StsDeqDataFifoOverflowInterrupt0, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: Data FIFO for Q0 is full\n");
        rhAsicInterrupts.rxDeq[port].dataFifoOverflow0++;
    }

    regVal = 0;
    regGet(regdb, StsDeqDataFifoOverflowInterrupt1, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: Data FIFO for Q1 is full\n");
        rhAsicInterrupts.rxDeq[port].dataFifoOverflow1++;
    }

    regVal = 0;
    regGet(regdb, StsDeqDataFifoOverflowInterrupt2, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: Data FIFO for Q2 is full\n");
        rhAsicInterrupts.rxDeq[port].dataFifoOverflow2++;
    }

    regVal = 0;
    regGet(regdb, StsDeqDataFifoOverflowInterrupt3, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: Data FIFO for Q3 is full\n");
        rhAsicInterrupts.rxDeq[port].dataFifoOverflow3++;
    }

    regVal = 0;
    regGet(regdb, StsDeqDataFifoOverflowInterrupt4, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: Data FIFO for Q4 is full\n");
        rhAsicInterrupts.rxDeq[port].dataFifoOverflow4++;
    }

    regVal = 0;
    regGet(regdb, StsDeqDataFifoOverflowInterrupt5, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: Data FIFO for Q5 is full\n");
        rhAsicInterrupts.rxDeq[port].dataFifoOverflow5++;
    }

    regVal = 0;
    regGet(regdb, StsDeqDataFifoOverflowInterrupt6, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: Data FIFO for Q6 is full\n");
        rhAsicInterrupts.rxDeq[port].dataFifoOverflow6++;
    }

    regVal = 0;
    regGet(regdb, StsDeqDataFifoOverflowInterrupt7, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: Data FIFO for Q7 is full\n");
        rhAsicInterrupts.rxDeq[port].dataFifoOverflow7++;
    }

    regVal = 0;
    regGet(regdb, StsDeqEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: MTU Buffer data has an ECC error\n");
        rhAsicInterrupts.rxDeq[port].eccErr++;
    }

    regVal = 0;
    regGet(regdb, StsDeqEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: MTU Buffer data has an Single Correctable error\n");
        rhAsicInterrupts.rxDeq[port].eccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsDeqEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("RX DEQUEUER: MTU Buffer data has an Double Uncorrectable error\n");
        rhAsicInterrupts.rxDeq[port].eccDoubleErr++;
    }
}

void rhAsicRxXAUIUpIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.rxXauiUpLink[port].total++;

    regVal = 0;
    regGet(regdb, StsRegRxRSInterrupt, 0, &regVal);

    if (regVal & RXXAUI_REMOTEFAULTSTATUS) {
        osPrintf("RX XAUI UpLink: Remote Fault detected\n");
        rhAsicInterrupts.rxXauiUpLink[port].remoteLinkFaultStatus++;
    }

    if (regVal & RXXAUI_LOCALFAULTSTATUS) {
        osPrintf("RX XAUI UpLink: Local Fault detected\n");
        rhAsicInterrupts.rxXauiUpLink[port].localLinkFaultStatus++;
    }
}

void rhAsicTxMemMgrIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.txMemMgr[port].total++;

    regVal = 0;
    regGet(regdb, StsTxMemMgrEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TX MEM MGR: MTU Buffer has an ECC error\n");
        rhAsicInterrupts.txMemMgr[port].eccErr++;
    }

    regVal = 0;
    regGet(regdb, StsTxMemMgrEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TX MEM MGR: MTU Buffer has a Single correctable ECC error\n");
        rhAsicInterrupts.txMemMgr[port].eccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsTxMemMgrEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TX MEM MGR: MTU Buffer has a Double uncorrectable ECC error\n");
        rhAsicInterrupts.txMemMgr[port].eccDoubleErr++;
    }

    regVal = 0;
    regGet(regdb, StsTxMemMgrMTUFifoOverflowInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TX MEM MGR: MTU Buffer Overflow Interrupt\n");
        rhAsicInterrupts.txMemMgr[port].mtuFifoOverflow++;
    }

    regVal = 0;
    regGet(regdb, StsTxMemMgrMTUFifoUnderflowInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TX MEM MGR: MTU Buffer Underflow Interrupt\n");
        rhAsicInterrupts.txMemMgr[port].mtuFifoUnderflow++;
    }

    regVal = 0;
    regGet(regdb, StsTxMemMgrEFHFifoOverflowInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TX MEM MGR: EFH Buffer Overflow Interrupt\n");
        rhAsicInterrupts.txMemMgr[port].efhFifoOverflow++;
    }

    regVal = 0;
    regGet(regdb, StsTxMemMgrEFHFifoUnderflowInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TX MEM MGR: EFH Buffer Underflow Interrupt\n");
        rhAsicInterrupts.txMemMgr[port].efhFifoUnderflow++;
    }
}

void rhAsicTxpSpiIntr(reginfo_t *regdb)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.txpSpi.total++;

        regVal = 0;
        regGet(regdb, StsRegTSpiInterrupt, 0, &regVal);

        if (regVal & TXSPI_FIFOOVERFLOW) {
            osPrintf("TXPSPI: FIFO OverFlow; Use Softreset to clear\n");
            rhAsicInterrupts.txpSpi.tSpiFifoOverFlow++;
        }

        if (regVal & TXSPI_LOSSOFSYNC) {
            osPrintf("TXPSPI: Loss Of Sync\n");
            rhAsicInterrupts.txpSpi.tSpiLossOfSync++;
        }

        if (regVal & TXSPI_PROTOCOLVIOLATION) {
            osPrintf("TXPSPI: Protocol Violation on SPI Bus\n");
            rhAsicInterrupts.txpSpi.tSpiProtocolViolation++;
        }

        if (regVal & TXSPI_HIGHDIP4ERROR) {
            osPrintf("TXPSPI: Excess DIP4 errors\n");
            rhAsicInterrupts.txpSpi.tSpiHighDip4Error++;
        }
}

void rhAsicTxsSpiIntr(reginfo_t *regdb)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.txsSpi.total++;

    regVal = 0;
    regGet(regdb, StsRegTxSSpiInterrupt, 0, &regVal);

    if (regVal & TXSPI_FIFOOVERFLOW) {
        osPrintf("TXSSPI: FIFO OverFlow; Use Softreset to clear\n");
        rhAsicInterrupts.txsSpi.txSSpiFifoOverFlow++;
    }

    if (regVal & TXSPI_LOSSOFSYNC) {
        osPrintf("TXSSPI: Loss Of Sync\n");
        rhAsicInterrupts.txsSpi.txSSpiLossOfSync++;
    }

    if (regVal & TXSPI_PROTOCOLVIOLATION) {
        osPrintf("TXSSPI: Protocol Violation on SPI Bus\n");
        rhAsicInterrupts.txsSpi.txSSpiProtocolViolation++;
    }

    if (regVal & TXSPI_HIGHDIP4ERROR) {
        osPrintf("TXSSPI: Excess DIP4 errors\n");
        rhAsicInterrupts.txsSpi.txSSpiHighDip4Error++;
    }

    regVal = 0;
    regGet(regdb, StsMiscEccErrorInterrupt0, 0, &regVal);
    if (regVal) {
        osPrintf("TXSSPI : ECC Error Interrupt 0\n");
        rhAsicInterrupts.txsSpi.miscEccErr0++;
    }

    regVal = 0;
    regGet(regdb, StsMiscEccSingleErrorInterrupt0, 0, &regVal);
    if (regVal) {
        osPrintf("TXSSPI : ECC Single Error Interrupt 0\n");
        rhAsicInterrupts.txsSpi.miscEccSingleErr0++;
    }

    regVal = 0;
    regGet(regdb, StsMiscEccDoubleErrorInterrupt0, 0, &regVal);
    if (regVal) {
        osPrintf("TXSSPI : ECC Double Error Interrupt 0\n");
        rhAsicInterrupts.txsSpi.miscEccDoubleErr0++;
    }

    regVal = 0;
    regGet(regdb, StsMiscEccErrorInterrupt1, 0, &regVal);
    if (regVal) {
        osPrintf("TXSSPI : ECC Error Interrupt 1\n");
        rhAsicInterrupts.txsSpi.miscEccErr1++;
    }

    regVal = 0;
    regGet(regdb, StsMiscEccSingleErrorInterrupt1, 0, &regVal);
    if (regVal) {
        osPrintf("TXSSPI : ECC Single Error Interrupt 1\n");
        rhAsicInterrupts.txsSpi.miscEccSingleErr1++;
    }

    regVal = 0;
    regGet(regdb, StsMiscEccDoubleErrorInterrupt1, 0, &regVal);
    if (regVal) {
        osPrintf("TXSSPI : ECC Double Error Interrupt 1\n");
        rhAsicInterrupts.txsSpi.miscEccDoubleErr1++;
    }
}

void rhAsicRxWredIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.rxWred[port].total++;

    regVal = 0;
    regGet(regdb, StsEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("RX WRED: ECC error\n");
        rhAsicInterrupts.rxWred[port].err++;
    }

    regVal = 0;
    regGet(regdb, StsEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("RX WRED: Single Correctable Ecc error\n");
        rhAsicInterrupts.rxWred[port].singleErr++;
    }

    regVal = 0;
    regGet(regdb, StsEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("RX WRED: Double Uncorrectable Ecc error\n");
        rhAsicInterrupts.rxWred[port].doubleErr++;
    }
}

void rhAsicMemEnqIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.memEnq[port].total++;

    regVal = 0;
    regGet(regdb, StsDMEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("MEM ENQUEUE: ECC error\n");
        rhAsicInterrupts.memEnq[port].dmeccErr++;
    }

    regVal = 0;
    regGet(regdb, StsDMEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("MEM ENQUEUE: Single Correctable ECC error\n");
        rhAsicInterrupts.memEnq[port].dmeccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsDMEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("MEM ENQUEUE: Double Uncorrectable ECC error\n");
        rhAsicInterrupts.memEnq[port].dmeccDoubleErr++;
    }

    regVal = 0;
    regGet(regdb, StsEnqSequenceErrInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("MEM ENQUEUE: SOP Sequence error\n");
        rhAsicInterrupts.memEnq[port].enqSequenceErr++;
    }

    regVal = 0;
    regGet(regdb, StsEnqDFifoOverflowInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("MEM ENQUEUE: FIFO Overflow\n");
        rhAsicInterrupts.memEnq[port].enqDFifoOverflow++;
    }

    regVal = 0;
    regGet(regdb, StsEnqSzLstFifoOverflowInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("MEM ENQUEUE: List FIFO Overflow\n");
        rhAsicInterrupts.memEnq[port].enqSzLstFifoOverflow++;
    }
}

void rhAsicTxVLanCtrlIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.txVlanCtrl[port].total++;

    regVal = 0;
    regGet(regdb, StsRegUnderRunIntr, port, &regVal);
    if (regVal) {
        osPrintf("TXVLAN CTRL: Under Run Interrupt\n");
        rhAsicInterrupts.txVlanCtrl[port].underRunIntr++;
    }

    regVal = 0;
    regGet(regdb, StsTxVlanEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TXVLAN CTRL: ECC Error Interrupt\n");
        rhAsicInterrupts.txVlanCtrl[port].err++;
    }

    regVal = 0;
    regGet(regdb, StsTxVlanEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TXVLAN CTRL: ECC Single Error Interrupt\n");
        rhAsicInterrupts.txVlanCtrl[port].singleErr++;
    }

    regVal = 0;
    regGet(regdb, StsTxVlanEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TXVLAN CTRL: ECC Double Error Interrupt\n");
        rhAsicInterrupts.txVlanCtrl[port].doubleErr++;
    }
}

void rhAsicTxCpuToLineIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    regVal = 0;
    regGet(regdb, StsCpuToLineEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TXCPUTOLINE INTR: ECC Error Interrupt\n");
        rhAsicInterrupts.cpuToLine[port].err++;
    }

    regVal = 0;
    regGet(regdb, StsCpuToLineEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TXCPUTOLINE INTR: Single ECC Error Interrupt\n");
        rhAsicInterrupts.cpuToLine[port].singleErr++;
    }

    regVal = 0;
    regGet(regdb, StsCpuToLineEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("TXCPUTOLINE INTR: Double ECC Error Interrupt\n");
        rhAsicInterrupts.cpuToLine[port].doubleErr++;
    }
}

void rhAsicMdioIntr(reginfo_t *regdb)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.mdio.total++;

    regVal = 0;
    regGet(regdb, StsRegMDIOInterrupt, 0, &regVal);
    if(regVal & MDIO_AUTOSCANPHY1) {
        osPrintf("MDIO: PHY1 AutoScan Interrupt\n");
        rhAsicInterrupts.mdio.autoScanPhy1++;
    }

    if(regVal & MDIO_AUTOSCANPHY0) {
        osPrintf("MDIO: PHY0 AutoScan Interrupt\n");
        rhAsicInterrupts.mdio.autoScanPhy0++;
    }

    if(regVal & MDIO_COMMANDDONE) {
        osPrintf("MDIO: Command Done Interrupt\n");
        rhAsicInterrupts.mdio.cmdDone++;
    }
}

void rhAsicDropCtrlIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.drpCtrl[port].total++;

    regVal = 0;
    regGet(regdb, StsMiscEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: ECC error\n");
        rhAsicInterrupts.drpCtrl[port].miscEccErr++;
    }

    regVal = 0;
    regGet(regdb, StsMiscEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Single Correctable ECC error\n");
        rhAsicInterrupts.drpCtrl[port].miscEccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsMiscEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Double Uncorrectable ECC error\n");
        rhAsicInterrupts.drpCtrl[port].miscEccDoubleErr++;
    }

    regVal = 0;
    regGet(regdb, StsOVLANCPUEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Outer VLAN Ctrl Table ECC error\n");
        rhAsicInterrupts.drpCtrl[port].oVlanCpuEccErr++;
    }

    regVal = 0;
    regGet(regdb, StsOVLANCPUEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Outer VLAN Ctrl Table Single Correctable ECC error\n");
        rhAsicInterrupts.drpCtrl[port].oVlanCpuEccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsOVLANCPUEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Outer VLAN Ctrl Table Double Uncorrectable ECC error\n");
        rhAsicInterrupts.drpCtrl[port].oVlanCpuEccDoubleErr++;
    }

    regVal = 0;
    regGet(regdb, StsOVLANCtrlEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Outer VLAN Ctrl Logic ECC error\n");
        rhAsicInterrupts.drpCtrl[port].oVlanCtrlEccErr++;
    }

    regVal = 0;
    regGet(regdb, StsOVLANCtrlEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Outer VLAN Ctrl Logic Single Correctable ECC error\n");
        rhAsicInterrupts.drpCtrl[port].oVlanCtrlEccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsOVLANCtrlEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Outer VLAN Ctrl Logic Double Uncorrectable ECC error\n");
        rhAsicInterrupts.drpCtrl[port].oVlanCtrlEccDoubleErr++;
    }

    regVal = 0;
    regGet(regdb, StsIVLANCPUEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Inner VLAN Control Table ECC error\n");
        rhAsicInterrupts.drpCtrl[port].iVlanCpuEccErr++;
    }

    regVal = 0;
    regGet(regdb, StsIVLANCPUEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Inner VLAN Control Table Single Correctable ECC error\n");
        rhAsicInterrupts.drpCtrl[port].iVlanCpuEccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsIVLANCPUEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Inner VLAN Control Table Double Uncorrectable ECC error\n");
        rhAsicInterrupts.drpCtrl[port].iVlanCpuEccDoubleErr++;
    }

    regVal = 0;
    regGet(regdb, StsIVLANCtrlEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Inner VLAN Control Logic ECC error\n");
        rhAsicInterrupts.drpCtrl[port].iVlanCtrlEccErr++;
    }

    regVal = 0;
    regGet(regdb, StsIVLANCtrlEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Inner VLAN Control Logic Single Correctable ECC error\n");
        rhAsicInterrupts.drpCtrl[port].iVlanCtrlEccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsIVLANCtrlEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("DROP CTRL: Inner VLAN Control Logic Double Uncorrectable ECC error\n");
        rhAsicInterrupts.drpCtrl[port].iVlanCtrlEccDoubleErr++;
    }
}

void rhAsicShadowIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.shadow[port].total++;

    regVal = 0;
    regGet(regdb, StsShadowEventTrigIntr, port, &regVal);
    if (regVal) {
        osPrintf("SHADOW: Shadow Event Triggered\n");
        rhAsicInterrupts.shadow[port].eventTrigger++;
    }
}

void rhAsicLineToCpuIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal;

    /* Increment the total count of interrupts */
    rhAsicInterrupts.lineToCpu[port].total++;

    regVal = 0;
    regGet(regdb, StsLineToCPUFifoFullInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("LINETOCPU: CPU FIFO Full\n");
        rhAsicInterrupts.lineToCpu[port].fifoFull++;
    }

    regVal = 0;
    regGet(regdb, StsLineToCPUFifoEmptyInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("LINETOCPU: CPU FIFO Empty\n");
        rhAsicInterrupts.lineToCpu[port].fifoEmpty++;
    }

    regVal = 0;
    regGet(regdb, StsLineToCPUFifoDataInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("LINETOCPU: CPU FIFO Data Interrupt\n");
        rhAsicInterrupts.lineToCpu[port].fifoData++;
    }

    regVal = 0;
    regGet(regdb, StsLineToCPUEccErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("LINETOCPU: ECC error\n");
        rhAsicInterrupts.lineToCpu[port].eccErr++;
    }

    regVal = 0;
    regGet(regdb, StsLineToCPUEccSingleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("LINETOCPU: Single Correctable ECC error\n");
        rhAsicInterrupts.lineToCpu[port].eccSingleErr++;
    }

    regVal = 0;
    regGet(regdb, StsLineToCPUEccDoubleErrorInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("LINETOCPU: Double Uncorrectable ECC error\n");
        rhAsicInterrupts.lineToCpu[port].eccDoubleErr++;
    }

    regVal = 0;
    regGet(regdb, StsLineToCPUFifoUnderrunInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("LINETOCPU: FIFO Underrun\n");
        rhAsicInterrupts.lineToCpu[port].fifoUnderrun++;
    }
}


void rhAsicTxPortIntr(reginfo_t *regdb, int port)
{
    unsigned int regVal, intrMask;
    /* osPrintf("Tx PCS Interrupt from port %d\n", port); */

    /* Increment the total count of interrupts */
    rhAsicInterrupts.txPrtInterface[port].total++;

    intrMask = regVal=0;
    regGet(regdb, StsRxSyncStatusChangedInterruptMask, port, &intrMask);
    if (!intrMask) {
        osPrintf("TXPORT: SYNC status changes in Rx PCS for port %d\n", port);
        regGet(regdb, StsRxSyncStatusChangedInterrupt, port, &regVal);
        if (regVal) {
            osPrintf ("Checking for multiple threads on port %d\n", port);
            while (1) {
                if (port == 0) {
                    if (!syncStatusChangedThreadP0) {
                        syncStatusChangedThreadP0 = 1;
                        break;
                    }
                } else {
                    if (!syncStatusChangedThreadP1) {
                        syncStatusChangedThreadP1 = 1;
                        break;
                    }
                }
            }

            rhAsicInterrupts.txPrtInterface[port].syncStatusChanged++;

            osPrintf ("Calling Thread Create function for port %d\n", port);
            /* Create a thread for polling */
            if (port == 0)
                osThreadCreateXFI0((void *)redHawkRegs, port);
            else
                osThreadCreateXFI1((void *)redHawkRegs, port);
            osPrintf ("Done with spanning the thread for port %d\n", port);
        }
    }

    regVal=0;
    regGet(regdb, StsRxPcsAlignFailInterrupt, port, &regVal);
    if (regVal) {
        osPrintf("PCS align failed\n");
        rhAsicInterrupts.txPrtInterface[port].pcsAlignFail++;
    }
}

/******************************************************************
* rhAsicInterruptHandler - RedHawk ASIC main Interrupt handler
*
* This routine implements the main interrupt handling functions of
* RedHawk ASIC.  Based on interrupt source, it invokes sub
* interrupt handler functions.
*
* This interrupt handler should run in task level context.
*
* RETURNS: NONE
*/
void rhAsicInterruptHandler (reginfo_t *regdb)
{
    unsigned int intSrc = 0;

    /* Read the Interrupt Source1 register */
    regGet(regdb, StsRegCoInterruptSource0, 0, &intSrc);

    /* Check for the interrupts */
    if (intSrc) {

        /* Check for the common Interrupt */
        if (intSrc & COMMON_INTR)
            rhAsicCommonIntr(regdb);

        /* Check for the RxMac port 0 interrupt */
        if (intSrc & RXMAC_INTR_P0)
            rhAsicRxMacIntr(regdb, 0); /* Passing the port number */

        /* Check for the RxMac port 1 interrupt */
        if (intSrc & RXMAC_INTR_P1)
            rhAsicRxMacIntr(regdb, 1); /* Passing the port number */

        /* Check for the TxMac port 0 and port 1 Configuration interrupt  */
        if (intSrc & TXMAC_CFGINTR_P0);
        if (intSrc & TXMAC_CFGINTR_P1);

        /* Check for the TxMac port 0 Statistics interrupt */
        if (intSrc & TXMAC_STSINTR_P0)
            rhAsicTxMacIntr(regdb, 0); /* Passing the port number */

        /* Check for the TxMac port 1 Statistics interrupt */
        if (intSrc & TXMAC_STSINTR_P1)
            rhAsicTxMacIntr(regdb, 1); /* Passing the port number */

        /* Check for the RxPSPI Interrupt */
        if (intSrc & RXPSPI_INTR)
            rhAsicRxSpiIntr(regdb, 1);

        /* Check for the RxSSPI Interrupt */
        if (intSrc & RXSSPI_INTR)
            rhAsicRxSpiIntr(regdb, 0);

        /* Check for the Queue Manager Interrupt for port 0 */
        if (intSrc & QUEUEMGR_INTR_P0)
            rhAsicDatabaseMgrIntr(regdb, 0);

        /* Check for the Queue Manager Interrupt for port 1 */
        if (intSrc & QUEUEMGR_INTR_P1)
            rhAsicDatabaseMgrIntr(regdb, 1);

        /* Check for the Dual Memory Control Interrupt for port 0 */
        if (intSrc & DUALMEMCTRL_INTR_P0)
            rhAsicExtMemIntr(regdb, 0); /* Passing the port number */

        /* Check for the Dual Memory Control Interrupt for port 1 */
        if (intSrc & DUALMEMCTRL_INTR_P1)
            rhAsicExtMemIntr(regdb, 1); /* Passing the port number */

        /* Check Rx Dequeuer Interrupt for port 0 */
        if (intSrc & DEQUEUER_INTR_P0)
            rhAsicRxDeqIntr(regdb, 0); /* Passing the port number */

        /* Check Rx Dequeuer Interrupt for port 1 */
        if (intSrc & DEQUEUER_INTR_P1)
            rhAsicRxDeqIntr(regdb, 1); /* Passing the port number */

        /* Check for RxHighGigXMac Interrupt for port 0 */
        if (intSrc & RXHIGIGXMAC_INTR_P0)
            rhAsicRxXAUIUpIntr(regdb, 0); /* Passing the port number */

        /* Check for RxHighGigXMac Interrupt for port 1 */
        if (intSrc & RXHIGIGXMAC_INTR_P1)
            rhAsicRxXAUIUpIntr(regdb, 1); /* Passing the port number */

        /* Check for the TxHiGigXMac Interrupt for port 0 and 1 */
        if (intSrc & TXHIGIGXMAC_INTR_P0);
        if (intSrc & TXHIGIGXMAC_INTR_P1);

        /* Check for the Tx Memory Manager Interrupt for port 0 */
        if (intSrc & TXMEMMGR_INTR_P0)
            rhAsicTxMemMgrIntr(regdb, 0); /* Passing port number */

        /* Check for the Tx Memory Manager Interrupt for port 1 */
        if (intSrc & TXMEMMGR_INTR_P1)
            rhAsicTxMemMgrIntr(regdb, 1); /* Passing port number */

        /* Check for the Common Interrupt */
        if (intSrc & TXMEMMGRCOMM_INTR);

        /* Check for the TxpSPI Interrupt */
        if (intSrc & TXPSPI_INTR)
            rhAsicTxpSpiIntr(regdb);

        /* Check for the TxsSPI Interrupt */
        if (intSrc & TXSSPI_INTR)
            rhAsicTxsSpiIntr(regdb);

        /* Check for the Rx Wred Interrupt for port 0 */
        if (intSrc & RXWRED_INTR_P0)
            rhAsicRxWredIntr(regdb, 0); /* Passing the port number */

        /* Check for the Rx Wred Interrupt for port 1 */
        if (intSrc & RXWRED_INTR_P1)
            rhAsicRxWredIntr(regdb, 1); /* Passing the port number */

        /* Check for the Memory Enqueuer Interrupt for port 0 */
        if (intSrc & ENQUEUER_INTR_P0)
            rhAsicMemEnqIntr(regdb, 0); /* Passing the port number */

        /* Check for the Memory Enqueuer Interrupt for port 1 */
        if (intSrc & ENQUEUER_INTR_P1)
            rhAsicMemEnqIntr(regdb, 1); /* Passing the port number */

        /* Check for the Tx VLAN Control Interrupt for port 0 */
        if (intSrc & TXVLANCTRL_INTR_P0)
            rhAsicTxVLanCtrlIntr(regdb, 0); /* Passing the port number */

        /* Check for the Tx VLAN Control Interrupt for port 1 */
        if (intSrc & TXVLANCTRL_INTR_P1)
            rhAsicTxVLanCtrlIntr(regdb, 1); /* Passing the port number */

        /* Check for the CPU To Line Interrupt for port 0 */
        if (intSrc & TXCPUTOLINE_INTR_P0)
            rhAsicTxCpuToLineIntr(regdb, 0); /* Passing the port number */

        /* Check for the CPU To Line Interrupt for port 1 */
        if (intSrc & TXCPUTOLINE_INTR_P1);
            rhAsicTxCpuToLineIntr(regdb, 1); /* Passing the port number */
    }

    intSrc = 0;
    /* Read the second interrupt source register */
    regGet(regdb, StsRegCoInterruptSource1, 0, &intSrc);

    /* Check for the interrupts */
    if (intSrc) {
        /* Check for the MDIO interrupt */
        if (intSrc & MDIO_INTR)
            rhAsicMdioIntr(regdb);

        /* Check for the Rx Drop Control Interrupt for port 0 */
        if (intSrc & RXDROPCTRL_INTR_P0)
            rhAsicDropCtrlIntr(regdb, 0); /* Passing the port number */

        /* Check for the Rx Drop Control Interrupt for port 1 */
        if (intSrc & RXDROPCTRL_INTR_P1)
            rhAsicDropCtrlIntr(regdb, 1); /* Passing the port number */

        /* Check for the Rx Drop Control Statistics Interrupt for port 0 and port 1 */
        if (intSrc & RXDROPCTRLSTAT_INTR_P0);
        if (intSrc & RXDROPCTRLSTAT_INTR_P1);

        /* Check for the Shadow Interrupt for port 0 */
        if (intSrc & SHADOWREG_INTR_P0)
            rhAsicShadowIntr(regdb, 0); /* passing the port number */

        /* Check for the Shadow Interrupt for port 1 */
        if (intSrc & SHADOWREG_INTR_P1)
            rhAsicShadowIntr(regdb, 1); /* passing the port number */

        /* Check for the Line To CPU Interrupt for port 0 */
        if (intSrc & RXLINETOCPUINTR_P0)
            rhAsicLineToCpuIntr(regdb, 0); /* passing the port number */

        /* Check for the Line To CPU Interrupt for port 1 */
        if (intSrc & RXLINETOCPUINTR_P1)
            rhAsicLineToCpuIntr(regdb, 1); /* passing the port number */

        /* Check for the LED Interrupt for ports 1 and 0 */
        if (intSrc & LED_INTR_P0);
        if (intSrc & LED_INTR_P1);

        /* Check for the Reserved bits */
        if (intSrc & RSVD_0);
        if (intSrc & RSVD_1);

        /* Check for the Tx PCS Interrupt for port 0 */
        if (intSrc & TXPCS_INTR_P0)
            rhAsicTxPortIntr(regdb, 0);

        /* Check for the Tx PCS Interrupt for port 1 */
        if (intSrc & TXPCS_INTR_P1)
            rhAsicTxPortIntr(regdb, 1);
    }

}

/*************************************************************************
 *
 * RedHawk ASIC Interrupt Functions
 *
 *************************************************************************/
void unmask_intr(int regid)
{
    int numInst, i;

    numInst = redHawkRegs[regid].instMax;

    /* Unmask all the instances */
    for (i=0; i<numInst; i++)
        regSet(redHawkRegs, regid, i, 0);
}

/******************************************************************
* rhAsicUnmaskInterrupts - Unmask all the RedHawk Interrupts
*
* This routine unmasks all the RedHawk Interrupts
*
* RETURNS : None
*/
void rhAsicUnmaskInterrupts()
{
    unmask_intr(StsRegCoClkMonInterruptMask);
    unmask_intr(StsRegCoXAUIInterruptMask);
    unmask_intr(StsRegCoXFIInterruptMask);
    unmask_intr(StsRegCo2wiremasterInterruptMask);
    unmask_intr(StsRegMDIOInterruptMask);
    unmask_intr(StsShadowEventTrigIntrMask);
    unmask_intr(StsRegRxMACInterruptMask);
    unmask_intr(StsMiscEccErrorInterruptMask);
    unmask_intr(StsMiscEccSingleErrorInterruptMask);
    unmask_intr(StsMiscEccDoubleErrorInterruptMask);
    unmask_intr(StsOVLANCPUEccErrorInterruptMask);
    unmask_intr(StsOVLANCPUEccSingleErrorInterruptMask);
    unmask_intr(StsOVLANCPUEccDoubleErrorInterruptMask);
    unmask_intr(StsOVLANCtrlEccErrorInterruptMask);
    unmask_intr(StsOVLANCtrlEccSingleErrorInterruptMask);
    unmask_intr(StsOVLANCtrlEccDoubleErrorInterruptMask);
    unmask_intr(StsIVLANCPUEccErrorInterruptMask);
    unmask_intr(StsIVLANCPUEccSingleErrorInterruptMask);
    unmask_intr(StsIVLANCPUEccDoubleErrorInterruptMask);
    unmask_intr(StsIVLANCtrlEccErrorInterruptMask);
    unmask_intr(StsIVLANCtrlEccSingleErrorInterruptMask);
    unmask_intr(StsIVLANCtrlEccDoubleErrorInterruptMask);
    unmask_intr(StsEccErrorInterruptMask);
    unmask_intr(StsEccSingleErrorInterruptMask);
    unmask_intr(StsEccDoubleErrorInterruptMask);
    unmask_intr(StsLineToCPUFifoFullInterruptMask);
    unmask_intr(StsLineToCPUFifoEmptyInterruptMask);
    unmask_intr(StsLineToCPUFifoDataInterruptMask);
    unmask_intr(StsLineToCPUEccErrorInterruptMask);
    unmask_intr(StsLineToCPUEccSingleErrorInterruptMask);
    unmask_intr(StsLineToCPUEccDoubleErrorInterruptMask);
    unmask_intr(StsLineToCPUFifoUnderrunInterruptMask);
    unmask_intr(StsDMEccErrorInterruptMask);
    unmask_intr(StsDMEccSingleErrorInterruptMask);
    unmask_intr(StsDMEccDoubleErrorInterruptMask);
    unmask_intr(StsEnqSequenceErrInterruptMask);
    unmask_intr(StsEnqDFifoOverflowInterruptMask);
    unmask_intr(StsEnqSzLstFifoOverflowInterruptMask);
    unmask_intr(StsMemAccessInterruptMask);
    unmask_intr(StsTotalRsvdPageCountInterruptMask);
    unmask_intr(StsPageFifoOverflowInterruptMask);
    unmask_intr(StsQmFptEccErrorInterruptMask);
    unmask_intr(StsQmFptEccSingleErrorInterruptMask);
    unmask_intr(StsQmFptEccDoubleErrorInterruptMask);
    unmask_intr(StsQmPltEccErrorInterruptMask);
    unmask_intr(StsQmPltEccSingleErrorInterruptMask);
    unmask_intr(StsQmPltEccDoubleErrorInterruptMask);
    unmask_intr(StsDeqQnumFifoOverflowInterruptMask);
    unmask_intr(StsDeqDataFifoOverflowInterrupt0Mask);
    unmask_intr(StsDeqDataFifoOverflowInterrupt1Mask);
    unmask_intr(StsDeqDataFifoOverflowInterrupt2Mask);
    unmask_intr(StsDeqDataFifoOverflowInterrupt3Mask);
    unmask_intr(StsDeqDataFifoOverflowInterrupt4Mask);
    unmask_intr(StsDeqDataFifoOverflowInterrupt5Mask);
    unmask_intr(StsDeqDataFifoOverflowInterrupt6Mask);
    unmask_intr(StsDeqDataFifoOverflowInterrupt7Mask);
    unmask_intr(StsDeqEccErrorInterruptMask);
    unmask_intr(StsDeqEccSingleErrorInterruptMask);
    unmask_intr(StsDeqEccDoubleErrorInterruptMask);
    unmask_intr(StsRegRxpSpiInterruptMask);
    unmask_intr(StsRegRxsSpiInterruptMask);
    unmask_intr(StsRegRxRSInterruptMask);
    unmask_intr(StsRxPcsAlignFailInterruptMask);
    unmask_intr(StsRxSyncStatusChangedInterruptMask);
    unmask_intr(StsRegTxMACInterruptMask);
    unmask_intr(StsRegUnderRunIntrMask);
    unmask_intr(StsTxVlanEccErrorInterruptMask);
    unmask_intr(StsTxVlanEccSingleErrorInterruptMask);
    unmask_intr(StsTxVlanEccDoubleErrorInterruptMask);
    unmask_intr(StsTxMemMgrEccErrorInterruptMask);
    unmask_intr(StsTxMemMgrEccSingleErrorInterruptMask);
    unmask_intr(StsTxMemMgrEccDoubleErrorInterruptMask);
    unmask_intr(StsTxMemMgrMTUFifoOverflowInterruptMask);
    unmask_intr(StsTxMemMgrMTUFifoUnderflowInterruptMask);
    unmask_intr(StsTxMemMgrEFHFifoOverflowInterruptMask);
    unmask_intr(StsTxMemMgrEFHFifoUnderflowInterruptMask);
    unmask_intr(StsCpuToLineEccErrorInterruptMask);
    unmask_intr(StsCpuToLineEccSingleErrorInterruptMask);
    unmask_intr(StsCpuToLineEccDoubleErrorInterruptMask);
    unmask_intr(StsRegTSpiInterruptMask);
    unmask_intr(StsRegTxSSpiInterruptMask);
    unmask_intr(StsMiscEccErrorInterrupt0Mask);
    unmask_intr(StsMiscEccSingleErrorInterrupt0Mask);
    unmask_intr(StsMiscEccDoubleErrorInterrupt0Mask);
    unmask_intr(StsMiscEccErrorInterrupt1Mask);
    unmask_intr(StsMiscEccSingleErrorInterrupt1Mask);
    unmask_intr(StsMiscEccDoubleErrorInterrupt1Mask);
}

void mask_intr(int regid)
{
    int numInst, i;

    numInst = redHawkRegs[regid].instMax;

    /* Unmask all the instances */
    for (i=0; i<numInst; i++)
        regSet(redHawkRegs, regid, i, 0xffffffff);
}

/******************************************************************
* rhAsicMaskInterrupts - Mask all the RedHawk Interrupts
*
* This routine masks all the RedHawk Interrupts
*
* RETURNS : None
*/
void rhAsicMaskInterrupts()
{
    mask_intr(StsRegCoClkMonInterruptMask);
    mask_intr(StsRegCoXAUIInterruptMask);
    mask_intr(StsRegCoXFIInterruptMask);
    mask_intr(StsRegCo2wiremasterInterruptMask);
    mask_intr(StsRegMDIOInterruptMask);
    mask_intr(StsShadowEventTrigIntrMask);
    mask_intr(StsRegRxMACInterruptMask);
    mask_intr(StsMiscEccErrorInterruptMask);
    mask_intr(StsMiscEccSingleErrorInterruptMask);
    mask_intr(StsMiscEccDoubleErrorInterruptMask);
    mask_intr(StsOVLANCPUEccErrorInterruptMask);
    mask_intr(StsOVLANCPUEccSingleErrorInterruptMask);
    mask_intr(StsOVLANCPUEccDoubleErrorInterruptMask);
    mask_intr(StsOVLANCtrlEccErrorInterruptMask);
    mask_intr(StsOVLANCtrlEccSingleErrorInterruptMask);
    mask_intr(StsOVLANCtrlEccDoubleErrorInterruptMask);
    mask_intr(StsIVLANCPUEccErrorInterruptMask);
    mask_intr(StsIVLANCPUEccSingleErrorInterruptMask);
    mask_intr(StsIVLANCPUEccDoubleErrorInterruptMask);
    mask_intr(StsIVLANCtrlEccErrorInterruptMask);
    mask_intr(StsIVLANCtrlEccSingleErrorInterruptMask);
    mask_intr(StsIVLANCtrlEccDoubleErrorInterruptMask);
    mask_intr(StsEccErrorInterruptMask);
    mask_intr(StsEccSingleErrorInterruptMask);
    mask_intr(StsEccDoubleErrorInterruptMask);
    mask_intr(StsLineToCPUFifoFullInterruptMask);
    mask_intr(StsLineToCPUFifoEmptyInterruptMask);
    mask_intr(StsLineToCPUFifoDataInterruptMask);
    mask_intr(StsLineToCPUEccErrorInterruptMask);
    mask_intr(StsLineToCPUEccSingleErrorInterruptMask);
    mask_intr(StsLineToCPUEccDoubleErrorInterruptMask);
    mask_intr(StsLineToCPUFifoUnderrunInterruptMask);
    mask_intr(StsDMEccErrorInterruptMask);
    mask_intr(StsDMEccSingleErrorInterruptMask);
    mask_intr(StsDMEccDoubleErrorInterruptMask);
    mask_intr(StsEnqSequenceErrInterruptMask);
    mask_intr(StsEnqDFifoOverflowInterruptMask);
    mask_intr(StsEnqSzLstFifoOverflowInterruptMask);
    mask_intr(StsMemAccessInterruptMask);
    mask_intr(StsTotalRsvdPageCountInterruptMask);
    mask_intr(StsPageFifoOverflowInterruptMask);
    mask_intr(StsQmFptEccErrorInterruptMask);
    mask_intr(StsQmFptEccSingleErrorInterruptMask);
    mask_intr(StsQmFptEccDoubleErrorInterruptMask);
    mask_intr(StsQmPltEccErrorInterruptMask);
    mask_intr(StsQmPltEccSingleErrorInterruptMask);
    mask_intr(StsQmPltEccDoubleErrorInterruptMask);
    mask_intr(StsDeqQnumFifoOverflowInterruptMask);
    mask_intr(StsDeqDataFifoOverflowInterrupt0Mask);
    mask_intr(StsDeqDataFifoOverflowInterrupt1Mask);
    mask_intr(StsDeqDataFifoOverflowInterrupt2Mask);
    mask_intr(StsDeqDataFifoOverflowInterrupt3Mask);
    mask_intr(StsDeqDataFifoOverflowInterrupt4Mask);
    mask_intr(StsDeqDataFifoOverflowInterrupt5Mask);
    mask_intr(StsDeqDataFifoOverflowInterrupt6Mask);
    mask_intr(StsDeqDataFifoOverflowInterrupt7Mask);
    mask_intr(StsDeqEccErrorInterruptMask);
    mask_intr(StsDeqEccSingleErrorInterruptMask);
    mask_intr(StsDeqEccDoubleErrorInterruptMask);
    mask_intr(StsRegRxpSpiInterruptMask);
    mask_intr(StsRegRxsSpiInterruptMask);
    mask_intr(StsRegRxRSInterruptMask);
    mask_intr(StsRxPcsAlignFailInterruptMask);
    mask_intr(StsRxSyncStatusChangedInterruptMask);
    mask_intr(StsRegTxMACInterruptMask);
    mask_intr(StsRegUnderRunIntrMask);
    mask_intr(StsTxVlanEccErrorInterruptMask);
    mask_intr(StsTxVlanEccSingleErrorInterruptMask);
    mask_intr(StsTxVlanEccDoubleErrorInterruptMask);
    mask_intr(StsTxMemMgrEccErrorInterruptMask);
    mask_intr(StsTxMemMgrEccSingleErrorInterruptMask);
    mask_intr(StsTxMemMgrEccDoubleErrorInterruptMask);
    mask_intr(StsTxMemMgrMTUFifoOverflowInterruptMask);
    mask_intr(StsTxMemMgrMTUFifoUnderflowInterruptMask);
    mask_intr(StsTxMemMgrEFHFifoOverflowInterruptMask);
    mask_intr(StsTxMemMgrEFHFifoUnderflowInterruptMask);
    mask_intr(StsCpuToLineEccErrorInterruptMask);
    mask_intr(StsCpuToLineEccSingleErrorInterruptMask);
    mask_intr(StsCpuToLineEccDoubleErrorInterruptMask);
    mask_intr(StsRegTSpiInterruptMask);
    mask_intr(StsRegTxSSpiInterruptMask);
    mask_intr(StsMiscEccErrorInterrupt0Mask);
    mask_intr(StsMiscEccSingleErrorInterrupt0Mask);
    mask_intr(StsMiscEccDoubleErrorInterrupt0Mask);
    mask_intr(StsMiscEccErrorInterrupt1Mask);
    mask_intr(StsMiscEccSingleErrorInterrupt1Mask);
    mask_intr(StsMiscEccDoubleErrorInterrupt1Mask);
}

/*************************************************************************
 *
 * RedHawk ASIC DPG DPV Functions
 *
 *************************************************************************/

/******************************************************************
* rhAsicDpgSetCrc - Configure the CRC for DPG generated packets
*
* This routine configures the CRC for DPG generated packets
* Mode Settings = 0; Don't append CRC
* Mode Settings = 1; Append CRC
* port_num = 0 / 1; Primary SPI DPG/ Secondary SPI DPG
* crc_val = The CRC that has to be appended
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgSetCrc(int mode, int port_num, unsigned int crc_val)
{
    /* Set the DPG Mode */
    if (port_num == 0) {
        if (mode == 1) {
            regSet(redHawkRegs, CfgRegTxPSpiDPGMode__CRCMode, 0, 1);
            regSet(redHawkRegs, CfgRegTxPSpiDPGCRCValue, 0, crc_val);
            regSet(redHawkRegs, CfgRegTxPSpiDPVMode, 0, 1);
        } else {
            regSet(redHawkRegs, CfgRegTxPSpiDPGMode__CRCMode, 0, 0);
            regSet(redHawkRegs, CfgRegTxPSpiDPVMode, 0, 0);
        }
    } else {
        if (mode == 1) {
            regSet(redHawkRegs, CfgRegTxSSpiDPGMode__CRCMode, 0, 1);
            regSet(redHawkRegs, CfgRegTxSSpiDPGCRCValue, 0, crc_val);
            regSet(redHawkRegs, CfgRegTxSSpiDPVMode, 0, 1);
        } else {
            regSet(redHawkRegs, CfgRegTxSSpiDPGMode__CRCMode, 0, 0);
            regSet(redHawkRegs, CfgRegTxSSpiDPVMode, 0, 0);
        }
    }
}

/******************************************************************
* rhAsicDpgSetPktSize - Configure the packet size for DPG generated packets
*
* This routine configures the packet size for DPG generated packets
* port_num = 0 / 1; Primary SPI DPG/ Secondary SPI DPG
* pkt_type = 0 / 1 / 2 (Fixed / Incrementing / Random)
* pkt_size = Fixed packet Size
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgSetPktSize(int port_num, int pkt_type, unsigned int pkt_size)
{
    /* Set the DPG Mode */
    if (port_num == 0) {
        regSet(redHawkRegs, CfgRegTxPSpiDPGMode__PacketSizeMode, 0, pkt_type);
    } else {
        regSet(redHawkRegs, CfgRegTxSSpiDPGMode__PacketSizeMode, 0, pkt_type);
    }

    /* Set the Fixed Packet Size */
    if (pkt_type == 0) {
        if (port_num == 0)
            regSet(redHawkRegs, CfgRegTxPSpiDPGPacketFixed, 0, pkt_size);
        else
            regSet(redHawkRegs, CfgRegTxSSpiDPGPacketFixed, 0, pkt_size);
    }
}

/******************************************************************
* rhAsicDpgSetNumPkts - Configure the number of packets to be generated by DPG
*
* This routine configures the number of packets to be generated by DPG
* port_num = 0 / 1; Primary SPI DPG/ Secondary SPI DPG
* cont_send = 0 / 1 (Fixed / Continouous)
* num_pkts = Number of packets to be transmitted
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgSetNumPkts(int port_num, int cont_send, unsigned int num_pkts)
{
    /* Set the DPG Mode */
    if (port_num == 0)
        regSet(redHawkRegs, CfgRegTxPSpiDPGMode__ContinuousMode, 0, cont_send);
    else
        regSet(redHawkRegs, CfgRegTxSSpiDPGMode__ContinuousMode, 0, cont_send);

    /* Set the Fixed Packet Size */
    if (cont_send == 0) {
        if (port_num == 0)
            regSet(redHawkRegs, CfgRegTxPSpiDPGPacketNumber, 0, num_pkts);
        else
            regSet(redHawkRegs, CfgRegTxSSpiDPGPacketNumber, 0, num_pkts);
    }
}

/******************************************************************
* rhAsicDpgSetGapSize - Configure the Gap size for the packets generated by DPG
*
* This routine configures the Gap size for the packets generated by DPG
* port_num = 0 / 1; Primary SPI DPG/ Secondary SPI DPG
* type = 0 / 1 (Fixed / Random)
* gap_size = Gap Size to be configured
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgSetGapSize(int port_num, int type, unsigned int gap_size)
{
    /* Set the DPG Mode register */
    if (port_num == 0) {
        regSet(redHawkRegs, CfgRegTxPSpiDPGMode__GapSizeMode, 0, type);
    } else {
        regSet(redHawkRegs, CfgRegTxSSpiDPGMode__GapSizeMode, 0, type);
    }

    /* Set the GAP */
    if (type == 0) {
        if (port_num == 0)
            regSet(redHawkRegs, CfgRegTxPSpiDPGGap, 0, gap_size);
        else
            regSet(redHawkRegs, CfgRegTxSSpiDPGGap, 0, gap_size);
    }
}

/******************************************************************
* rhAsicDpgSetPattern - Configure the Data Pattern for the packets generated by DPG
*
* This routine configures the Data Pattern for the packets generated by DPG
* port_num = 0 / 1; Primary SPI DPG/ Secondary SPI DPG
* patt_type = 0 / 1 / 2/ 3 (Fixed / Incrementing / Decrementing / Pseudo Random)
* patt_data = Data Pattern
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgSetPattern(int port_num, int patt_type, unsigned int patt_data)
{
    /* Set the DPG Mode register */
    if (port_num == 0)
        regSet(redHawkRegs, CfgRegTxPSpiDPGMode__PatternMode, 0, patt_type);
    else
        regSet(redHawkRegs, CfgRegTxSSpiDPGMode__PatternMode, 0, patt_type);

    /* Set the GAP */
    if (patt_type == 0) {
        if (port_num == 0)
            regSet(redHawkRegs, CfgRegTxPSpiDPGPatternFixed, 0, patt_data);
        else
            regSet(redHawkRegs, CfgRegTxSSpiDPGPatternFixed, 0, patt_data);
    }
}

/******************************************************************
* rhAsicDpgInsertDA - Configure DPG to insert DA in the packets generated.
*
* This routine configures the DPG to insert DA in the packets generated
* port_num = 0 / 1; Primary SPI DPG/ Secondary SPI DPG
* da_msb = 2 Most Signification Bytes of DA
* da_lsb = 4 Least Significant Bytes of DA
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgInsertDA(int port_num, unsigned int da_msb, unsigned int da_lsb)
{
    unsigned int regVal;

    /* Set the DPG Mode register */
    if (port_num == 0) {
        /* Get the value of Header Mode field */
        regGet(redHawkRegs, CfgRegTxPSpiDPGMode, 0, &regVal);

        /* Set the DA Insert bit in the field */
        regVal = regVal | BIT_13;
        regSet(redHawkRegs, CfgRegTxPSpiDPGMode, 0, regVal);

        /* Set the DA MSB */
        regSet(redHawkRegs, CfgRegTxPSpiDPGDestH, 0, da_msb);

        /* Set the DA LSB */
        regSet(redHawkRegs, CfgRegTxPSpiDPGDestL, 0, da_lsb);

        /* Set the DPV to check the packets for DA */
        regGet(redHawkRegs, CfgRegTxPSpiDPVHdrCtrl, 0, &regVal);
        regVal = regVal | BIT_1;
        regSet(redHawkRegs, CfgRegTxPSpiDPVHdrCtrl, 0, regVal);
    } else {
        /* Get the value of Header Mode field */
        regGet(redHawkRegs, CfgRegTxSSpiDPGMode, 0, &regVal);

        /* Set the DA Insert bit in the field */
        regVal = regVal | BIT_13;
        regSet(redHawkRegs, CfgRegTxSSpiDPGMode, 0, regVal);

        /* Set the DA MSB */
        regSet(redHawkRegs, CfgRegTxSSpiDPGDestH, 0, da_msb);

        /* Set the DA LSB */
        regSet(redHawkRegs, CfgRegTxSSpiDPGDestL, 0, da_lsb);

        /* Set the DPV to check the packets for DA */
        regGet(redHawkRegs, CfgRegTxSSpiDPVHdrCtrl, 0, &regVal);
        regVal = regVal | BIT_1;
        regSet(redHawkRegs, CfgRegTxSSpiDPVHdrCtrl, 0, regVal);
    }
}

/******************************************************************
* rhAsicDpgInsertSA - Configure DPG to insert SA in the packets generated.
*
* This routine configures the DPG to insert SA in the packets generated
* port_num = 0 / 1; Primary SPI DPG/ Secondary SPI DPG
* sa_msb = 2 Most Signification Bytes of SA
* sa_lsb = 4 Least Significant Bytes of SA
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgInsertSA(int port_num, unsigned int sa_msb, unsigned int sa_lsb)
{
    unsigned int regVal;

    /* Set the DPG Mode register */
    if (port_num == 0) {
        /* Get the value of Header Mode field */
        regGet(redHawkRegs, CfgRegTxPSpiDPGMode, 0, &regVal);

        /* Set the SA Insert bit in the field */
        regVal = regVal | BIT_14;
        regSet(redHawkRegs, CfgRegTxPSpiDPGMode, 0, regVal);

        /* Set the SA MSB */
        regSet(redHawkRegs, CfgRegTxPSpiDPGSrcH, 0, sa_msb);

        /* Set the SA LSB */
        regSet(redHawkRegs, CfgRegTxPSpiDPGSrcL, 0, sa_lsb);

        /* Set the DPV to check the packets for SA */
        regGet(redHawkRegs, CfgRegTxPSpiDPVHdrCtrl, 0, &regVal);
        regVal = regVal | BIT_2;
        regSet(redHawkRegs, CfgRegTxPSpiDPVHdrCtrl, 0, regVal);
    } else {
        /* Get the value of Header Mode field */
        regGet(redHawkRegs, CfgRegTxSSpiDPGMode, 0, &regVal);

        /* Set the SA Insert bit in the field */
        regVal = regVal | BIT_14;
        regSet(redHawkRegs, CfgRegTxSSpiDPGMode, 0, regVal);

        /* Set the SA MSB */
        regSet(redHawkRegs, CfgRegTxSSpiDPGSrcH, 0, sa_msb);

        /* Set the SA LSB */
        regSet(redHawkRegs, CfgRegTxSSpiDPGSrcL, 0, sa_lsb);

        /* Set the DPV to check the packets for SA */
        regGet(redHawkRegs, CfgRegTxSSpiDPVHdrCtrl, 0, &regVal);
        regVal = regVal | BIT_2;
        regSet(redHawkRegs, CfgRegTxSSpiDPVHdrCtrl, 0, regVal);
    }
}

/******************************************************************
* rhAsicDpgInsertPreamble - Configure DPG to insert Preamble in the packets generated.
*
* This routine configures the DPG to insert Preamble in the packets generated
* port_num = 0 / 1; Primary SPI DPG/ Secondary SPI DPG
* pr_msb = 4 Most Signification Bytes of Preamble
* pr_lsb = 4 Least Significant Bytes of Preamble
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgInsertPreamble(int port_num, unsigned int pr_msb, unsigned int pr_lsb)
{
    unsigned int regVal;

    /* Set the DPG Mode register */
    if (port_num == 0) {
        /* Get the value of Header Mode field */
        regGet(redHawkRegs, CfgRegTxPSpiDPGMode, 0, &regVal);

        /* Set the SA Insert bit in the field */
        regVal = regVal | BIT_12;
        regSet(redHawkRegs, CfgRegTxPSpiDPGMode, 0, regVal);

        /* Set the Preamble MSB */
        regSet(redHawkRegs, CfgRegTxPSpiDPGPreambleH, 0, pr_msb);

        /* Set the Preamble LSB */
        regSet(redHawkRegs, CfgRegTxPSpiDPGPreambleL, 0, pr_lsb);

        /* Set the DPV to check the packets for Preamble */
        regGet(redHawkRegs, CfgRegTxPSpiDPVHdrCtrl, 0, &regVal);
        regVal = regVal | BIT_0;
        regSet(redHawkRegs, CfgRegTxPSpiDPVHdrCtrl, 0, regVal);
    } else {
        /* Get the value of Header Mode field */
        regGet(redHawkRegs, CfgRegTxSSpiDPGMode, 0, &regVal);

        /* Set the SA Insert bit in the field */
        regVal = regVal | BIT_12;
        regSet(redHawkRegs, CfgRegTxSSpiDPGMode, 0, regVal);

        /* Set the Preamble MSB */
        regSet(redHawkRegs, CfgRegTxSSpiDPGPreambleH, 0, pr_msb);

        /* Set the Preamble LSB */
        regSet(redHawkRegs, CfgRegTxSSpiDPGPreambleL, 0, pr_lsb);

        /* Set the DPV to check the packets for Preamble */
        regGet(redHawkRegs, CfgRegTxSSpiDPVHdrCtrl, 0, &regVal);
        regVal = regVal | BIT_0;
        regSet(redHawkRegs, CfgRegTxSSpiDPVHdrCtrl, 0, regVal);
    }
}

/******************************************************************
* rhAsicDpgInsertVlan - Configure DPG to insert Vlan in the packets generated.
*
* This routine configures the DPG to insert Vlan in the packets generated
* port_num = 0 / 1; Primary SPI DPG/ Secondary SPI DPG
* vlan_val = VLAN value that is inserted in the packets
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgInsertVlan(int port_num, unsigned int vlan_val)
{
    unsigned int regVal;

    /* Set the DPG Mode register */
    if (port_num == 0) {
        /* Get the value of Header Mode field */
        regGet(redHawkRegs, CfgRegTxPSpiDPGMode, 0, &regVal);

        /* Set the SA Insert bit in the field */
        regVal = regVal | BIT_15;
        regSet(redHawkRegs, CfgRegTxPSpiDPGMode, 0, regVal);

        /* Set the VLAN Value */
        regSet(redHawkRegs, CfgRegTxPSpiDPGPreambleH, 0, vlan_val);

        /* Set the DPV to check the packets for VLAN Insert */
        regGet(redHawkRegs, CfgRegTxPSpiDPVHdrCtrl, 0, &regVal);
        regVal = regVal | BIT_3;
        regSet(redHawkRegs, CfgRegTxPSpiDPVHdrCtrl, 0, regVal);
    } else {
        /* Get the value of Header Mode field */
        regGet(redHawkRegs, CfgRegTxSSpiDPGMode, 0, &regVal);

        /* Set the SA Insert bit in the field */
        regVal = regVal | BIT_15;
        regSet(redHawkRegs, CfgRegTxSSpiDPGMode, 0, regVal);

        /* Set the VLAN Value */
        regSet(redHawkRegs, CfgRegTxSSpiDPGVLanTag, 0, vlan_val);

        /* Set the DPV to check the packets for VLAN Insert */
        regGet(redHawkRegs, CfgRegTxSSpiDPVHdrCtrl, 0, &regVal);
        regVal = regVal | BIT_3;
        regSet(redHawkRegs, CfgRegTxSSpiDPVHdrCtrl, 0, regVal);
    }
}

/******************************************************************
* rhAsicDpgPortSetup - Initialize RedHawk ports and configure the loopbacks.
*
* This routine initializes the ports and configures the loopback accordingly
* port0 = 0 / 1 / -1  (XFI / XAUI / Configuration not required)
* port1 = 0 / 1 / -1  (XFI / XAUI / Configuration not required)
* lp_mode = 0 / 1     (Core Loopback / PCS Loopback for XFI ports)
*         = 0 / 1 / 2 (Core Loopback / PCS Loopback / PAD Loopback for XAUI ports)
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgPortSetup(int port0, int port1, int lp_mode)
{
    if (port0 == -1 && port1 == -1) {
        osPrintf("No port configuration specified\n");
        osPrintf("One of the port should be XFI or XAUI to be configured\n");
        return;
    }

    /* Do a Global Software Reset */
    regSet(redHawkRegs, VarRegCoGlobalSoftReset, 0, 1);

    /* Enable SPI Internal Loopback */
    regSet (redHawkRegs, CfgRegCoLoopbackMode, 0, 0xc0);

    if (port0 == 0) {
        /* Initialize XFI interface on the port 0 */
        rh_xfi_config (redHawkRegs, 0, 0);
        regSet(redHawkRegs, CfgRxControl__rxeq, 0, 0x7);
        regSet(redHawkRegs, CfgRxControl__rxphase, 0, 0x17);
    } else if (port0 == 1) {
        /* Initialize XAUI interface on the port 0 */
        rh_xaui_config (redHawkRegs, 0, 0);
    }

    if (port1 == 0) {
        /* Initialize XFI interface on the port 0 */
        rh_xfi_config (redHawkRegs, 1, 0);
        regSet(redHawkRegs, CfgRxControl__rxeq, 1, 0x7);
        regSet(redHawkRegs, CfgRxControl__rxphase, 1, 0x17);
    } else if (port1 == 1){
        /* Initialize XAUI interface on the port 1 */
        rh_xaui_config (redHawkRegs, 1, 0);
    }

    /* Disable primary SPI modules before cal programming */
    if (port0 != -1) {
        regSet (redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdeb);
        regSet (redHawkRegs, CfgRegTSpiCalSetup, 0, 0x0000001a);
        regSet (redHawkRegs, CfgRegRxpSpiCalSetup, 0, 0x0000001a);
        regSet (redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdff);

        regSet (redHawkRegs, CfgRegRxpSpiSetup__EnableStatus, 0, 1);
        regSet (redHawkRegs, CfgRegRxpSpiSetup__EnableTraining, 0, 1);
        regSet (redHawkRegs, CfgRegTSpiSetup__EnableDeskew, 0, 0);
        regSet (redHawkRegs, CfgRegTSpiSetup__EnableTraining, 0, 1);
        regSet (redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 0, 1);
    }

    if (port1 != -1) {
        regSet (redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdd7);
        regSet (redHawkRegs, CfgRegTxSSpiCalSetup, 0, 0x0000001a);
        regSet (redHawkRegs, CfgRegRxsSpiCalSetup, 0, 0x0000001a);
        regSet (redHawkRegs, VarRegCoFunctionActivate0, 0, 0xffbffdff);

        /* Internal loopback */
        regSet (redHawkRegs, CfgRegRxsSpiSetup__EnableStatus, 0, 1);
        regSet (redHawkRegs, CfgRegRxsSpiSetup__EnableTraining, 0, 1);
        regSet (redHawkRegs, CfgRegTxSSpiSetup__EnableDeskew, 0, 0);
        regSet (redHawkRegs, CfgRegTxSSpiSetup__EnableTraining, 0, 1);
        regSet (redHawkRegs, CfgTxMemMgrAEopErrPktDropDis, 1, 1);
    }

    if (port0 != -1)
        regSet (redHawkRegs, CfgDeqHeaderStripControl, 0, 0x00000001);
    if (port1 != -1)
        regSet (redHawkRegs, CfgDeqHeaderStripControl, 1, 0x00000001);

    /* XFI PCS Loopback for port 0 */
    if (port0 == 0) {
        if (lp_mode == 0) {
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP0, 0, 0);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP0, 0, 0);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP0, 0, 0);
            regSet (redHawkRegs, CfgRegCoXFISetup__Cfgrxlockref_xfi0, 0, 1);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP0, 0, 1);
            osDelay (2000);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP0, 0, 1);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP0, 0, 1);
            regSet (redHawkRegs, CfgTxControl__fwlpbena, 0, 1);

            /* Pulse XFI enables */
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP0, 0, 0);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP0, 0, 0);
            osDelay (1000);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP0, 0, 1);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP0, 0, 1);
            regSet (redHawkRegs, CfgRegCoXFISetup__Cfgrxlockref_xfi0, 0, 0);
        } else if (lp_mode == 1) {
            /* XFI PCS Loopback */
            regSet(redHawkRegs, CfgRegCoClockDiv0__MDIOClk, 0, 0xe);
            regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_6);
            rhAsicMdioWrite(0, 0, 0, 0x6040);
        }
    } else if (port0 == 1) {
        if (lp_mode == 0) {
            /* XAUI Core Loopback */
            regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfglpen_D_xaui0, 0, 1);
            regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfglpen_C_xaui0, 0, 1);
            regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfglpen_B_xaui0, 0, 1);
            regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfglpen_A_xaui0, 0, 1);
        } else if (lp_mode == 1) {
            /* XAUI PCS Loopback */
            regSet(redHawkRegs, CfgRegCoClockDiv0__MDIOClk, 0, 0x1f);
            regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_8);
            rhAsicMdioWrite(1, 0, 3, 0x6040);
        } else if (lp_mode == 2) {
            /* XAUI PAD Loopback */
            regSet(redHawkRegs, CfgRegCoClockDiv0__MDIOClk, 0, 0xe);
            regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_2);
            rhAsicMdioWrite(0, 32770, 3, 0xb218);
            rhAsicMdioWrite(0, 32771, 3, 0xb218);
            rhAsicMdioWrite(0, 32772, 3, 0xb218);
            rhAsicMdioWrite(0, 32773, 3, 0xb218);
        }
    }

    /* XFI PCS Loopback for port 1 */
    if (port1 == 0) {
        if (lp_mode == 0) {
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP1, 0, 0);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP1, 0, 0);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP1, 0, 0);
            regSet (redHawkRegs, CfgRegCoXFISetup__Cfgrxlockref_xfi1, 0, 1);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreVCOEnP1, 0, 1);
            osDelay (2000);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP1, 0, 1);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP1, 0, 1);
            regSet (redHawkRegs, CfgTxControl__fwlpbena, 1, 1);

            /* Pulse XFI enables */
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP1, 0, 0);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP1, 0, 0);
            osDelay (1000);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreTxEnP1, 0, 1);
            regSet (redHawkRegs, VarRegCoFunctionActivate1__VarXFICoreRxEnP1, 0, 1);
            regSet (redHawkRegs, CfgRegCoXFISetup__Cfgrxlockref_xfi1, 0, 0);
        } else if (lp_mode == 1) {
            /* XFI PCS Loopback */
            regSet(redHawkRegs, CfgRegCoClockDiv0__MDIOClk, 0, 0xe);
            regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_7);
            rhAsicMdioWrite(1, 0, 0, 0x6040);
        }
    } else if (port1 == 1) {
        if (lp_mode == 0) {
            /* XAUI Core Loopback */
            regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfglpen_D_xaui1, 0, 1);
            regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfglpen_C_xaui1, 0, 1);
            regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfglpen_B_xaui1, 0, 1);
            regSet (redHawkRegs, CfgRegCoXAUISetup1__Cfglpen_A_xaui1, 0, 1);
        } else if (lp_mode == 1) {
            /* XAUI PCS Loopback */
            regSet(redHawkRegs, CfgRegCoClockDiv0__MDIOClk, 0, 0x1f);
            regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_8);
            rhAsicMdioWrite(2, 0, 3, 0x6040);
        } else if (lp_mode == 2) {
            /* XAUI PAD Loopback */
            regSet(redHawkRegs, CfgRegCoClockDiv0__MDIOClk, 0, 0xe);
            regSet(redHawkRegs, CfgRegCoMDIOMode, 0, BIT_3);
            rhAsicMdioWrite(1, 32770, 3, 0xb218);
            rhAsicMdioWrite(1, 32771, 3, 0xb218);
            rhAsicMdioWrite(1, 32772, 3, 0xb218);
            rhAsicMdioWrite(1, 32773, 3, 0xb218);
        }
    }

    osDelay (2000);

    /* Configuring other modules for port 0 */
    if (port0 != -1) {
        regSet (redHawkRegs, CfgFilters, 0, 0x00005000);
        regSet (redHawkRegs, CfgRegTxMaxFSize, 0, 0x00003a98);
        regSet (redHawkRegs, CfgMaxFrmSize, 0, 0x00003a98);
        regSet (redHawkRegs, CfgMinFrmSize, 0, 0x00000021);
        regSet (redHawkRegs, CfgTxMemMgrMaxPktSzPrt0, 0, 0x00003a98);

        regSet (redHawkRegs, CfgRegTxMACModes, 0, 0x00000006);
        regSet (redHawkRegs, CfgRegRxMACModes, 0, 0x00d05f37);
    }

    /* Configuring other modules for port 0 */
    if (port1 != -1) {
        regSet (redHawkRegs, CfgFilters, 1, 0x00005000);
        regSet (redHawkRegs, CfgRegTxMaxFSize, 1, 0x00003a98);
        regSet (redHawkRegs, CfgMaxFrmSize, 1, 0x00003a98);
        regSet (redHawkRegs, CfgMinFrmSize, 1, 0x00000021);
        regSet (redHawkRegs, CfgTxMemMgrMaxPktSzPrt1, 0, 0x00003a98);

        regSet (redHawkRegs, CfgRegTxMACModes, 1, 0x00000006);
        regSet (redHawkRegs, CfgRegRxMACModes, 1, 0x00d05f37);
    }

    osDelay(5000); /* Waiting for DPG to complete transmission */
}

/******************************************************************
* rhAsicStartDpg - Initialize DPG to pump traffic.
*
* This routine initializes the DPG and DPV. The DPG pumps the traffic and the
* packets transmitted are configured by the user using the DPG configuration
* functions provided. The DPV verifies the received packets and updates the
* statistics accordingly and these statistics are printed accordingly.
* port0 = 0/1 -- Disable/Enable
* port1 = 0/1 -- Disable/Enable
*
* RETURNS: Returns OK status on success.
*/
void rhAsicStartDpg(int port0, int port1)
{
    unsigned int regVal, lo_bit, hi_bit, regMask;
    unsigned int expd_pkt_cnt, rcvd_pkt_cnt;

    /* Port 0 DPG */
    if (port0 == 1) {
        /* Disable the DPV and DPG */
        regSet(redHawkRegs, VarRegTxPSpiDPVEnable, 0, 0);
        regSet(redHawkRegs, VarRegTxPSpiDPGEnable, 0, 0);

        printf("DPG Configuration for port 0\n");

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGMode, 0, &regVal);
        printf("    CfgRegTxPSpiDPGMode : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGCRCValue, 0, &regVal);
        printf("    CfgRegTxPSpiDPGCRCValue : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGPacketFixed, 0, &regVal);
        printf("    CfgRegTxPSpiDPGPacketFixed : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGPacketNumber, 0, &regVal);
        printf("    CfgRegTxPSpiDPGPacketNumber : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGGap, 0, &regVal);
        printf("    CfgRegTxPSpiDPGGap : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGPatternFixed, 0, &regVal);
        printf("    CfgRegTxPSpiDPGPatternFixed : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiPrbsSeed, 0, &regVal);
        printf("    CfgRegTxPSpiPrbsSeed : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGSrcL, 0, &regVal);
        printf("    CfgRegTxPSpiDPGSrcL : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGSrcH, 0, &regVal);
        printf("    CfgRegTxPSpiDPGSrcH : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGDestL, 0, &regVal);
        printf("    CfgRegTxPSpiDPGDestL : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGDestH, 0, &regVal);
        printf("    CfgRegTxPSpiDPGDestH : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGVLanTag, 0, &regVal);
        printf("    CfgRegTxPSpiDPGVLanTag : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGPreambleL, 0, &regVal);
        printf("    CfgRegTxPSpiDPGPreambleL : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxPSpiDPGPreambleH, 0, &regVal);
        printf("    CfgRegTxPSpiDPGPreambleH : 0x%.8X\n", regVal);
    }

    /* Port 1 DPG */
    if(port1 == 1) {
        /* Disable the DPV and DPG */
        regSet(redHawkRegs, VarRegTxSSpiDPVEnable, 0, 0);
        regSet(redHawkRegs, VarRegTxSSpiDPGEnable, 0, 0);

        printf("DPG Configuration for port 0\n");

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGMode, 0, &regVal);
        printf("    CfgRegTxSSpiDPGMode : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGCRCValue, 0, &regVal);
        printf("    CfgRegTxSSpiDPGCRCValue : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGPacketFixed, 0, &regVal);
        printf("    CfgRegTxSSpiDPGPacketFixed : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGPacketNumber, 0, &regVal);
        printf("    CfgRegTxSSpiDPGPacketNumber : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGGap, 0, &regVal);
        printf("    CfgRegTxSSpiDPGGap : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGPatternFixed, 0, &regVal);
        printf("    CfgRegTxSSpiDPGPatternFixed : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiPrbsSeed, 0, &regVal);
        printf("    CfgRegTxSSpiPrbsSeed : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGSrcL, 0, &regVal);
        printf("    CfgRegTxSSpiDPGSrcL : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGSrcH, 0, &regVal);
        printf("    CfgRegTxSSpiDPGSrcH : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGDestL, 0, &regVal);
        printf("    CfgRegTxSSpiDPGDestL : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGDestH, 0, &regVal);
        printf("    CfgRegTxSSpiDPGDestH : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGVLanTag, 0, &regVal);
        printf("    CfgRegTxSSpiDPGVLanTag : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGPreambleL, 0, &regVal);
        printf("    CfgRegTxSSpiDPGPreambleL : 0x%.8X\n", regVal);

        regVal = 0;
        regGet(redHawkRegs, CfgRegTxSSpiDPGPreambleH, 0, &regVal);
        printf("    CfgRegTxSSpiDPGPreambleH : 0x%.8X\n", regVal);
    }

    /* Enabling the DPG on Port 0 */
    if (port0 == 1) {
        /* Enable the DPV and DPG */
        regSet(redHawkRegs, VarRegTxPSpiDPVEnable, 0, 1);
        regSet(redHawkRegs, VarRegTxPSpiDPGEnable, 0, 1);

        /* Induce a delay of 10 sec */
        osPrintf("DPG Transmitting packets for port 0.....\n");
    }

    /* Enabling the DPG on Port 1 */
    if (port1 == 1) {
        /* Enable the DPV and DPG */
        regSet(redHawkRegs, VarRegTxSSpiDPVEnable, 0, 1);
        regSet(redHawkRegs, VarRegTxSSpiDPGEnable, 0, 1);

        /* Induce a delay of 10 sec */
        osPrintf("DPG Transmitting packets for port 1......\n");
    }

    /* Waiting for the DPG traffic to get done and printing the status on Port 0 */
    if (port0 == 1) {
        osDelay(10000);

        /* Now check for the status of DPG */
        regGet(redHawkRegs, StsTxPSpiDPGStatus, 0, &regVal);
        while (regVal == 0) {
            osDelay(5000);
            regGet(redHawkRegs, StsTxPSpiDPGStatus, 0, &regVal);
        }

        /* Check for the Error in DPG configuration */
        if (regVal == BIT_1) {
            printf("DPG TEST : ERROR IN DPG CONFIGURATION for port 0\n");
        } else if (regVal == BIT_0) {
            /* DPG done */
            /* Check for the DPV Status */
            osDelay(5000); /* Wait for 10 seconds */

            osPrintf("Reading DPV status registers for port 0\n");

            regVal = 0;
            regGet(redHawkRegs, StsTxPSpiDPVErrorCnt, 0, &regVal);
            printf("    StsTxPSpiDPVErrorCnt : 0x%.8X\n", regVal);

            regVal = 0;
            regGet(redHawkRegs, StsTxPSpiDPVCRCErrorCnt, 0, &regVal);
            printf("    StsTxPSpiDPVCRCErrorCnt : 0x%.8X\n", regVal);

            regVal = 0;
            regGet(redHawkRegs, StsTxPSpiDPVGoodPktCnt, 0, &regVal);
            printf("    StsTxPSpiDPVGoodPktCnt : 0x%.8X\n", regVal);
            rcvd_pkt_cnt = regVal;

            regVal = 0;
            regGet(redHawkRegs, StsTxPSpiDPVSyncOnCnt, 0, &regVal);
            printf("    StsTxPSpiDPVSyncOnCnt : 0x%.8X\n", regVal);

            regVal = 0;
            regGet(redHawkRegs, StsTxPSpiDPVEopCnt, 0, &regVal);
            printf("    StsTxPSpiDPVEopCnt : 0x%.8X\n", regVal);

            /* Check the status and print the output */
            regGet(redHawkRegs, CfgRegTxPSpiDPGMode__PortId, 0, &regVal);
            lo_bit = redHawkRegs[CfgRegTxPSpiDPGMode__PortId].loBit;
            hi_bit = redHawkRegs[CfgRegTxPSpiDPGMode__PortId].hiBit;
            regMask = buildMask(hi_bit, lo_bit);
            regVal = regVal & regMask;
            regVal = regVal >> lo_bit;
            if (regVal == 0) {
                regGet (redHawkRegs, StsTxPSpiEopCountCh0, 0, &expd_pkt_cnt);
            } else if (regVal == 1) {
                regGet (redHawkRegs, StsTxPSpiEopCountCh1, 0, &expd_pkt_cnt);
            } else if (regVal == 2) {
                regGet (redHawkRegs, StsTxPSpiEopCountCh2, 0, &expd_pkt_cnt);
            }
            if ((rcvd_pkt_cnt == expd_pkt_cnt) || (rcvd_pkt_cnt == (expd_pkt_cnt - 1))) {
                osPrintf("Test PASS\n");
            } else {
                osPrintf("EOP Count Expected 0x%X but Received 0x%X\n", expd_pkt_cnt, rcvd_pkt_cnt);
                osPrintf("Test FAIL\n");
            }
        }
    }

    /* Waiting for the DPG traffic to get done and printing the status on Port 1 */
    if (port1 == 1) {
        if (port0 != 1)
            osDelay(10000);

        /* Now check for the status of DPG */
        regGet(redHawkRegs, StsTxSSpiDPGStatus, 0, &regVal);
        while (regVal == 0) {
            osDelay(10000);
            regGet(redHawkRegs, StsTxSSpiDPGStatus, 0, &regVal);
        }

        /* Check for the Error in DPG configuration */
        if (regVal == BIT_1) {
            printf("DPG TEST : ERROR IN DPG CONFIGURATION for port 1\n");
        } else if (regVal == BIT_0) {
            /* DPG done */
            /* Check for the DPV Status */
            osDelay(5000); /* Wait for 10 seconds */

            osPrintf("Reading DPV status registers for port 1\n");

            regVal = 0;
            regGet(redHawkRegs, StsTxSSpiDPVErrorCnt, 0, &regVal);
            printf("    StsTxSSpiDPVErrorCnt : 0x%.8X\n", regVal);

            regVal = 0;
            regGet(redHawkRegs, StsTxSSpiDPVCRCErrorCnt, 0, &regVal);
            printf("    StsTxSSpiDPVCRCErrorCnt : 0x%.8X\n", regVal);

            regVal = 0;
            regGet(redHawkRegs, StsTxSSpiDPVGoodPktCnt, 0, &regVal);
            printf("    StsTxSSpiDPVGoodPktCnt : 0x%.8X\n", regVal);
            rcvd_pkt_cnt = regVal;

            regVal = 0;
            regGet(redHawkRegs, StsTxSSpiDPVSyncOnCnt, 0, &regVal);
            printf("    StsTxSSpiDPVSyncOnCnt : 0x%.8X\n", regVal);

            regVal = 0;
            regGet(redHawkRegs, StsTxSSpiDPVEopCnt, 0, &regVal);
            printf("    StsTxSSpiDPVEopCnt : 0x%.8X\n", regVal);

            /* Check the status and print the output */
            regGet(redHawkRegs, CfgRegTxSSpiDPGMode__PortId, 0, &regVal);
            lo_bit = redHawkRegs[CfgRegTxSSpiDPGMode__PortId].loBit;
            hi_bit = redHawkRegs[CfgRegTxSSpiDPGMode__PortId].hiBit;
            regMask = buildMask(hi_bit, lo_bit);
            regVal = regVal & regMask;
            regVal = regVal >> lo_bit;
            if (regVal == 0) {
                regGet (redHawkRegs, StsTxSSpiEopCountCh0, 0, &expd_pkt_cnt);
            } else if (regVal == 1) {
                regGet (redHawkRegs, StsTxSSpiEopCountCh1, 0, &expd_pkt_cnt);
            } else if (regVal == 2) {
                regGet (redHawkRegs, StsTxSSpiEopCountCh2, 0, &expd_pkt_cnt);
            }
            if ((rcvd_pkt_cnt == expd_pkt_cnt) || (rcvd_pkt_cnt == (expd_pkt_cnt - 1))) {
                osPrintf("Test PASS\n");
            } else {
                osPrintf("EOP Count Expected 0x%X but Received 0x%X\n", expd_pkt_cnt, rcvd_pkt_cnt);
                osPrintf("Test FAIL\n");
            }
        }
    }

    /* Disabling both DPG's/DPV's */
    regSet(redHawkRegs, VarRegTxPSpiDPVEnable, 0, 0);
    regSet(redHawkRegs, VarRegTxPSpiDPGEnable, 0, 0);
    regSet(redHawkRegs, VarRegTxSSpiDPVEnable, 0, 0);
    regSet(redHawkRegs, VarRegTxSSpiDPGEnable, 0, 0);
}

/******************************************************************
* rhAsicDpgSetDefault - Configure the DPG registers to default values
*
* This routine configures all the registers of DPG to their default values.
* port_num = 0 / 1(Primary DPG / Secondary DPG)
*
* RETURNS: Returns OK status on success.
*/
void rhAsicDpgSetDefault(int port_num)
{
    /* Check for the SPI */
    if (port_num == 0) {
        /* Primary SPI
           Set all the configuration registers to their respective default
           values */
        regSet(redHawkRegs, CfgRegTxPSpiDPGMode, 0, 0);
        regSet(redHawkRegs, CfgRegTxPSpiDPGCRCValue, 0, 0);
        regSet(redHawkRegs, CfgRegTxPSpiDPGPacketFixed, 0, 0x40);
        regSet(redHawkRegs, CfgRegTxPSpiDPGPacketNumber, 0, 0x0a);
        regSet(redHawkRegs, CfgRegTxPSpiDPGGap, 0, 0x10);
        regSet(redHawkRegs, CfgRegTxPSpiDPGPatternFixed, 0, 0xaaaa);
        regSet(redHawkRegs, CfgRegTxPSpiDPGSrcL, 0, 0);
        regSet(redHawkRegs, CfgRegTxPSpiDPGSrcH, 0, 0);
        regSet(redHawkRegs, CfgRegTxPSpiDPGDestL, 0, 0);
        regSet(redHawkRegs, CfgRegTxPSpiDPGDestH, 0, 0);
        regSet(redHawkRegs, CfgRegTxPSpiDPGVLanTag, 0, 0);
        regSet(redHawkRegs, CfgRegTxPSpiDPGPreambleL, 0, 0);
        regSet(redHawkRegs, CfgRegTxPSpiDPGPreambleH, 0, 0);
    } else {
        /* Secondary SPI
           Set all the configuration registers to their respective default
           values */
        regSet(redHawkRegs, CfgRegTxSSpiDPGMode, 0, 0);
        regSet(redHawkRegs, CfgRegTxSSpiDPGCRCValue, 0, 0);
        regSet(redHawkRegs, CfgRegTxSSpiDPGPacketFixed, 0, 0x40);
        regSet(redHawkRegs, CfgRegTxSSpiDPGPacketNumber, 0, 0x0a);
        regSet(redHawkRegs, CfgRegTxSSpiDPGGap, 0, 0x10);
        regSet(redHawkRegs, CfgRegTxSSpiDPGPatternFixed, 0, 0xaaaa);
        regSet(redHawkRegs, CfgRegTxSSpiDPGSrcL, 0, 0);
        regSet(redHawkRegs, CfgRegTxSSpiDPGSrcH, 0, 0);
        regSet(redHawkRegs, CfgRegTxSSpiDPGDestL, 0, 0);
        regSet(redHawkRegs, CfgRegTxSSpiDPGDestH, 0, 0);
        regSet(redHawkRegs, CfgRegTxSSpiDPGVLanTag, 0, 0);
        regSet(redHawkRegs, CfgRegTxSSpiDPGPreambleL, 0, 0);
        regSet(redHawkRegs, CfgRegTxSSpiDPGPreambleH, 0, 0);
    }
}
