/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Boot support
 */
#include <common.h>
#include <command.h>
#include <net.h>
#include <octeon_boot.h>

#if (CONFIG_COMMANDS & CFG_CMD_NET)


/* The network loading changes the global load address, which we don't want to do,
** so create a new variable for the networking to use */
uint32_t net_load_addr;  

extern int autoscript_enable;
extern int do_bootm (cmd_tbl_t *, int, int, char *[]);

static int netboot_common (int, cmd_tbl_t *, int , char *[]);

#if ENABLE_BOOTP_AND_RARP
int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	return netboot_common (BOOTP, cmdtp, argc, argv);
}

U_BOOT_CMD(
	bootp,	3,	1,	do_bootp,
	"bootp   - boot image via network using BootP/TFTP protocol\n",
	"[loadAddress] [bootfilename]\n"
);
#endif

int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    int retval = netboot_common (TFTP, cmdtp, argc, argv);
    octeon_check_mem_load_range();
    return retval;
}

U_BOOT_CMD(
	tftpboot,	3,	1,	do_tftpb,
	"tftpboot- boot image via network using TFTP protocol\n",
	"[loadAddress] [bootfilename]\n"
	"If loadAddress is 0, then file will be loaded to the default load address\n"
);

#if ENABLE_BOOTP_AND_RARP
int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	return netboot_common (RARP, cmdtp, argc, argv);
}

U_BOOT_CMD(
	rarpboot,	3,	1,	do_rarpb,
	"rarpboot- boot image via network using RARP/TFTP protocol\n",
	"[loadAddress] [bootfilename]\n"
);
#endif

#if (CONFIG_COMMANDS & CFG_CMD_DHCP)
int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	return netboot_common(DHCP, cmdtp, argc, argv);
}

U_BOOT_CMD(
	dhcp,	3,	1,	do_dhcp,
	"dhcp    - invoke DHCP client to obtain IP/boot params\n",
	"\n"
);
#endif	/* CFG_CMD_DHCP */

#if defined(CONFIG_OCTEON_GEF_BOARD_GENERAL) || defined(CONFIG_OCTEON_GEF_56XX_BOARD_GENERAL) || defined(CONFIG_OCTEON_GEF_63XX_BOARD_GENERAL)
        #include "octeon_boot.h"
typedef enum
{
    PORT_RGMII = 1,
    PORT_GMII,
    PORT_MII,
    PORT_SPI4000
} port_types;
typedef struct
{
    uint32_t port;
    uint32_t interface;
    uint32_t queue;
    uint32_t port_type;
    uint32_t initted_flag;
    uint32_t link_speed:2;   /* current link status, use to reconfigure on status changes */
    uint32_t link_duplex:1;
    uint32_t link_status:1;
} octeon_eth_info_t;
extern struct eth_device *eth_current;
int do_netintstat (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    const char *link_duplex;
    const char *link_speed;
    const char *link_status;
    octeon_eth_info_t* priv;
    int interface;
    int index;
    cvmx_gmxx_rxx_rx_inbnd_t link;
    struct eth_device* current;

    if (!eth_current)
        return 0;
    current = eth_current;
    do
    {
#if defined(CONFIG_OCTEON_TNPA3804) || defined(CONFIG_OCTEON_AT5810) || defined(CONFIG_OCTEON_TNPA5804)
        if (strncmp("e1000#0", current->name, 7) == 0)
        {
            switch (current->link_status)
            {
            case LINK_STATUS_UNKNOWN:
                printf("e1000#0: Down\n");
                break;
            case LINK_STATUS_ERROR:
                printf("e1000#0: Error\n");
                break;
            case LINK_STATUS_DOWN:
                printf("e1000#0: Down\n");
                break;
            case LINK_STATUS_UP:
                printf("e1000#0: Up\n");
                break;
            default:
                printf("e1000#0: ???\n");
                break;
            }
        }
        else if (strncmp("e1000#1", current->name, 7) == 0)
        {
            switch (current->link_status)
            {
            case LINK_STATUS_UNKNOWN:
                printf("e1000#1: Down\n");
                break;
            case LINK_STATUS_ERROR:
                printf("e1000#1: Error\n");
                break;
            case LINK_STATUS_DOWN:
                printf("e1000#1: Down\n");
                break;
            case LINK_STATUS_UP:
                printf("e1000#1: Up\n");
                break;
            default:
                printf("e1000#1: ???\n");
                break;
            }
        }
        else
#endif
        {
            priv = (octeon_eth_info_t*)current->priv;
            interface = priv->interface;
            index = priv->port - 16 * interface;
            link.u64 = cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));

            if (priv->port_type == PORT_GMII)
            {
                /* GMII only supports full duplex gigabit */
                link.s.speed = 2;
                link.s.duplex = 1;
                link.s.status = 1;
            }

            if (link.s.duplex)
                link_duplex = "Full";
            else
                link_duplex = "Half";

            if (link.s.speed == 0)
            {
                link_speed = " 10Mbs";
            }
            else if (link.s.speed == 1)
            {
                link_speed = "100Mbs";
            }
            else if (link.s.speed == 2)
            {
                link_speed = "  1Gbs";
            }
            else
            {
                link_speed = " Rsrvd";
            }

            if (link.s.status)
            {
                link_status = "Up  ";
            }
            else
            {
                link_status = "Down";
            }
            printf("%s: %s %s %s duplex, (port %2d)\n",
                   current->name, link_status, link_speed, link_duplex, 16*interface + index);
        }
        current = current->next;
    }
    while (current != eth_current);

    return 0;
}

        #ifdef OBSOLETE
U_BOOT_CMD(
          netintstat, 1,  1,  do_netintstat,
          "netintstat    - obtain network interface status\n",
          "\n"
          );
        #endif

        #include "cvmx-helper.h"
int do_regdump (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    int interface = cvmx_helper_get_interface_num(19);
    int index = cvmx_helper_get_interface_index_num(19);
    cvmx_pcsx_miscx_ctl_reg_t mode_type;
    cvmx_pcsx_anx_results_reg_t inband_status;
    cvmx_pcsx_mrx_status_reg_t mrx_status;
    cvmx_pcsx_anx_adv_reg_t anxx_adv;

    int i;
    for (i=0;i<10;i++)
    {


        anxx_adv.u64 = cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface));
        mrx_status.u64 = cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG(index, interface));

        mode_type.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));

        /* Read Octeon's inband status */
        inband_status.u64 = cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG(index, interface));

        printf("cvmx_pcsx_mrx_status_reg_t:0x%x\n",mrx_status.u64); 
        printf("cvmx_pcsx_miscx_ctl_reg_t:0x%x\n",mode_type.u64); 
        printf("cvmx_pcsx_anx_results_reg_t:0x%x\n",inband_status.u64); 
        printf("cvmx_pcsx_anxx_adv_reg_t:0x%x\n",anxx_adv.u64);
    }

    return 0;
}
U_BOOT_CMD(
          regdump,    1,  1,  do_regdump,
          "regdump    - obtain network interface status\n",
          "\n"
          );



extern struct eth_device *eth_devices;

        #if defined(CONFIG_OCTEON_TNPA3804) || defined(CONFIG_OCTEON_AT5810) || defined(CONFIG_OCTEON_TNPA5804)
extern int e1000_eeprom_init(struct eth_device *, uint16_t, uint16_t, uint16_t *);
extern uint16_t e1000_eeprom_82546gb_defaults[];

int do_inite1000eeprom (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    struct eth_device *d;

    for (d=eth_devices; d->next!=eth_devices; d=d->next)
    {
        if ((d->name[0] == 'e') && (d->name[1] == '1') && (d->name[2] == '0') &&
            (d->name[3] == '0') && (d->name[4] == '0'))
        {
            e1000_eeprom_init(d, 0, 0x003F, &e1000_eeprom_82546gb_defaults[0]);
        }
    }

    return 0;
}

U_BOOT_CMD(
          inite1000eeprom,    1,  1,  do_inite1000eeprom,
          "inite1000eeprom    - initialize the e1000 EEPROM with defaults\n",
          "\n"
          );

extern int e1000_read_eeprom(/* struct e1000_hw */ void *, uint16_t, uint16_t *);

int do_displaye1000eeprom (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    struct eth_device *d;
    struct e1000_hw *hw;
    uint16_t i, eeprom_data;

    for (d=eth_devices; d->next!=eth_devices; d=d->next)
    {
        if ((d->name[0] == 'e') && (d->name[1] == '1') && (d->name[2] == '0') &&
            (d->name[3] == '0') && (d->name[4] == '0'))
        {
            hw = d->priv;
            for (i = 0; i < (0x003F + 1); i++)
            {
                if (e1000_read_eeprom(hw, i, &eeprom_data) < 0)
                {
                    printf ("\nEEPROM Read Error");
                    break;
                }
                if ((i % 8) == 0)
                {
                    printf ("\n0x%04x: ", i);
                }
                printf ("%04x ", eeprom_data);
            }
            printf ("\n\n");
            break;
        }
    }

    return 0;
}

U_BOOT_CMD(
          displaye1000eeprom, 1,  1,  do_displaye1000eeprom,
          "displaye1000eeprom    - display the e1000 EEPROM contents\n",
          "\n"
          );

int do_checksume1000eeprom (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    struct eth_device *d;
    struct e1000_hw *hw;
    uint16_t i, eeprom_data, checksum = 0;

    for (d=eth_devices; d->next!=eth_devices; d=d->next)
    {
        if ((d->name[0] == 'e') && (d->name[1] == '1') && (d->name[2] == '0') &&
            (d->name[3] == '0') && (d->name[4] == '0'))
        {
            hw = d->priv;
            for (i = 0; i < (0x003F + 1); i++)
            {
                if (e1000_read_eeprom(hw, i, &eeprom_data) < 0)
                {
                    printf ("\nEEPROM Read Error");
                    break;
                }
                checksum += eeprom_data;
            }
            break;
        }
    }
    if (checksum == 0xBABA)
    {
        printf ("\nThe e1000 checksum is valid (0xBABA sum)\n\n");
    }
    else
    {
        printf ("\nThe e1000 checksum is NOT valid (0x%04x sum)\n\n", checksum);
    }

    return 0;
}

U_BOOT_CMD(
          checksum1000eeprom, 1,  1,  do_checksume1000eeprom,
          "checksume1000eeprom    - checksum the e1000 EEPROM contents\n",
          "\n"
          );
        #endif

    #endif // CONFIG_OCTEON_TNPA3804 || CONFIG_OCTEON_AT5810 || CONFIG_OCTEON_TNPA5804

#if (CONFIG_COMMANDS & CFG_CMD_NFS)
int do_nfs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	return netboot_common(NFS, cmdtp, argc, argv);
}

U_BOOT_CMD(
	nfs,	3,	1,	do_nfs,
	"nfs    - boot image via network using NFS protocol\n",
	"[loadAddress] [host ip addr:bootfilename]\n"
);
#endif	/* CFG_CMD_NFS */

static void netboot_update_env (void)
{
	char tmp[22];

	if (NetOurGatewayIP) {
		ip_to_string (NetOurGatewayIP, tmp);
		setenv ("gatewayip", tmp);
	}

	if (NetOurSubnetMask) {
		ip_to_string (NetOurSubnetMask, tmp);
		setenv ("netmask", tmp);
	}

	if (NetOurHostName[0])
		setenv ("hostname", NetOurHostName);

	if (NetOurRootPath[0])
		setenv ("rootpath", NetOurRootPath);

	if (NetOurIP) {
		ip_to_string (NetOurIP, tmp);
		setenv ("ipaddr", tmp);
	}

#if defined(CONFIG_OCTEON_GEF_BOARD_GENERAL) || defined(CONFIG_OCTEON_GEF_56XX_BOARD_GENERAL) || defined(CONFIG_OCTEON_GEF_63XX_BOARD_GENERAL)
    if (!getenv("serverip"))
    {
        if (NetServerIP)
        {
            ip_to_string (NetServerIP, tmp);
            setenv ("serverip", tmp);
        }
    }
#else
    if (NetServerIP)
	{
		ip_to_string (NetServerIP, tmp);
		setenv ("serverip", tmp);
	}
#endif

	if (NetOurDNSIP) {
		ip_to_string (NetOurDNSIP, tmp);
		setenv ("dnsip", tmp);
	}
#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
	if (NetOurDNS2IP) {
		ip_to_string (NetOurDNS2IP, tmp);
		setenv ("dnsip2", tmp);
	}
#endif
	if (NetOurNISDomain[0])
		setenv ("domain", NetOurNISDomain);
}

static int
netboot_common (int proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
{
	int   rcode = 0;
	int   size;
        uint32_t addr = 0;

	switch (argc) {
	case 1:
		break;

	case 2:	/* only one arg - accept two forms:
		 * just load address, or just boot file name.
		 * The latter form must be written "filename" here.
		 */
		if (argv[1][0] == '"') {	/* just boot filename */
			copy_filename (BootFile, argv[1], sizeof(BootFile));
		} else {			/* load address	*/
			addr = simple_strtoul(argv[1], NULL, 16);
		}
		break;

	case 3:	
                addr = simple_strtoul(argv[1], NULL, 16);
		copy_filename (BootFile, argv[2], sizeof(BootFile));

		break;

	default: printf ("Usage:\n%s\n", cmdtp->usage);
		return 1;
	}
        /* use default loadaddr address is 0 */
        if (!addr)
            addr = load_addr;

        /* Set network global load address */
        net_load_addr = addr;
	if ((size = NetLoop(proto)) < 0)
		return 1;

	/* NetLoop ok, update environment */
	netboot_update_env();

	/* done if no file was loaded (no errors though) */
	if (size == 0)
		return 0;

	/* flush cache */
	flush_cache(addr, size);

#ifdef CONFIG_CMD_BOOTM
	/* Loading ok, check if we should attempt an auto-start */
	if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
		char *local_args[2];
		local_args[0] = argv[0];
		local_args[1] = NULL;

		printf ("Automatic boot of image at addr 0x%08lX ...\n",
			addr);
		rcode = do_bootm (cmdtp, 0, 1, local_args);
	}
#endif /* CONFIG_CMD_BOOTM */

#ifdef CONFIG_AUTOSCRIPT
#ifndef CONFIG_CMD_BOOTM
    /* if CONFIG_CMD_BOOTM is defined above then s is already defined */
    char *s;
#endif

    if ( autoscript_enable )
    {
        autoscript_enable = 0;
        if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0))
        {
            printf("Running autoscript at addr 0x%08lX ...\n", addr);
            rcode = autoscript (addr);

        }
    }
#endif
	return rcode;
}

#if (CONFIG_COMMANDS & CFG_CMD_PING)
int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	if (argc < 2)
		return -1;

	NetPingIP = string_to_ip(argv[1]);
	if (NetPingIP == 0) {
		printf ("Usage:\n%s\n", cmdtp->usage);
		return -1;
	}

	if (NetLoop(PING) < 0) {
		printf("ping failed; host %s is not alive\n", argv[1]);
		return 1;
	}

	printf("host %s is alive\n", argv[1]);

	return 0;
}

U_BOOT_CMD(
	ping,	2,	1,	do_ping,
	"ping    - send ICMP ECHO_REQUEST to network host\n",
	"pingAddress\n"
);
#endif	/* CFG_CMD_PING */

#if (CONFIG_COMMANDS & CFG_CMD_CDP)

static void cdp_update_env(void)
{
	char tmp[16];

	if (CDPApplianceVLAN != htons(-1)) {
		printf("CDP offered appliance VLAN %d\n", ntohs(CDPApplianceVLAN));
		VLAN_to_string(CDPApplianceVLAN, tmp);
		setenv("vlan", tmp);
		NetOurVLAN = CDPApplianceVLAN;
	}

	if (CDPNativeVLAN != htons(-1)) {
		printf("CDP offered native VLAN %d\n", ntohs(CDPNativeVLAN));
		VLAN_to_string(CDPNativeVLAN, tmp);
		setenv("nvlan", tmp);
		NetOurNativeVLAN = CDPNativeVLAN;
	}

}

int do_cdp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	int r;

	r = NetLoop(CDP);
	if (r < 0) {
		printf("cdp failed; perhaps not a CISCO switch?\n");
		return 1;
	}

	cdp_update_env();

	return 0;
}

U_BOOT_CMD(
	cdp,	1,	1,	do_cdp,
	"cdp     - Perform CDP network configuration\n",
);
#endif	/* CFG_CMD_CDP */

extern int miiphy_write(unsigned char, unsigned char, unsigned short);
extern int miiphy_read(unsigned char, unsigned char, unsigned short *);

int do_phy_reg_access(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    uint16_t val;
    uint8_t addr;
    int i,j;
    uint32_t reg;

#if defined(IS_10G_PHY_PRESENT)
    if (IS_10G_PHY_PRESENT)
    {
        printf("ERROR: This feature only supported on 1G PHYs\n");
    }
    else
#endif
    {
		if (argc < 2 || (argc == 2 && argv[1][0] == '0'))
        {
            addr = 0x40;//phy0
    
            for (i = addr; i <= 0x43;i++)
            {
                printf("****** PHY addr:%x ******\n", i);
                for (j = 0; j <= 31; j++)
                {
                    /* read the current value out of the register on the MDIO interface */
                    miiphy_read (i, j, &val);
                    printf("reg:%d, val:0x%02x\n", j, val);
                }
            }
    
        }
    
        /* get phy address (usually 0x40-0x43) */
        addr = simple_strtoul(argv[2], NULL, 10);
    
        /* get phy register number*/
        reg = simple_strtoul(argv[3], NULL, 10);
    
        miiphy_read (addr, reg, &val);
    
        printf("READ: PHY:%x  Reg:%x:	0x%08x\n",addr, reg, val);
    
        if (argv[1][0] == 'w')//read
        {
            /* get value to write to phy reg */
            val = simple_strtoul(argv[4], NULL, 10);
    
            miiphy_write (addr, reg, val);
    
            printf("WRITE: PHY:%x  Reg:%x:	0x%08x\n",addr, reg, val);
        }
          
    #if defined(BOARD_PHY_INTERRUPT_REG)
    
        printf("BOARD_PHY_INTERRUPT_REG:%02x\n", *BOARD_PHY_INTERRUPT_REG);
    #endif
    }
    return 0;
}

U_BOOT_CMD(
          phy,    5,  1,  do_phy_reg_access,
          "phy     - phy <flag> <phy addr> <phy reg> <value>; i.e. phy w 0x40 17 0x1234 or phy r 0x40 17\n",
          );

#define PCS1_MR0_CONTROL_REG 	0x11800B8001000ull 
#define PCS1_MISC0_CONTROL_REG	0x11800B8001078ull
#define PCSX_CONTROL1_REG		0x11800B8000800ull

int do_phy_loopback (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    uint16_t val;
    int i,j;
    uint64_t data; 


    i = j = 0;

    if (argc < 3)
    {
        return -1;
    }
    if (argc == 3)
    {
        switch (argv[1][0])
        {
        case '0':
            i = 0x40;
            break;
        case '1':
            i = 0x41;
            break;
        case '2':
            i = 0x42;
            break;
        case '3':
            i = 0x43;
            break;
        default:
            i = 0x40;
        }

        if (argv[2][0] == 'm' || argv[2][0] == 'M')
        {
            j = 0; //register 0
        }
        else if (argv[2][0] == 'l' || argv[2][0] == 'L' || argv[2][0] == 't' || argv[2][0] == 'T')
        {
            j = 20; //register 20
        }
        else if (argv[2][0] == 'p' || argv[2][0] == 'P' )
        {   
            data = cvmx_read_csr(CVMX_ADD_IO_SEG(PCS1_MR0_CONTROL_REG));
            printf("PCS1_MR0_CONTROL_REG    read:0x%08x%08x\n", data >> 32, data);

            if (data & 0x4000)
            {
                /* clear loopback bit */
                data = data & ~0x4000;
            }
            else
            {
                /* set loopback bit */
                data = data | 0x4000;
            }

            cvmx_write_csr(CVMX_ADD_IO_SEG(PCS1_MR0_CONTROL_REG), data);
            printf("PCS1_MR0_CONTROL_REG   wrote:0x%08x%08x\n", data >> 32, data);

            //we're done
            return 0;

        }
        else if (argv[2][0] == 'q' || argv[2][0] == 'Q' )
        {   
            data = cvmx_read_csr(CVMX_ADD_IO_SEG(PCS1_MISC0_CONTROL_REG));
            printf("PCS1_MISC0_CONTROL_REG    read:0x%08x%08x\n", data >> 32, data);

            if (data & 0x0400)
            {
                //clear loopback bit
                data = data & ~0x0400;
            }
            else
            {
                //set loopback bit
                data = data | 0x0400;
            }

            cvmx_write_csr(CVMX_ADD_IO_SEG(PCS1_MISC0_CONTROL_REG), data);
            printf("PCS1_MISC0_CONTROL_REG   wrote:0x%08x%08x\n", data >> 32, data);

            //we're done
            return 0;
        }
        else if (argv[2][0] == 'g' || argv[2][0] == 'G' )
        {   
            data = cvmx_read_csr(CVMX_ADD_IO_SEG(PCSX_CONTROL1_REG));
            printf("PCSX_CONTROL1_REG    read:0x%08x%08x\n", data >> 32, data);

            if (argv[2][1] != 'r')
            {
                if (data & 0x4000)
                {
                    //clear loopback bit
                    data = data & ~0x4000;
                }
                else
                {
                    //set loopback bit
                    data = data | 0x4000;
                }

            }
            if (argv[2][1] == 'r')
            {
                //set reset bit
                data = data | 0x8000;
            }

            cvmx_write_csr(CVMX_ADD_IO_SEG(PCSX_CONTROL1_REG), data);
            printf("PCSX_CONTROL1_REG   wrote:0x%08x%08x\n", data >> 32, data);

            /** 
            *   it takes 32 clock cycles for the reset to comnplete. By
            *   the time we execute a ping it will be thousands of clock
            *   cycles later
            **/
            //we're done
            return 0;
        }

        if (j == 0)
        {
            j = 20;
            miiphy_read(i, j, &val);
            if (val & 0x0070)
            {
                //clear bits 6:4
                val = val & ~0x0070;
            }
            else
            {
                //set loopback bit
                val = val | 0x0070;
            }

            j = 0;
            //soft reset
            /* read the current value out of the register on the MDIO interface */
            miiphy_read(i, j, &val);
            val = val | 0x8000;
            miiphy_write(i, j, val);
            do
            {
                miiphy_read(i, j, &val);
            }while ((val & 0x8000) != 0) ; /* wait till finished */



        }

        /* read the current value out of the register on the MDIO interface */
        miiphy_read(i, j, &val);

        printf("PHY:0x%x reg:%d  read:0x%04x ", i, j,val);

        if (argv[2][0] == 'l' || argv[2][0] == 'L')
        {
            if (val & 0x4000)
            {
                //clear loopback bit
                val = val & ~0x4000;
            }
            else
            {
                //set loopback bit
                val = val | 0x4000;
            }
        }
        else /* we must be toggling the Tx enable */
        {
            if (val & 0x0001)
            {
                //clear loopback bit
                val = val & ~0x0001;
            }
            else
            {
                //set loopback bit
                val = val | 0x0001;
            }
        }
        miiphy_write(i, j, val);

        printf("wrote:0x%04x\n ", val);

		return 0;

    }
	printf("ERROR: Too many arguments\n");
    return -1;
}

U_BOOT_CMD(
          phyl,   3,  1,  do_phy_loopback,
          "phyl     - phyl 0 l or phy 0 m or phy 0 t  (l=line m=mac t=Tx [toggles the value for either l, m, or t]) \n",
          );

int do_xaui_loopback (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    uint64_t data; 

    if (argc < 3)
    {
        return -1;
    }
    if (argc == 3)
    {
        if (argv[2][0] == 'r' || argv[2][0] == 'r' )
        {
            data = cvmx_read_csr(CVMX_ADD_IO_SEG(0x11800B0000800ull));
            printf("PCSX0_CONTROL1_REG    read:0x%08x%08x\n", data >> 32, data);
            /* reset PCS */
            data |= 0x8000;
            //cvmx_write_csr(uint64_t csr_addr, uint64_t val)
            cvmx_write_csr(CVMX_ADD_IO_SEG(0x11800B0000800ull), data);
            printf("PCSX0_CONTROL1_REG   wrote:0x%08x%08x\n", data >> 32, data);

            data = cvmx_read_csr(CVMX_ADD_IO_SEG(0x11800B8000800ull));
            printf("PCSX1_CONTROL1_REG    read:0x%08x%08x\n", data >> 32, data);
            /* reset PCS */
            data |= 0x8000;
            cvmx_write_csr(CVMX_ADD_IO_SEG(0x11800B8000800ull), data);
            printf("PCSX1_CONTROL1_REG   wrote:0x%08x%08x\n", data >> 32, data);
        }
        if (argv[2][0] == 'p' || argv[2][0] == 'P' )
        {
            data = cvmx_read_csr(CVMX_ADD_IO_SEG(0x11800B0000800ull));
            printf("PCSX0_CONTROL1_REG    read:0x%08x%08x\n", data >> 32, data);

            if (data & 0x4000)
            {
                /* clear loopback bit */
                data = data & ~0x4000;
            }
            else
            {
                /* set loopback bit */
                data = data | 0x4000;
            }

            //cvmx_write_csr(uint64_t csr_addr, uint64_t val)
            cvmx_write_csr(CVMX_ADD_IO_SEG(0x11800B0000800ull), data);
            printf("PCSX0_CONTROL1_REG   wrote:0x%08x%08x\n", data >> 32, data);

            data = cvmx_read_csr(CVMX_ADD_IO_SEG(0x11800B8000800ull));
            printf("PCSX1_CONTROL1_REG    read:0x%08x%08x\n", data >> 32, data);

            if (data & 0x4000)
            {
                /* clear loopback bit */
                data = data & ~0x4000;
            }
            else
            {
                /* set loopback bit */
                data = data | 0x4000;
            }

            //cvmx_write_csr(uint64_t csr_addr, uint64_t val)
            cvmx_write_csr(CVMX_ADD_IO_SEG(0x11800B8000800ull), data);
            printf("PCSX1_CONTROL1_REG   wrote:0x%08x%08x\n", data >> 32, data);

            //we're done
        }
        else if (argv[2][0] == 'g' || argv[2][0] == 'G' )
        {

            data = cvmx_read_csr(CVMX_ADD_IO_SEG(0x11800B8001078ull));
            printf("PCSX0_MISC0_CONTROL_REG    read:0x%08x%08x\n", data >> 32, data);

            if (data & 0x0400)
            {
                //clear loopback bit
                data = data & ~0x0400;
            }
            else
            {
                //set loopback bit
                data = data | 0x0400;
            }

            cvmx_write_csr(CVMX_ADD_IO_SEG(0x11800B8001078ull), data);
            printf("PCS1_MISC0_CONTROL_REG   wrote:0x%08x%08x\n", data >> 32, data);

            /* reset PCS logic */
            data = cvmx_read_csr(CVMX_ADD_IO_SEG(0x11800B8001000ull));
            data |= 0x8000;
            cvmx_write_csr(CVMX_ADD_IO_SEG(0x11800B8001000ull), data);

            //we're done
        }
    }
    return 0;
}

U_BOOT_CMD(
          xauil,   3,  1,  do_xaui_loopback,
          "xauil     - xauil 0 p or xauil 0 g \n",
          );


#include "cvmx-csr-db.h"

static const CVMX_CSR_DB_ADDRESS_TYPE gmx_regs_56xx[] = {
    /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_RX000_STATS_PKTS"       ,       0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX0_RX001_STATS_PKTS"       ,       0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX0_RX002_STATS_PKTS"       ,       0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX0_RX003_STATS_PKTS"       ,       0x1180008001880ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
#endif
    {"GMX1_RX000_STATS_PKTS"       ,       0x1180010000080ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX1_RX001_STATS_PKTS"       ,       0x1180010000880ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX1_RX002_STATS_PKTS"       ,       0x1180010001080ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX1_RX003_STATS_PKTS"       ,       0x1180010001880ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_RX000_STATS_PKTS_BAD"   ,       0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX0_RX001_STATS_PKTS_BAD"   ,       0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX0_RX002_STATS_PKTS_BAD"   ,       0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX0_RX003_STATS_PKTS_BAD"   ,       0x11800080018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
#endif
    {"GMX1_RX000_STATS_PKTS_BAD"   ,       0x11800100000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX1_RX001_STATS_PKTS_BAD"   ,       0x11800100008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX1_RX002_STATS_PKTS_BAD"   ,       0x11800100010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX1_RX003_STATS_PKTS_BAD"   ,       0x11800100018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_RX000_STATS_PKTS_CTL"   ,       0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX0_RX001_STATS_PKTS_CTL"   ,       0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX0_RX002_STATS_PKTS_CTL"   ,       0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX0_RX003_STATS_PKTS_CTL"   ,       0x1180008001890ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
#endif
    {"GMX1_RX000_STATS_PKTS_CTL"   ,       0x1180010000090ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX1_RX001_STATS_PKTS_CTL"   ,       0x1180010000890ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX1_RX002_STATS_PKTS_CTL"   ,       0x1180010001090ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX1_RX003_STATS_PKTS_CTL"   ,       0x1180010001890ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_RX000_STATS_PKTS_DMAC"  ,       0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX0_RX001_STATS_PKTS_DMAC"  ,       0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX0_RX002_STATS_PKTS_DMAC"  ,       0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX0_RX003_STATS_PKTS_DMAC"  ,       0x11800080018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
#endif
    {"GMX1_RX000_STATS_PKTS_DMAC"  ,       0x11800100000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX1_RX001_STATS_PKTS_DMAC"  ,       0x11800100008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX1_RX002_STATS_PKTS_DMAC"  ,       0x11800100010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX1_RX003_STATS_PKTS_DMAC"  ,       0x11800100018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_RX000_STATS_PKTS_DRP"   ,       0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX0_RX001_STATS_PKTS_DRP"   ,       0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX0_RX002_STATS_PKTS_DRP"   ,       0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX0_RX003_STATS_PKTS_DRP"   ,       0x11800080018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
#endif
    {"GMX1_RX000_STATS_PKTS_DRP"   ,       0x11800100000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX1_RX001_STATS_PKTS_DRP"   ,       0x11800100008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX1_RX002_STATS_PKTS_DRP"   ,       0x11800100010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX1_RX003_STATS_PKTS_DRP"   ,       0x11800100018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STAT0"            ,       0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX0_TX001_STAT0"            ,       0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX0_TX002_STAT0"            ,       0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX0_TX003_STAT0"            ,       0x1180008001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
#endif
    {"GMX1_TX000_STAT0"            ,       0x1180010000280ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX1_TX001_STAT0"            ,       0x1180010000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX1_TX002_STAT0"            ,       0x1180010001280ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX1_TX003_STAT0"            ,       0x1180010001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STAT1"            ,       0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX0_TX001_STAT1"            ,       0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX0_TX002_STAT1"            ,       0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX0_TX003_STAT1"            ,       0x1180008001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
#endif
    {"GMX1_TX000_STAT1"            ,       0x1180010000288ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX1_TX001_STAT1"            ,       0x1180010000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX1_TX002_STAT1"            ,       0x1180010001288ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX1_TX003_STAT1"            ,       0x1180010001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STAT2"            ,       0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX0_TX001_STAT2"            ,       0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX0_TX002_STAT2"            ,       0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX0_TX003_STAT2"            ,       0x1180008001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
#endif
    {"GMX1_TX000_STAT2"            ,       0x1180010000290ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX1_TX001_STAT2"            ,       0x1180010000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX1_TX002_STAT2"            ,       0x1180010001290ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX1_TX003_STAT2"            ,       0x1180010001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STAT3"            ,       0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX0_TX001_STAT3"            ,       0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX0_TX002_STAT3"            ,       0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX0_TX003_STAT3"            ,       0x1180008001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
#endif
    {"GMX1_TX000_STAT3"            ,       0x1180010000298ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX1_TX001_STAT3"            ,       0x1180010000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX1_TX002_STAT3"            ,       0x1180010001298ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX1_TX003_STAT3"            ,       0x1180010001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STAT4"            ,       0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX0_TX001_STAT4"            ,       0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX0_TX002_STAT4"            ,       0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX0_TX003_STAT4"            ,       0x1180008001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
#endif
    {"GMX1_TX000_STAT4"            ,       0x11800100002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX1_TX001_STAT4"            ,       0x1180010000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX1_TX002_STAT4"            ,       0x11800100012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX1_TX003_STAT4"            ,       0x1180010001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STAT5"            ,       0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX0_TX001_STAT5"            ,       0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX0_TX002_STAT5"            ,       0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX0_TX003_STAT5"            ,       0x1180008001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
#endif
    {"GMX1_TX000_STAT5"            ,       0x11800100002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX1_TX001_STAT5"            ,       0x1180010000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX1_TX002_STAT5"            ,       0x11800100012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX1_TX003_STAT5"            ,       0x1180010001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STAT6"            ,       0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX0_TX001_STAT6"            ,       0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX0_TX002_STAT6"            ,       0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX0_TX003_STAT6"            ,       0x1180008001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
#endif
    {"GMX1_TX000_STAT6"            ,       0x11800100002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX1_TX001_STAT6"            ,       0x1180010000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX1_TX002_STAT6"            ,       0x11800100012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX1_TX003_STAT6"            ,       0x1180010001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STAT7"            ,       0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX0_TX001_STAT7"            ,       0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX0_TX002_STAT7"            ,       0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX0_TX003_STAT7"            ,       0x1180008001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
#endif
    {"GMX1_TX000_STAT7"            ,       0x11800100002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX1_TX001_STAT7"            ,       0x1180010000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX1_TX002_STAT7"            ,       0x11800100012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX1_TX003_STAT7"            ,       0x1180010001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STAT8"            ,       0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX0_TX001_STAT8"            ,       0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX0_TX002_STAT8"            ,       0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX0_TX003_STAT8"            ,       0x1180008001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
#endif
    {"GMX1_TX000_STAT8"            ,       0x11800100002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX1_TX001_STAT8"            ,       0x1180010000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX1_TX002_STAT8"            ,       0x11800100012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX1_TX003_STAT8"            ,       0x1180010001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STAT9"            ,       0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX0_TX001_STAT9"            ,       0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX0_TX002_STAT9"            ,       0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX0_TX003_STAT9"            ,       0x1180008001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
#endif
    {"GMX1_TX000_STAT9"            ,       0x11800100002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX1_TX001_STAT9"            ,       0x1180010000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX1_TX002_STAT9"            ,       0x11800100012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX1_TX003_STAT9"            ,       0x1180010001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_TX000_STATS_CTL"        ,       0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX0_TX001_STATS_CTL"        ,       0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX0_TX002_STATS_CTL"        ,       0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX0_TX003_STATS_CTL"        ,       0x1180008001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
#endif
    {"GMX1_TX000_STATS_CTL"        ,       0x1180010000268ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX1_TX001_STATS_CTL"        ,       0x1180010000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX1_TX002_STATS_CTL"        ,       0x1180010001268ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX1_TX003_STATS_CTL"        ,       0x1180010001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {NULL,0,0,0,0}
};

static const CVMX_CSR_DB_ADDRESS_TYPE pcs_regs_56xx[] = {
    /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
#if defined(CONFIG_OCTEON_SGMII_DUAL)

    {"PCS0_AN000_ADV_REG"          ,       0x11800B0001010ull,  CVMX_CSR_DB_TYPE_RSL,   64, 648},
    {"PCS0_AN001_ADV_REG"          ,       0x11800B0001410ull,  CVMX_CSR_DB_TYPE_RSL,   64, 648},
    {"PCS0_AN002_ADV_REG"          ,       0x11800B0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64, 648},
    {"PCS0_AN003_ADV_REG"          ,       0x11800B0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64, 648},
#endif
    {"PCS1_AN000_ADV_REG"          ,       0x11800B8001010ull,  CVMX_CSR_DB_TYPE_RSL,   64, 648},
    {"PCS1_AN001_ADV_REG"          ,       0x11800B8001410ull,  CVMX_CSR_DB_TYPE_RSL,   64, 648},
    {"PCS1_AN002_ADV_REG"          ,       0x11800B8001810ull,  CVMX_CSR_DB_TYPE_RSL,   64, 648},
    {"PCS1_AN003_ADV_REG"          ,       0x11800B8001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64, 648},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_AN000_EXT_ST_REG"       ,       0x11800B0001028ull,  CVMX_CSR_DB_TYPE_RSL,   64, 649},
    {"PCS0_AN001_EXT_ST_REG"       ,       0x11800B0001428ull,  CVMX_CSR_DB_TYPE_RSL,   64, 649},
    {"PCS0_AN002_EXT_ST_REG"       ,       0x11800B0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64, 649},
    {"PCS0_AN003_EXT_ST_REG"       ,       0x11800B0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64, 649},
#endif
    {"PCS1_AN000_EXT_ST_REG"       ,       0x11800B8001028ull,  CVMX_CSR_DB_TYPE_RSL,   64, 649},
    {"PCS1_AN001_EXT_ST_REG"       ,       0x11800B8001428ull,  CVMX_CSR_DB_TYPE_RSL,   64, 649},
    {"PCS1_AN002_EXT_ST_REG"       ,       0x11800B8001828ull,  CVMX_CSR_DB_TYPE_RSL,   64, 649},
    {"PCS1_AN003_EXT_ST_REG"       ,       0x11800B8001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64, 649},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_AN000_LP_ABIL_REG"      ,       0x11800B0001018ull,  CVMX_CSR_DB_TYPE_RSL,   64, 650},
    {"PCS0_AN001_LP_ABIL_REG"      ,       0x11800B0001418ull,  CVMX_CSR_DB_TYPE_RSL,   64, 650},
    {"PCS0_AN002_LP_ABIL_REG"      ,       0x11800B0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64, 650},
    {"PCS0_AN003_LP_ABIL_REG"      ,       0x11800B0001C18ull,  CVMX_CSR_DB_TYPE_RSL,   64, 650},
#endif
    {"PCS1_AN000_LP_ABIL_REG"      ,       0x11800B8001018ull,  CVMX_CSR_DB_TYPE_RSL,   64, 650},
    {"PCS1_AN001_LP_ABIL_REG"      ,       0x11800B8001418ull,  CVMX_CSR_DB_TYPE_RSL,   64, 650},
    {"PCS1_AN002_LP_ABIL_REG"      ,       0x11800B8001818ull,  CVMX_CSR_DB_TYPE_RSL,   64, 650},
    {"PCS1_AN003_LP_ABIL_REG"      ,       0x11800B8001C18ull,  CVMX_CSR_DB_TYPE_RSL,   64, 650},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_AN000_RESULTS_REG"      ,       0x11800B0001020ull,  CVMX_CSR_DB_TYPE_RSL,   64, 651},
    {"PCS0_AN001_RESULTS_REG"      ,       0x11800B0001420ull,  CVMX_CSR_DB_TYPE_RSL,   64, 651},
    {"PCS0_AN002_RESULTS_REG"      ,       0x11800B0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64, 651},
    {"PCS0_AN003_RESULTS_REG"      ,       0x11800B0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64, 651},
#endif
    {"PCS1_AN000_RESULTS_REG"      ,       0x11800B8001020ull,  CVMX_CSR_DB_TYPE_RSL,   64, 651},
    {"PCS1_AN001_RESULTS_REG"      ,       0x11800B8001420ull,  CVMX_CSR_DB_TYPE_RSL,   64, 651},
    {"PCS1_AN002_RESULTS_REG"      ,       0x11800B8001820ull,  CVMX_CSR_DB_TYPE_RSL,   64, 651},
    {"PCS1_AN003_RESULTS_REG"      ,       0x11800B8001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64, 651},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_INT000_EN_REG"          ,       0x11800B0001088ull,  CVMX_CSR_DB_TYPE_RSL,   64, 652},
    {"PCS0_INT001_EN_REG"          ,       0x11800B0001488ull,  CVMX_CSR_DB_TYPE_RSL,   64, 652},
    {"PCS0_INT002_EN_REG"          ,       0x11800B0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64, 652},
    {"PCS0_INT003_EN_REG"          ,       0x11800B0001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64, 652},
#endif
    {"PCS1_INT000_EN_REG"          ,       0x11800B8001088ull,  CVMX_CSR_DB_TYPE_RSL,   64, 652},
    {"PCS1_INT001_EN_REG"          ,       0x11800B8001488ull,  CVMX_CSR_DB_TYPE_RSL,   64, 652},
    {"PCS1_INT002_EN_REG"          ,       0x11800B8001888ull,  CVMX_CSR_DB_TYPE_RSL,   64, 652},
    {"PCS1_INT003_EN_REG"          ,       0x11800B8001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64, 652},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_INT000_REG"             ,       0x11800B0001080ull,  CVMX_CSR_DB_TYPE_RSL,   64, 653},
    {"PCS0_INT001_REG"             ,       0x11800B0001480ull,  CVMX_CSR_DB_TYPE_RSL,   64, 653},
    {"PCS0_INT002_REG"             ,       0x11800B0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64, 653},
    {"PCS0_INT003_REG"             ,       0x11800B0001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64, 653},
#endif
    {"PCS1_INT000_REG"             ,       0x11800B8001080ull,  CVMX_CSR_DB_TYPE_RSL,   64, 653},
    {"PCS1_INT001_REG"             ,       0x11800B8001480ull,  CVMX_CSR_DB_TYPE_RSL,   64, 653},
    {"PCS1_INT002_REG"             ,       0x11800B8001880ull,  CVMX_CSR_DB_TYPE_RSL,   64, 653},
    {"PCS1_INT003_REG"             ,       0x11800B8001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64, 653},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_LINK000_TIMER_COUNT_REG",       0x11800B0001040ull,  CVMX_CSR_DB_TYPE_RSL,   64, 654},
    {"PCS0_LINK001_TIMER_COUNT_REG",       0x11800B0001440ull,  CVMX_CSR_DB_TYPE_RSL,   64, 654},
    {"PCS0_LINK002_TIMER_COUNT_REG",       0x11800B0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64, 654},
    {"PCS0_LINK003_TIMER_COUNT_REG",       0x11800B0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64, 654},
#endif
    {"PCS1_LINK000_TIMER_COUNT_REG",       0x11800B8001040ull,  CVMX_CSR_DB_TYPE_RSL,   64, 654},
    {"PCS1_LINK001_TIMER_COUNT_REG",       0x11800B8001440ull,  CVMX_CSR_DB_TYPE_RSL,   64, 654},
    {"PCS1_LINK002_TIMER_COUNT_REG",       0x11800B8001840ull,  CVMX_CSR_DB_TYPE_RSL,   64, 654},
    {"PCS1_LINK003_TIMER_COUNT_REG",       0x11800B8001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64, 654},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_LOG_ANL000_REG"         ,       0x11800B0001090ull,  CVMX_CSR_DB_TYPE_RSL,   64, 655},
    {"PCS0_LOG_ANL001_REG"         ,       0x11800B0001490ull,  CVMX_CSR_DB_TYPE_RSL,   64, 655},
    {"PCS0_LOG_ANL002_REG"         ,       0x11800B0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64, 655},
    {"PCS0_LOG_ANL003_REG"         ,       0x11800B0001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64, 655},
#endif
    {"PCS1_LOG_ANL000_REG"         ,       0x11800B8001090ull,  CVMX_CSR_DB_TYPE_RSL,   64, 655},
    {"PCS1_LOG_ANL001_REG"         ,       0x11800B8001490ull,  CVMX_CSR_DB_TYPE_RSL,   64, 655},
    {"PCS1_LOG_ANL002_REG"         ,       0x11800B8001890ull,  CVMX_CSR_DB_TYPE_RSL,   64, 655},
    {"PCS1_LOG_ANL003_REG"         ,       0x11800B8001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64, 655},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_MISC000_CTL_REG"        ,       0x11800B0001078ull,  CVMX_CSR_DB_TYPE_RSL,   64, 656},
    {"PCS0_MISC001_CTL_REG"        ,       0x11800B0001478ull,  CVMX_CSR_DB_TYPE_RSL,   64, 656},
    {"PCS0_MISC002_CTL_REG"        ,       0x11800B0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64, 656},
    {"PCS0_MISC003_CTL_REG"        ,       0x11800B0001C78ull,  CVMX_CSR_DB_TYPE_RSL,   64, 656},
#endif
    {"PCS1_MISC000_CTL_REG"        ,       0x11800B8001078ull,  CVMX_CSR_DB_TYPE_RSL,   64, 656},
    {"PCS1_MISC001_CTL_REG"        ,       0x11800B8001478ull,  CVMX_CSR_DB_TYPE_RSL,   64, 656},
    {"PCS1_MISC002_CTL_REG"        ,       0x11800B8001878ull,  CVMX_CSR_DB_TYPE_RSL,   64, 656},
    {"PCS1_MISC003_CTL_REG"        ,       0x11800B8001C78ull,  CVMX_CSR_DB_TYPE_RSL,   64, 656},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_MR000_CONTROL_REG"      ,       0x11800B0001000ull,  CVMX_CSR_DB_TYPE_RSL,   64, 657},
    {"PCS0_MR001_CONTROL_REG"      ,       0x11800B0001400ull,  CVMX_CSR_DB_TYPE_RSL,   64, 657},
    {"PCS0_MR002_CONTROL_REG"      ,       0x11800B0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64, 657},
    {"PCS0_MR003_CONTROL_REG"      ,       0x11800B0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64, 657},
#endif
    {"PCS1_MR000_CONTROL_REG"      ,       0x11800B8001000ull,  CVMX_CSR_DB_TYPE_RSL,   64, 657},
    {"PCS1_MR001_CONTROL_REG"      ,       0x11800B8001400ull,  CVMX_CSR_DB_TYPE_RSL,   64, 657},
    {"PCS1_MR002_CONTROL_REG"      ,       0x11800B8001800ull,  CVMX_CSR_DB_TYPE_RSL,   64, 657},
    {"PCS1_MR003_CONTROL_REG"      ,       0x11800B8001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64, 657},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_MR000_STATUS_REG"       ,       0x11800B0001008ull,  CVMX_CSR_DB_TYPE_RSL,   64, 658},
    {"PCS0_MR001_STATUS_REG"       ,       0x11800B0001408ull,  CVMX_CSR_DB_TYPE_RSL,   64, 658},
    {"PCS0_MR002_STATUS_REG"       ,       0x11800B0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64, 658},
    {"PCS0_MR003_STATUS_REG"       ,       0x11800B0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64, 658},
#endif
    {"PCS1_MR000_STATUS_REG"       ,       0x11800B8001008ull,  CVMX_CSR_DB_TYPE_RSL,   64, 658},
    {"PCS1_MR001_STATUS_REG"       ,       0x11800B8001408ull,  CVMX_CSR_DB_TYPE_RSL,   64, 658},
    {"PCS1_MR002_STATUS_REG"       ,       0x11800B8001808ull,  CVMX_CSR_DB_TYPE_RSL,   64, 658},
    {"PCS1_MR003_STATUS_REG"       ,       0x11800B8001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64, 658},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_RX000_STATES_REG"       ,       0x11800B0001058ull,  CVMX_CSR_DB_TYPE_RSL,   64, 659},
    {"PCS0_RX001_STATES_REG"       ,       0x11800B0001458ull,  CVMX_CSR_DB_TYPE_RSL,   64, 659},
    {"PCS0_RX002_STATES_REG"       ,       0x11800B0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64, 659},
    {"PCS0_RX003_STATES_REG"       ,       0x11800B0001C58ull,  CVMX_CSR_DB_TYPE_RSL,   64, 659},
#endif
    {"PCS1_RX000_STATES_REG"       ,       0x11800B8001058ull,  CVMX_CSR_DB_TYPE_RSL,   64, 659},
    {"PCS1_RX001_STATES_REG"       ,       0x11800B8001458ull,  CVMX_CSR_DB_TYPE_RSL,   64, 659},
    {"PCS1_RX002_STATES_REG"       ,       0x11800B8001858ull,  CVMX_CSR_DB_TYPE_RSL,   64, 659},
    {"PCS1_RX003_STATES_REG"       ,       0x11800B8001C58ull,  CVMX_CSR_DB_TYPE_RSL,   64, 659},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_RX000_SYNC_REG"         ,       0x11800B0001050ull,  CVMX_CSR_DB_TYPE_RSL,   64, 660},
    {"PCS0_RX001_SYNC_REG"         ,       0x11800B0001450ull,  CVMX_CSR_DB_TYPE_RSL,   64, 660},
    {"PCS0_RX002_SYNC_REG"         ,       0x11800B0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64, 660},
    {"PCS0_RX003_SYNC_REG"         ,       0x11800B0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64, 660},
#endif
    {"PCS1_RX000_SYNC_REG"         ,       0x11800B8001050ull,  CVMX_CSR_DB_TYPE_RSL,   64, 660},
    {"PCS1_RX001_SYNC_REG"         ,       0x11800B8001450ull,  CVMX_CSR_DB_TYPE_RSL,   64, 660},
    {"PCS1_RX002_SYNC_REG"         ,       0x11800B8001850ull,  CVMX_CSR_DB_TYPE_RSL,   64, 660},
    {"PCS1_RX003_SYNC_REG"         ,       0x11800B8001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64, 660},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_SGM000_AN_ADV_REG"      ,       0x11800B0001068ull,  CVMX_CSR_DB_TYPE_RSL,   64, 661},
    {"PCS0_SGM001_AN_ADV_REG"      ,       0x11800B0001468ull,  CVMX_CSR_DB_TYPE_RSL,   64, 661},
    {"PCS0_SGM002_AN_ADV_REG"      ,       0x11800B0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64, 661},
    {"PCS0_SGM003_AN_ADV_REG"      ,       0x11800B0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64, 661},
#endif
    {"PCS1_SGM000_AN_ADV_REG"      ,       0x11800B8001068ull,  CVMX_CSR_DB_TYPE_RSL,   64, 661},
    {"PCS1_SGM001_AN_ADV_REG"      ,       0x11800B8001468ull,  CVMX_CSR_DB_TYPE_RSL,   64, 661},
    {"PCS1_SGM002_AN_ADV_REG"      ,       0x11800B8001868ull,  CVMX_CSR_DB_TYPE_RSL,   64, 661},
    {"PCS1_SGM003_AN_ADV_REG"      ,       0x11800B8001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64, 661},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_SGM000_LP_ADV_REG"      ,       0x11800B0001070ull,  CVMX_CSR_DB_TYPE_RSL,   64, 662},
    {"PCS0_SGM001_LP_ADV_REG"      ,       0x11800B0001470ull,  CVMX_CSR_DB_TYPE_RSL,   64, 662},
    {"PCS0_SGM002_LP_ADV_REG"      ,       0x11800B0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64, 662},
    {"PCS0_SGM003_LP_ADV_REG"      ,       0x11800B0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64, 662},
#endif
    {"PCS1_SGM000_LP_ADV_REG"      ,       0x11800B8001070ull,  CVMX_CSR_DB_TYPE_RSL,   64, 662},
    {"PCS1_SGM001_LP_ADV_REG"      ,       0x11800B8001470ull,  CVMX_CSR_DB_TYPE_RSL,   64, 662},
    {"PCS1_SGM002_LP_ADV_REG"      ,       0x11800B8001870ull,  CVMX_CSR_DB_TYPE_RSL,   64, 662},
    {"PCS1_SGM003_LP_ADV_REG"      ,       0x11800B8001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64, 662},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_TX000_STATES_REG"       ,       0x11800B0001060ull,  CVMX_CSR_DB_TYPE_RSL,   64, 663},
    {"PCS0_TX001_STATES_REG"       ,       0x11800B0001460ull,  CVMX_CSR_DB_TYPE_RSL,   64, 663},
    {"PCS0_TX002_STATES_REG"       ,       0x11800B0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64, 663},
    {"PCS0_TX003_STATES_REG"       ,       0x11800B0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64, 663},
#endif
    {"PCS1_TX000_STATES_REG"       ,       0x11800B8001060ull,  CVMX_CSR_DB_TYPE_RSL,   64, 663},
    {"PCS1_TX001_STATES_REG"       ,       0x11800B8001460ull,  CVMX_CSR_DB_TYPE_RSL,   64, 663},
    {"PCS1_TX002_STATES_REG"       ,       0x11800B8001860ull,  CVMX_CSR_DB_TYPE_RSL,   64, 663},
    {"PCS1_TX003_STATES_REG"       ,       0x11800B8001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64, 663},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCS0_TX_RX000_POLARITY_REG"  ,       0x11800B0001048ull,  CVMX_CSR_DB_TYPE_RSL,   64, 664},
    {"PCS0_TX_RX001_POLARITY_REG"  ,       0x11800B0001448ull,  CVMX_CSR_DB_TYPE_RSL,   64, 664},
    {"PCS0_TX_RX002_POLARITY_REG"  ,       0x11800B0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64, 664},
    {"PCS0_TX_RX003_POLARITY_REG"  ,       0x11800B0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64, 664},
#endif
    {"PCS1_TX_RX000_POLARITY_REG"  ,       0x11800B8001048ull,  CVMX_CSR_DB_TYPE_RSL,   64, 664},
    {"PCS1_TX_RX001_POLARITY_REG"  ,       0x11800B8001448ull,  CVMX_CSR_DB_TYPE_RSL,   64, 664},
    {"PCS1_TX_RX002_POLARITY_REG"  ,       0x11800B8001848ull,  CVMX_CSR_DB_TYPE_RSL,   64, 664},
    {"PCS1_TX_RX003_POLARITY_REG"  ,       0x11800B8001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64, 664},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_10GBX_STATUS_REG"      ,       0x11800B0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64, 665},
#endif
    {"PCSX1_10GBX_STATUS_REG"      ,       0x11800B8000828ull,  CVMX_CSR_DB_TYPE_RSL,   64, 665},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_BIST_STATUS_REG"       ,       0x11800B0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64, 666},
#endif
    {"PCSX1_BIST_STATUS_REG"       ,       0x11800B8000870ull,  CVMX_CSR_DB_TYPE_RSL,   64, 666},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_BIT_LOCK_STATUS_REG"   ,       0x11800B0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64, 667},
#endif
    {"PCSX1_BIT_LOCK_STATUS_REG"   ,       0x11800B8000850ull,  CVMX_CSR_DB_TYPE_RSL,   64, 667},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_CONTROL1_REG"          ,       0x11800B0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64, 668},
#endif
    {"PCSX1_CONTROL1_REG"          ,       0x11800B8000800ull,  CVMX_CSR_DB_TYPE_RSL,   64, 668},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_CONTROL2_REG"          ,       0x11800B0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64, 669},
#endif
    {"PCSX1_CONTROL2_REG"          ,       0x11800B8000818ull,  CVMX_CSR_DB_TYPE_RSL,   64, 669},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_INT_EN_REG"            ,       0x11800B0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64, 670},
#endif
    {"PCSX1_INT_EN_REG"            ,       0x11800B8000860ull,  CVMX_CSR_DB_TYPE_RSL,   64, 670},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_INT_REG"               ,       0x11800B0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64, 671},
#endif
    {"PCSX1_INT_REG"               ,       0x11800B8000858ull,  CVMX_CSR_DB_TYPE_RSL,   64, 671},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_LOG_ANL_REG"           ,       0x11800B0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64, 672},
#endif
    {"PCSX1_LOG_ANL_REG"           ,       0x11800B8000868ull,  CVMX_CSR_DB_TYPE_RSL,   64, 672},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_MISC_CTL_REG"          ,       0x11800B0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64, 673},
#endif
    {"PCSX1_MISC_CTL_REG"          ,       0x11800B8000848ull,  CVMX_CSR_DB_TYPE_RSL,   64, 673},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_RX_SYNC_STATES_REG"    ,       0x11800B0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64, 674},
#endif
    {"PCSX1_RX_SYNC_STATES_REG"    ,       0x11800B8000838ull,  CVMX_CSR_DB_TYPE_RSL,   64, 674},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_SPD_ABIL_REG"          ,       0x11800B0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64, 675},
#endif
    {"PCSX1_SPD_ABIL_REG"          ,       0x11800B8000810ull,  CVMX_CSR_DB_TYPE_RSL,   64, 675},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_STATUS1_REG"           ,       0x11800B0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64, 676},
#endif
    {"PCSX1_STATUS1_REG"           ,       0x11800B8000808ull,  CVMX_CSR_DB_TYPE_RSL,   64, 676},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_STATUS2_REG"           ,       0x11800B0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64, 677},
#endif
    {"PCSX1_STATUS2_REG"           ,       0x11800B8000820ull,  CVMX_CSR_DB_TYPE_RSL,   64, 677},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_TX_RX_POLARITY_REG"    ,       0x11800B0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64, 678},
#endif
    {"PCSX1_TX_RX_POLARITY_REG"    ,       0x11800B8000840ull,  CVMX_CSR_DB_TYPE_RSL,   64, 678},
#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"PCSX0_TX_RX_STATES_REG"      ,       0x11800B0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64, 679},
#endif
    {"PCSX1_TX_RX_STATES_REG"      ,       0x11800B8000830ull,  CVMX_CSR_DB_TYPE_RSL,   64, 679},
    {NULL,0,0,0,0}

};

static const CVMX_CSR_DB_ADDRESS_TYPE gmx_all_regs_56xx[] = {
    /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
    {"GMX1_BAD_REG"                ,       0x1180010000518ull,  CVMX_CSR_DB_TYPE_RSL,   64, 112},
    {"GMX1_BIST"                   ,       0x1180010000400ull,  CVMX_CSR_DB_TYPE_RSL,   64, 113},
    {"GMX1_CLK_EN"                 ,       0x11800100007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 114},
    {"GMX1_HG2_CONTROL"            ,       0x1180010000550ull,  CVMX_CSR_DB_TYPE_RSL,   64, 115},
    {"GMX1_INF_MODE"               ,       0x11800100007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 116},
    {"GMX1_NXA_ADR"                ,       0x1180010000510ull,  CVMX_CSR_DB_TYPE_RSL,   64, 117},
    {"GMX1_PRT000_CFG"             ,       0x1180010000010ull,  CVMX_CSR_DB_TYPE_RSL,   64, 118},
    {"GMX1_PRT001_CFG"             ,       0x1180010000810ull,  CVMX_CSR_DB_TYPE_RSL,   64, 118},
    {"GMX1_PRT002_CFG"             ,       0x1180010001010ull,  CVMX_CSR_DB_TYPE_RSL,   64, 118},
    {"GMX1_PRT003_CFG"             ,       0x1180010001810ull,  CVMX_CSR_DB_TYPE_RSL,   64, 118},
    {"GMX1_RX000_ADR_CAM0"         ,       0x1180010000180ull,  CVMX_CSR_DB_TYPE_RSL,   64, 119},
    {"GMX1_RX001_ADR_CAM0"         ,       0x1180010000980ull,  CVMX_CSR_DB_TYPE_RSL,   64, 119},
    {"GMX1_RX002_ADR_CAM0"         ,       0x1180010001180ull,  CVMX_CSR_DB_TYPE_RSL,   64, 119},
    {"GMX1_RX003_ADR_CAM0"         ,       0x1180010001980ull,  CVMX_CSR_DB_TYPE_RSL,   64, 119},
    {"GMX1_RX000_ADR_CAM1"         ,       0x1180010000188ull,  CVMX_CSR_DB_TYPE_RSL,   64, 120},
    {"GMX1_RX001_ADR_CAM1"         ,       0x1180010000988ull,  CVMX_CSR_DB_TYPE_RSL,   64, 120},
    {"GMX1_RX002_ADR_CAM1"         ,       0x1180010001188ull,  CVMX_CSR_DB_TYPE_RSL,   64, 120},
    {"GMX1_RX003_ADR_CAM1"         ,       0x1180010001988ull,  CVMX_CSR_DB_TYPE_RSL,   64, 120},
    {"GMX1_RX000_ADR_CAM2"         ,       0x1180010000190ull,  CVMX_CSR_DB_TYPE_RSL,   64, 121},
    {"GMX1_RX001_ADR_CAM2"         ,       0x1180010000990ull,  CVMX_CSR_DB_TYPE_RSL,   64, 121},
    {"GMX1_RX002_ADR_CAM2"         ,       0x1180010001190ull,  CVMX_CSR_DB_TYPE_RSL,   64, 121},
    {"GMX1_RX003_ADR_CAM2"         ,       0x1180010001990ull,  CVMX_CSR_DB_TYPE_RSL,   64, 121},
    {"GMX1_RX000_ADR_CAM3"         ,       0x1180010000198ull,  CVMX_CSR_DB_TYPE_RSL,   64, 122},
    {"GMX1_RX001_ADR_CAM3"         ,       0x1180010000998ull,  CVMX_CSR_DB_TYPE_RSL,   64, 122},
    {"GMX1_RX002_ADR_CAM3"         ,       0x1180010001198ull,  CVMX_CSR_DB_TYPE_RSL,   64, 122},
    {"GMX1_RX003_ADR_CAM3"         ,       0x1180010001998ull,  CVMX_CSR_DB_TYPE_RSL,   64, 122},
    {"GMX1_RX000_ADR_CAM4"         ,       0x11800100001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 123},
    {"GMX1_RX001_ADR_CAM4"         ,       0x11800100009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 123},
    {"GMX1_RX002_ADR_CAM4"         ,       0x11800100011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 123},
    {"GMX1_RX003_ADR_CAM4"         ,       0x11800100019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 123},
    {"GMX1_RX000_ADR_CAM5"         ,       0x11800100001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 124},
    {"GMX1_RX001_ADR_CAM5"         ,       0x11800100009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 124},
    {"GMX1_RX002_ADR_CAM5"         ,       0x11800100011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 124},
    {"GMX1_RX003_ADR_CAM5"         ,       0x11800100019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 124},
    {"GMX1_RX000_ADR_CAM_EN"       ,       0x1180010000108ull,  CVMX_CSR_DB_TYPE_RSL,   64, 125},
    {"GMX1_RX001_ADR_CAM_EN"       ,       0x1180010000908ull,  CVMX_CSR_DB_TYPE_RSL,   64, 125},
    {"GMX1_RX002_ADR_CAM_EN"       ,       0x1180010001108ull,  CVMX_CSR_DB_TYPE_RSL,   64, 125},
    {"GMX1_RX003_ADR_CAM_EN"       ,       0x1180010001908ull,  CVMX_CSR_DB_TYPE_RSL,   64, 125},
    {"GMX1_RX000_ADR_CTL"          ,       0x1180010000100ull,  CVMX_CSR_DB_TYPE_RSL,   64, 126},
    {"GMX1_RX001_ADR_CTL"          ,       0x1180010000900ull,  CVMX_CSR_DB_TYPE_RSL,   64, 126},
    {"GMX1_RX002_ADR_CTL"          ,       0x1180010001100ull,  CVMX_CSR_DB_TYPE_RSL,   64, 126},
    {"GMX1_RX003_ADR_CTL"          ,       0x1180010001900ull,  CVMX_CSR_DB_TYPE_RSL,   64, 126},
    {"GMX1_RX000_DECISION"         ,       0x1180010000040ull,  CVMX_CSR_DB_TYPE_RSL,   64, 127},
    {"GMX1_RX001_DECISION"         ,       0x1180010000840ull,  CVMX_CSR_DB_TYPE_RSL,   64, 127},
    {"GMX1_RX002_DECISION"         ,       0x1180010001040ull,  CVMX_CSR_DB_TYPE_RSL,   64, 127},
    {"GMX1_RX003_DECISION"         ,       0x1180010001840ull,  CVMX_CSR_DB_TYPE_RSL,   64, 127},
    {"GMX1_RX000_FRM_CHK"          ,       0x1180010000020ull,  CVMX_CSR_DB_TYPE_RSL,   64, 128},
    {"GMX1_RX001_FRM_CHK"          ,       0x1180010000820ull,  CVMX_CSR_DB_TYPE_RSL,   64, 128},
    {"GMX1_RX002_FRM_CHK"          ,       0x1180010001020ull,  CVMX_CSR_DB_TYPE_RSL,   64, 128},
    {"GMX1_RX003_FRM_CHK"          ,       0x1180010001820ull,  CVMX_CSR_DB_TYPE_RSL,   64, 128},
    {"GMX1_RX000_FRM_CTL"          ,       0x1180010000018ull,  CVMX_CSR_DB_TYPE_RSL,   64, 129},
    {"GMX1_RX001_FRM_CTL"          ,       0x1180010000818ull,  CVMX_CSR_DB_TYPE_RSL,   64, 129},
    {"GMX1_RX002_FRM_CTL"          ,       0x1180010001018ull,  CVMX_CSR_DB_TYPE_RSL,   64, 129},
    {"GMX1_RX003_FRM_CTL"          ,       0x1180010001818ull,  CVMX_CSR_DB_TYPE_RSL,   64, 129},
    {"GMX1_RX000_IFG"              ,       0x1180010000058ull,  CVMX_CSR_DB_TYPE_RSL,   64, 130},
    {"GMX1_RX001_IFG"              ,       0x1180010000858ull,  CVMX_CSR_DB_TYPE_RSL,   64, 130},
    {"GMX1_RX002_IFG"              ,       0x1180010001058ull,  CVMX_CSR_DB_TYPE_RSL,   64, 130},
    {"GMX1_RX003_IFG"              ,       0x1180010001858ull,  CVMX_CSR_DB_TYPE_RSL,   64, 130},
    {"GMX1_RX000_INT_EN"           ,       0x1180010000008ull,  CVMX_CSR_DB_TYPE_RSL,   64, 131},
    {"GMX1_RX001_INT_EN"           ,       0x1180010000808ull,  CVMX_CSR_DB_TYPE_RSL,   64, 131},
    {"GMX1_RX002_INT_EN"           ,       0x1180010001008ull,  CVMX_CSR_DB_TYPE_RSL,   64, 131},
    {"GMX1_RX003_INT_EN"           ,       0x1180010001808ull,  CVMX_CSR_DB_TYPE_RSL,   64, 131},
    {"GMX1_RX000_INT_REG"          ,       0x1180010000000ull,  CVMX_CSR_DB_TYPE_RSL,   64, 132},
    {"GMX1_RX001_INT_REG"          ,       0x1180010000800ull,  CVMX_CSR_DB_TYPE_RSL,   64, 132},
    {"GMX1_RX002_INT_REG"          ,       0x1180010001000ull,  CVMX_CSR_DB_TYPE_RSL,   64, 132},
    {"GMX1_RX003_INT_REG"          ,       0x1180010001800ull,  CVMX_CSR_DB_TYPE_RSL,   64, 132},
    {"GMX1_RX000_JABBER"           ,       0x1180010000038ull,  CVMX_CSR_DB_TYPE_RSL,   64, 133},
    {"GMX1_RX001_JABBER"           ,       0x1180010000838ull,  CVMX_CSR_DB_TYPE_RSL,   64, 133},
    {"GMX1_RX002_JABBER"           ,       0x1180010001038ull,  CVMX_CSR_DB_TYPE_RSL,   64, 133},
    {"GMX1_RX003_JABBER"           ,       0x1180010001838ull,  CVMX_CSR_DB_TYPE_RSL,   64, 133},
    {"GMX1_RX000_PAUSE_DROP_TIME"  ,       0x1180010000068ull,  CVMX_CSR_DB_TYPE_RSL,   64, 134},
    {"GMX1_RX001_PAUSE_DROP_TIME"  ,       0x1180010000868ull,  CVMX_CSR_DB_TYPE_RSL,   64, 134},
    {"GMX1_RX002_PAUSE_DROP_TIME"  ,       0x1180010001068ull,  CVMX_CSR_DB_TYPE_RSL,   64, 134},
    {"GMX1_RX003_PAUSE_DROP_TIME"  ,       0x1180010001868ull,  CVMX_CSR_DB_TYPE_RSL,   64, 134},
    {"GMX1_RX000_STATS_CTL"        ,       0x1180010000050ull,  CVMX_CSR_DB_TYPE_RSL,   64, 135},
    {"GMX1_RX001_STATS_CTL"        ,       0x1180010000850ull,  CVMX_CSR_DB_TYPE_RSL,   64, 135},
    {"GMX1_RX002_STATS_CTL"        ,       0x1180010001050ull,  CVMX_CSR_DB_TYPE_RSL,   64, 135},
    {"GMX1_RX003_STATS_CTL"        ,       0x1180010001850ull,  CVMX_CSR_DB_TYPE_RSL,   64, 135},
    {"GMX1_RX000_STATS_OCTS"       ,       0x1180010000088ull,  CVMX_CSR_DB_TYPE_RSL,   64, 136},
    {"GMX1_RX001_STATS_OCTS"       ,       0x1180010000888ull,  CVMX_CSR_DB_TYPE_RSL,   64, 136},
    {"GMX1_RX002_STATS_OCTS"       ,       0x1180010001088ull,  CVMX_CSR_DB_TYPE_RSL,   64, 136},
    {"GMX1_RX003_STATS_OCTS"       ,       0x1180010001888ull,  CVMX_CSR_DB_TYPE_RSL,   64, 136},
    {"GMX1_RX000_STATS_OCTS_CTL"   ,       0x1180010000098ull,  CVMX_CSR_DB_TYPE_RSL,   64, 137},
    {"GMX1_RX001_STATS_OCTS_CTL"   ,       0x1180010000898ull,  CVMX_CSR_DB_TYPE_RSL,   64, 137},
    {"GMX1_RX002_STATS_OCTS_CTL"   ,       0x1180010001098ull,  CVMX_CSR_DB_TYPE_RSL,   64, 137},
    {"GMX1_RX003_STATS_OCTS_CTL"   ,       0x1180010001898ull,  CVMX_CSR_DB_TYPE_RSL,   64, 137},
    {"GMX1_RX000_STATS_OCTS_DMAC"  ,       0x11800100000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 138},
    {"GMX1_RX001_STATS_OCTS_DMAC"  ,       0x11800100008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 138},
    {"GMX1_RX002_STATS_OCTS_DMAC"  ,       0x11800100010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 138},
    {"GMX1_RX003_STATS_OCTS_DMAC"  ,       0x11800100018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 138},
    {"GMX1_RX000_STATS_OCTS_DRP"   ,       0x11800100000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX1_RX001_STATS_OCTS_DRP"   ,       0x11800100008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX1_RX002_STATS_OCTS_DRP"   ,       0x11800100010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX1_RX003_STATS_OCTS_DRP"   ,       0x11800100018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX1_RX000_STATS_PKTS"       ,       0x1180010000080ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX1_RX001_STATS_PKTS"       ,       0x1180010000880ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX1_RX002_STATS_PKTS"       ,       0x1180010001080ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX1_RX003_STATS_PKTS"       ,       0x1180010001880ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX1_RX000_STATS_PKTS_BAD"   ,       0x11800100000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX1_RX001_STATS_PKTS_BAD"   ,       0x11800100008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX1_RX002_STATS_PKTS_BAD"   ,       0x11800100010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX1_RX003_STATS_PKTS_BAD"   ,       0x11800100018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX1_RX000_STATS_PKTS_CTL"   ,       0x1180010000090ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX1_RX001_STATS_PKTS_CTL"   ,       0x1180010000890ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX1_RX002_STATS_PKTS_CTL"   ,       0x1180010001090ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX1_RX003_STATS_PKTS_CTL"   ,       0x1180010001890ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX1_RX000_STATS_PKTS_DMAC"  ,       0x11800100000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX1_RX001_STATS_PKTS_DMAC"  ,       0x11800100008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX1_RX002_STATS_PKTS_DMAC"  ,       0x11800100010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX1_RX003_STATS_PKTS_DMAC"  ,       0x11800100018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX1_RX000_STATS_PKTS_DRP"   ,       0x11800100000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 144},
    {"GMX1_RX001_STATS_PKTS_DRP"   ,       0x11800100008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 144},
    {"GMX1_RX002_STATS_PKTS_DRP"   ,       0x11800100010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 144},
    {"GMX1_RX003_STATS_PKTS_DRP"   ,       0x11800100018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 144},
    {"GMX1_RX000_UDD_SKP"          ,       0x1180010000048ull,  CVMX_CSR_DB_TYPE_RSL,   64, 145},
    {"GMX1_RX001_UDD_SKP"          ,       0x1180010000848ull,  CVMX_CSR_DB_TYPE_RSL,   64, 145},
    {"GMX1_RX002_UDD_SKP"          ,       0x1180010001048ull,  CVMX_CSR_DB_TYPE_RSL,   64, 145},
    {"GMX1_RX003_UDD_SKP"          ,       0x1180010001848ull,  CVMX_CSR_DB_TYPE_RSL,   64, 145},
    {"GMX1_RX_BP_DROP000"          ,       0x1180010000420ull,  CVMX_CSR_DB_TYPE_RSL,   64, 146},
    {"GMX1_RX_BP_DROP001"          ,       0x1180010000428ull,  CVMX_CSR_DB_TYPE_RSL,   64, 146},
    {"GMX1_RX_BP_DROP002"          ,       0x1180010000430ull,  CVMX_CSR_DB_TYPE_RSL,   64, 146},
    {"GMX1_RX_BP_DROP003"          ,       0x1180010000438ull,  CVMX_CSR_DB_TYPE_RSL,   64, 146},
    {"GMX1_RX_BP_OFF000"           ,       0x1180010000460ull,  CVMX_CSR_DB_TYPE_RSL,   64, 147},
    {"GMX1_RX_BP_OFF001"           ,       0x1180010000468ull,  CVMX_CSR_DB_TYPE_RSL,   64, 147},
    {"GMX1_RX_BP_OFF002"           ,       0x1180010000470ull,  CVMX_CSR_DB_TYPE_RSL,   64, 147},
    {"GMX1_RX_BP_OFF003"           ,       0x1180010000478ull,  CVMX_CSR_DB_TYPE_RSL,   64, 147},
    {"GMX1_RX_BP_ON000"            ,       0x1180010000440ull,  CVMX_CSR_DB_TYPE_RSL,   64, 148},
    {"GMX1_RX_BP_ON001"            ,       0x1180010000448ull,  CVMX_CSR_DB_TYPE_RSL,   64, 148},
    {"GMX1_RX_BP_ON002"            ,       0x1180010000450ull,  CVMX_CSR_DB_TYPE_RSL,   64, 148},
    {"GMX1_RX_BP_ON003"            ,       0x1180010000458ull,  CVMX_CSR_DB_TYPE_RSL,   64, 148},
    {"GMX1_RX_HG2_STATUS"          ,       0x1180010000548ull,  CVMX_CSR_DB_TYPE_RSL,   64, 149},
    {"GMX1_RX_PRT_INFO"            ,       0x11800100004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 150},
    {"GMX1_RX_PRTS"                ,       0x1180010000410ull,  CVMX_CSR_DB_TYPE_RSL,   64, 151},
    {"GMX1_RX_XAUI_BAD_COL"        ,       0x1180010000538ull,  CVMX_CSR_DB_TYPE_RSL,   64, 152},
    {"GMX1_RX_XAUI_CTL"            ,       0x1180010000530ull,  CVMX_CSR_DB_TYPE_RSL,   64, 153},
    {"GMX1_SMAC000"                ,       0x1180010000230ull,  CVMX_CSR_DB_TYPE_RSL,   64, 154},
    {"GMX1_SMAC001"                ,       0x1180010000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64, 154},
    {"GMX1_SMAC002"                ,       0x1180010001230ull,  CVMX_CSR_DB_TYPE_RSL,   64, 154},
    {"GMX1_SMAC003"                ,       0x1180010001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64, 154},
    {"GMX1_STAT_BP"                ,       0x1180010000520ull,  CVMX_CSR_DB_TYPE_RSL,   64, 155},
    {"GMX1_TX000_APPEND"           ,       0x1180010000218ull,  CVMX_CSR_DB_TYPE_RSL,   64, 156},
    {"GMX1_TX001_APPEND"           ,       0x1180010000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64, 156},
    {"GMX1_TX002_APPEND"           ,       0x1180010001218ull,  CVMX_CSR_DB_TYPE_RSL,   64, 156},
    {"GMX1_TX003_APPEND"           ,       0x1180010001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64, 156},
    {"GMX1_TX000_BURST"            ,       0x1180010000228ull,  CVMX_CSR_DB_TYPE_RSL,   64, 157},
    {"GMX1_TX001_BURST"            ,       0x1180010000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64, 157},
    {"GMX1_TX002_BURST"            ,       0x1180010001228ull,  CVMX_CSR_DB_TYPE_RSL,   64, 157},
    {"GMX1_TX003_BURST"            ,       0x1180010001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64, 157},
    {"GMX1_TX000_CTL"              ,       0x1180010000270ull,  CVMX_CSR_DB_TYPE_RSL,   64, 158},
    {"GMX1_TX001_CTL"              ,       0x1180010000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64, 158},
    {"GMX1_TX002_CTL"              ,       0x1180010001270ull,  CVMX_CSR_DB_TYPE_RSL,   64, 158},
    {"GMX1_TX003_CTL"              ,       0x1180010001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64, 158},
    {"GMX1_TX000_MIN_PKT"          ,       0x1180010000240ull,  CVMX_CSR_DB_TYPE_RSL,   64, 159},
    {"GMX1_TX001_MIN_PKT"          ,       0x1180010000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64, 159},
    {"GMX1_TX002_MIN_PKT"          ,       0x1180010001240ull,  CVMX_CSR_DB_TYPE_RSL,   64, 159},
    {"GMX1_TX003_MIN_PKT"          ,       0x1180010001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64, 159},
    {"GMX1_TX000_PAUSE_PKT_INTERVAL",      0x1180010000248ull,  CVMX_CSR_DB_TYPE_RSL,   64, 160},
    {"GMX1_TX001_PAUSE_PKT_INTERVAL",      0x1180010000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64, 160},
    {"GMX1_TX002_PAUSE_PKT_INTERVAL",      0x1180010001248ull,  CVMX_CSR_DB_TYPE_RSL,   64, 160},
    {"GMX1_TX003_PAUSE_PKT_INTERVAL",      0x1180010001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64, 160},
    {"GMX1_TX000_PAUSE_PKT_TIME"   ,       0x1180010000238ull,  CVMX_CSR_DB_TYPE_RSL,   64, 161},
    {"GMX1_TX001_PAUSE_PKT_TIME"   ,       0x1180010000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64, 161},
    {"GMX1_TX002_PAUSE_PKT_TIME"   ,       0x1180010001238ull,  CVMX_CSR_DB_TYPE_RSL,   64, 161},
    {"GMX1_TX003_PAUSE_PKT_TIME"   ,       0x1180010001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64, 161},
    {"GMX1_TX000_PAUSE_TOGO"       ,       0x1180010000258ull,  CVMX_CSR_DB_TYPE_RSL,   64, 162},
    {"GMX1_TX001_PAUSE_TOGO"       ,       0x1180010000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64, 162},
    {"GMX1_TX002_PAUSE_TOGO"       ,       0x1180010001258ull,  CVMX_CSR_DB_TYPE_RSL,   64, 162},
    {"GMX1_TX003_PAUSE_TOGO"       ,       0x1180010001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64, 162},
    {"GMX1_TX000_PAUSE_ZERO"       ,       0x1180010000260ull,  CVMX_CSR_DB_TYPE_RSL,   64, 163},
    {"GMX1_TX001_PAUSE_ZERO"       ,       0x1180010000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64, 163},
    {"GMX1_TX002_PAUSE_ZERO"       ,       0x1180010001260ull,  CVMX_CSR_DB_TYPE_RSL,   64, 163},
    {"GMX1_TX003_PAUSE_ZERO"       ,       0x1180010001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64, 163},
    {"GMX1_TX000_SGMII_CTL"        ,       0x1180010000300ull,  CVMX_CSR_DB_TYPE_RSL,   64, 164},
    {"GMX1_TX001_SGMII_CTL"        ,       0x1180010000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64, 164},
    {"GMX1_TX002_SGMII_CTL"        ,       0x1180010001300ull,  CVMX_CSR_DB_TYPE_RSL,   64, 164},
    {"GMX1_TX003_SGMII_CTL"        ,       0x1180010001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64, 164},
    {"GMX1_TX000_SLOT"             ,       0x1180010000220ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX1_TX001_SLOT"             ,       0x1180010000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX1_TX002_SLOT"             ,       0x1180010001220ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX1_TX003_SLOT"             ,       0x1180010001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX1_TX000_SOFT_PAUSE"       ,       0x1180010000250ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX1_TX001_SOFT_PAUSE"       ,       0x1180010000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX1_TX002_SOFT_PAUSE"       ,       0x1180010001250ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX1_TX003_SOFT_PAUSE"       ,       0x1180010001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX1_TX000_STAT0"            ,       0x1180010000280ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX1_TX001_STAT0"            ,       0x1180010000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX1_TX002_STAT0"            ,       0x1180010001280ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX1_TX003_STAT0"            ,       0x1180010001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX1_TX000_STAT1"            ,       0x1180010000288ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX1_TX001_STAT1"            ,       0x1180010000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX1_TX002_STAT1"            ,       0x1180010001288ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX1_TX003_STAT1"            ,       0x1180010001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX1_TX000_STAT2"            ,       0x1180010000290ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX1_TX001_STAT2"            ,       0x1180010000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX1_TX002_STAT2"            ,       0x1180010001290ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX1_TX003_STAT2"            ,       0x1180010001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX1_TX000_STAT3"            ,       0x1180010000298ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX1_TX001_STAT3"            ,       0x1180010000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX1_TX002_STAT3"            ,       0x1180010001298ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX1_TX003_STAT3"            ,       0x1180010001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX1_TX000_STAT4"            ,       0x11800100002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX1_TX001_STAT4"            ,       0x1180010000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX1_TX002_STAT4"            ,       0x11800100012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX1_TX003_STAT4"            ,       0x1180010001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX1_TX000_STAT5"            ,       0x11800100002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX1_TX001_STAT5"            ,       0x1180010000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX1_TX002_STAT5"            ,       0x11800100012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX1_TX003_STAT5"            ,       0x1180010001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX1_TX000_STAT6"            ,       0x11800100002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX1_TX001_STAT6"            ,       0x1180010000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX1_TX002_STAT6"            ,       0x11800100012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX1_TX003_STAT6"            ,       0x1180010001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX1_TX000_STAT7"            ,       0x11800100002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX1_TX001_STAT7"            ,       0x1180010000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX1_TX002_STAT7"            ,       0x11800100012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX1_TX003_STAT7"            ,       0x1180010001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX1_TX000_STAT8"            ,       0x11800100002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX1_TX001_STAT8"            ,       0x1180010000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX1_TX002_STAT8"            ,       0x11800100012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX1_TX003_STAT8"            ,       0x1180010001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX1_TX000_STAT9"            ,       0x11800100002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 176},
    {"GMX1_TX001_STAT9"            ,       0x1180010000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 176},
    {"GMX1_TX002_STAT9"            ,       0x11800100012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 176},
    {"GMX1_TX003_STAT9"            ,       0x1180010001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 176},
    {"GMX1_TX000_STATS_CTL"        ,       0x1180010000268ull,  CVMX_CSR_DB_TYPE_RSL,   64, 177},
    {"GMX1_TX001_STATS_CTL"        ,       0x1180010000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64, 177},
    {"GMX1_TX002_STATS_CTL"        ,       0x1180010001268ull,  CVMX_CSR_DB_TYPE_RSL,   64, 177},
    {"GMX1_TX003_STATS_CTL"        ,       0x1180010001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64, 177},
    {"GMX1_TX000_THRESH"           ,       0x1180010000210ull,  CVMX_CSR_DB_TYPE_RSL,   64, 178},
    {"GMX1_TX001_THRESH"           ,       0x1180010000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64, 178},
    {"GMX1_TX002_THRESH"           ,       0x1180010001210ull,  CVMX_CSR_DB_TYPE_RSL,   64, 178},
    {"GMX1_TX003_THRESH"           ,       0x1180010001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64, 178},
    {"GMX1_TX_BP"                  ,       0x11800100004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 179},
    {"GMX1_TX_COL_ATTEMPT"         ,       0x1180010000498ull,  CVMX_CSR_DB_TYPE_RSL,   64, 180},
    {"GMX1_TX_CORRUPT"             ,       0x11800100004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 181},
    {"GMX1_TX_HG2_REG1"            ,       0x1180010000558ull,  CVMX_CSR_DB_TYPE_RSL,   64, 182},
    {"GMX1_TX_HG2_REG2"            ,       0x1180010000560ull,  CVMX_CSR_DB_TYPE_RSL,   64, 183},
    {"GMX1_TX_IFG"                 ,       0x1180010000488ull,  CVMX_CSR_DB_TYPE_RSL,   64, 184},
    {"GMX1_TX_INT_EN"              ,       0x1180010000508ull,  CVMX_CSR_DB_TYPE_RSL,   64, 185},
    {"GMX1_TX_INT_REG"             ,       0x1180010000500ull,  CVMX_CSR_DB_TYPE_RSL,   64, 186},
    {"GMX1_TX_JAM"                 ,       0x1180010000490ull,  CVMX_CSR_DB_TYPE_RSL,   64, 187},
    {"GMX1_TX_LFSR"                ,       0x11800100004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 188},
    {"GMX1_TX_OVR_BP"              ,       0x11800100004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 189},
    {"GMX1_TX_PAUSE_PKT_DMAC"      ,       0x11800100004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 190},
    {"GMX1_TX_PAUSE_PKT_TYPE"      ,       0x11800100004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 191},
    {"GMX1_TX_PRTS"                ,       0x1180010000480ull,  CVMX_CSR_DB_TYPE_RSL,   64, 192},
    {"GMX1_TX_XAUI_CTL"            ,       0x1180010000528ull,  CVMX_CSR_DB_TYPE_RSL,   64, 193},
    {"GMX1_XAUI_EXT_LOOPBACK"      ,       0x1180010000540ull,  CVMX_CSR_DB_TYPE_RSL,   64, 194},

#if defined(CONFIG_OCTEON_SGMII_DUAL)
    {"GMX0_BAD_REG"                ,       0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64, 112},
    {"GMX0_BIST"                   ,       0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64, 113},
    {"GMX0_CLK_EN"                 ,       0x11800080007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 114},
    {"GMX0_HG2_CONTROL"            ,       0x1180008000550ull,  CVMX_CSR_DB_TYPE_RSL,   64, 115},
    {"GMX0_INF_MODE"               ,       0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 116},
    {"GMX0_NXA_ADR"                ,       0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64, 117},
    {"GMX0_PRT000_CFG"             ,       0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64, 118},
    {"GMX0_PRT001_CFG"             ,       0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64, 118},
    {"GMX0_PRT002_CFG"             ,       0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64, 118},
    {"GMX0_PRT003_CFG"             ,       0x1180008001810ull,  CVMX_CSR_DB_TYPE_RSL,   64, 118},
    {"GMX0_RX000_ADR_CAM0"         ,       0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64, 119},
    {"GMX0_RX001_ADR_CAM0"         ,       0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64, 119},
    {"GMX0_RX002_ADR_CAM0"         ,       0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64, 119},
    {"GMX0_RX003_ADR_CAM0"         ,       0x1180008001980ull,  CVMX_CSR_DB_TYPE_RSL,   64, 119},
    {"GMX0_RX000_ADR_CAM1"         ,       0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64, 120},
    {"GMX0_RX001_ADR_CAM1"         ,       0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64, 120},
    {"GMX0_RX002_ADR_CAM1"         ,       0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64, 120},
    {"GMX0_RX003_ADR_CAM1"         ,       0x1180008001988ull,  CVMX_CSR_DB_TYPE_RSL,   64, 120},
    {"GMX0_RX000_ADR_CAM2"         ,       0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64, 121},
    {"GMX0_RX001_ADR_CAM2"         ,       0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64, 121},
    {"GMX0_RX002_ADR_CAM2"         ,       0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64, 121},
    {"GMX0_RX003_ADR_CAM2"         ,       0x1180008001990ull,  CVMX_CSR_DB_TYPE_RSL,   64, 121},
    {"GMX0_RX000_ADR_CAM3"         ,       0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64, 122},
    {"GMX0_RX001_ADR_CAM3"         ,       0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64, 122},
    {"GMX0_RX002_ADR_CAM3"         ,       0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64, 122},
    {"GMX0_RX003_ADR_CAM3"         ,       0x1180008001998ull,  CVMX_CSR_DB_TYPE_RSL,   64, 122},
    {"GMX0_RX000_ADR_CAM4"         ,       0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 123},
    {"GMX0_RX001_ADR_CAM4"         ,       0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 123},
    {"GMX0_RX002_ADR_CAM4"         ,       0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 123},
    {"GMX0_RX003_ADR_CAM4"         ,       0x11800080019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 123},
    {"GMX0_RX000_ADR_CAM5"         ,       0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 124},
    {"GMX0_RX001_ADR_CAM5"         ,       0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 124},
    {"GMX0_RX002_ADR_CAM5"         ,       0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 124},
    {"GMX0_RX003_ADR_CAM5"         ,       0x11800080019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 124},
    {"GMX0_RX000_ADR_CAM_EN"       ,       0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64, 125},
    {"GMX0_RX001_ADR_CAM_EN"       ,       0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64, 125},
    {"GMX0_RX002_ADR_CAM_EN"       ,       0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64, 125},
    {"GMX0_RX003_ADR_CAM_EN"       ,       0x1180008001908ull,  CVMX_CSR_DB_TYPE_RSL,   64, 125},
    {"GMX0_RX000_ADR_CTL"          ,       0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64, 126},
    {"GMX0_RX001_ADR_CTL"          ,       0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64, 126},
    {"GMX0_RX002_ADR_CTL"          ,       0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64, 126},
    {"GMX0_RX003_ADR_CTL"          ,       0x1180008001900ull,  CVMX_CSR_DB_TYPE_RSL,   64, 126},
    {"GMX0_RX000_DECISION"         ,       0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64, 127},
    {"GMX0_RX001_DECISION"         ,       0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64, 127},
    {"GMX0_RX002_DECISION"         ,       0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64, 127},
    {"GMX0_RX003_DECISION"         ,       0x1180008001840ull,  CVMX_CSR_DB_TYPE_RSL,   64, 127},
    {"GMX0_RX000_FRM_CHK"          ,       0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64, 128},
    {"GMX0_RX001_FRM_CHK"          ,       0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64, 128},
    {"GMX0_RX002_FRM_CHK"          ,       0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64, 128},
    {"GMX0_RX003_FRM_CHK"          ,       0x1180008001820ull,  CVMX_CSR_DB_TYPE_RSL,   64, 128},
    {"GMX0_RX000_FRM_CTL"          ,       0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64, 129},
    {"GMX0_RX001_FRM_CTL"          ,       0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64, 129},
    {"GMX0_RX002_FRM_CTL"          ,       0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64, 129},
    {"GMX0_RX003_FRM_CTL"          ,       0x1180008001818ull,  CVMX_CSR_DB_TYPE_RSL,   64, 129},
    {"GMX0_RX000_IFG"              ,       0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64, 130},
    {"GMX0_RX001_IFG"              ,       0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64, 130},
    {"GMX0_RX002_IFG"              ,       0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64, 130},
    {"GMX0_RX003_IFG"              ,       0x1180008001858ull,  CVMX_CSR_DB_TYPE_RSL,   64, 130},
    {"GMX0_RX000_INT_EN"           ,       0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64, 131},
    {"GMX0_RX001_INT_EN"           ,       0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64, 131},
    {"GMX0_RX002_INT_EN"           ,       0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64, 131},
    {"GMX0_RX003_INT_EN"           ,       0x1180008001808ull,  CVMX_CSR_DB_TYPE_RSL,   64, 131},
    {"GMX0_RX000_INT_REG"          ,       0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64, 132},
    {"GMX0_RX001_INT_REG"          ,       0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64, 132},
    {"GMX0_RX002_INT_REG"          ,       0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64, 132},
    {"GMX0_RX003_INT_REG"          ,       0x1180008001800ull,  CVMX_CSR_DB_TYPE_RSL,   64, 132},
    {"GMX0_RX000_JABBER"           ,       0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64, 133},
    {"GMX0_RX001_JABBER"           ,       0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64, 133},
    {"GMX0_RX002_JABBER"           ,       0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64, 133},
    {"GMX0_RX003_JABBER"           ,       0x1180008001838ull,  CVMX_CSR_DB_TYPE_RSL,   64, 133},
    {"GMX0_RX000_PAUSE_DROP_TIME"  ,       0x1180008000068ull,  CVMX_CSR_DB_TYPE_RSL,   64, 134},
    {"GMX0_RX001_PAUSE_DROP_TIME"  ,       0x1180008000868ull,  CVMX_CSR_DB_TYPE_RSL,   64, 134},
    {"GMX0_RX002_PAUSE_DROP_TIME"  ,       0x1180008001068ull,  CVMX_CSR_DB_TYPE_RSL,   64, 134},
    {"GMX0_RX003_PAUSE_DROP_TIME"  ,       0x1180008001868ull,  CVMX_CSR_DB_TYPE_RSL,   64, 134},
    {"GMX0_RX000_STATS_CTL"        ,       0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64, 135},
    {"GMX0_RX001_STATS_CTL"        ,       0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64, 135},
    {"GMX0_RX002_STATS_CTL"        ,       0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64, 135},
    {"GMX0_RX003_STATS_CTL"        ,       0x1180008001850ull,  CVMX_CSR_DB_TYPE_RSL,   64, 135},
    {"GMX0_RX000_STATS_OCTS"       ,       0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64, 136},
    {"GMX0_RX001_STATS_OCTS"       ,       0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64, 136},
    {"GMX0_RX002_STATS_OCTS"       ,       0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64, 136},
    {"GMX0_RX003_STATS_OCTS"       ,       0x1180008001888ull,  CVMX_CSR_DB_TYPE_RSL,   64, 136},
    {"GMX0_RX000_STATS_OCTS_CTL"   ,       0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64, 137},
    {"GMX0_RX001_STATS_OCTS_CTL"   ,       0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64, 137},
    {"GMX0_RX002_STATS_OCTS_CTL"   ,       0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64, 137},
    {"GMX0_RX003_STATS_OCTS_CTL"   ,       0x1180008001898ull,  CVMX_CSR_DB_TYPE_RSL,   64, 137},
    {"GMX0_RX000_STATS_OCTS_DMAC"  ,       0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 138},
    {"GMX0_RX001_STATS_OCTS_DMAC"  ,       0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 138},
    {"GMX0_RX002_STATS_OCTS_DMAC"  ,       0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 138},
    {"GMX0_RX003_STATS_OCTS_DMAC"  ,       0x11800080018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 138},
    {"GMX0_RX000_STATS_OCTS_DRP"   ,       0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX0_RX001_STATS_OCTS_DRP"   ,       0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX0_RX002_STATS_OCTS_DRP"   ,       0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX0_RX003_STATS_OCTS_DRP"   ,       0x11800080018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 139},
    {"GMX0_RX000_STATS_PKTS"       ,       0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX0_RX001_STATS_PKTS"       ,       0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX0_RX002_STATS_PKTS"       ,       0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX0_RX003_STATS_PKTS"       ,       0x1180008001880ull,  CVMX_CSR_DB_TYPE_RSL,   64, 140},
    {"GMX0_RX000_STATS_PKTS_BAD"   ,       0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX0_RX001_STATS_PKTS_BAD"   ,       0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX0_RX002_STATS_PKTS_BAD"   ,       0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX0_RX003_STATS_PKTS_BAD"   ,       0x11800080018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 141},
    {"GMX0_RX000_STATS_PKTS_CTL"   ,       0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX0_RX001_STATS_PKTS_CTL"   ,       0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX0_RX002_STATS_PKTS_CTL"   ,       0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX0_RX003_STATS_PKTS_CTL"   ,       0x1180008001890ull,  CVMX_CSR_DB_TYPE_RSL,   64, 142},
    {"GMX0_RX000_STATS_PKTS_DMAC"  ,       0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX0_RX001_STATS_PKTS_DMAC"  ,       0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX0_RX002_STATS_PKTS_DMAC"  ,       0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX0_RX003_STATS_PKTS_DMAC"  ,       0x11800080018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 143},
    {"GMX0_RX000_STATS_PKTS_DRP"   ,       0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 144},
    {"GMX0_RX001_STATS_PKTS_DRP"   ,       0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 144},
    {"GMX0_RX002_STATS_PKTS_DRP"   ,       0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 144},
    {"GMX0_RX003_STATS_PKTS_DRP"   ,       0x11800080018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 144},
    {"GMX0_RX000_UDD_SKP"          ,       0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64, 145},
    {"GMX0_RX001_UDD_SKP"          ,       0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64, 145},
    {"GMX0_RX002_UDD_SKP"          ,       0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64, 145},
    {"GMX0_RX003_UDD_SKP"          ,       0x1180008001848ull,  CVMX_CSR_DB_TYPE_RSL,   64, 145},
    {"GMX0_RX_BP_DROP000"          ,       0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64, 146},
    {"GMX0_RX_BP_DROP001"          ,       0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64, 146},
    {"GMX0_RX_BP_DROP002"          ,       0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64, 146},
    {"GMX0_RX_BP_DROP003"          ,       0x1180008000438ull,  CVMX_CSR_DB_TYPE_RSL,   64, 146},
    {"GMX0_RX_BP_OFF000"           ,       0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64, 147},
    {"GMX0_RX_BP_OFF001"           ,       0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64, 147},
    {"GMX0_RX_BP_OFF002"           ,       0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64, 147},
    {"GMX0_RX_BP_OFF003"           ,       0x1180008000478ull,  CVMX_CSR_DB_TYPE_RSL,   64, 147},
    {"GMX0_RX_BP_ON000"            ,       0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64, 148},
    {"GMX0_RX_BP_ON001"            ,       0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64, 148},
    {"GMX0_RX_BP_ON002"            ,       0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64, 148},
    {"GMX0_RX_BP_ON003"            ,       0x1180008000458ull,  CVMX_CSR_DB_TYPE_RSL,   64, 148},
    {"GMX0_RX_HG2_STATUS"          ,       0x1180008000548ull,  CVMX_CSR_DB_TYPE_RSL,   64, 149},
    {"GMX0_RX_PRT_INFO"            ,       0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 150},
    {"GMX0_RX_PRTS"                ,       0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64, 151},
    {"GMX0_RX_XAUI_BAD_COL"        ,       0x1180008000538ull,  CVMX_CSR_DB_TYPE_RSL,   64, 152},
    {"GMX0_RX_XAUI_CTL"            ,       0x1180008000530ull,  CVMX_CSR_DB_TYPE_RSL,   64, 153},
    {"GMX0_SMAC000"                ,       0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64, 154},
    {"GMX0_SMAC001"                ,       0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64, 154},
    {"GMX0_SMAC002"                ,       0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64, 154},
    {"GMX0_SMAC003"                ,       0x1180008001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64, 154},
    {"GMX0_STAT_BP"                ,       0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64, 155},
    {"GMX0_TX000_APPEND"           ,       0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64, 156},
    {"GMX0_TX001_APPEND"           ,       0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64, 156},
    {"GMX0_TX002_APPEND"           ,       0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64, 156},
    {"GMX0_TX003_APPEND"           ,       0x1180008001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64, 156},
    {"GMX0_TX000_BURST"            ,       0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64, 157},
    {"GMX0_TX001_BURST"            ,       0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64, 157},
    {"GMX0_TX002_BURST"            ,       0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64, 157},
    {"GMX0_TX003_BURST"            ,       0x1180008001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64, 157},
    {"GMX0_TX000_CTL"              ,       0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64, 158},
    {"GMX0_TX001_CTL"              ,       0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64, 158},
    {"GMX0_TX002_CTL"              ,       0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64, 158},
    {"GMX0_TX003_CTL"              ,       0x1180008001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64, 158},
    {"GMX0_TX000_MIN_PKT"          ,       0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64, 159},
    {"GMX0_TX001_MIN_PKT"          ,       0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64, 159},
    {"GMX0_TX002_MIN_PKT"          ,       0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64, 159},
    {"GMX0_TX003_MIN_PKT"          ,       0x1180008001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64, 159},
    {"GMX0_TX000_PAUSE_PKT_INTERVAL",      0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64, 160},
    {"GMX0_TX001_PAUSE_PKT_INTERVAL",      0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64, 160},
    {"GMX0_TX002_PAUSE_PKT_INTERVAL",      0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64, 160},
    {"GMX0_TX003_PAUSE_PKT_INTERVAL",      0x1180008001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64, 160},
    {"GMX0_TX000_PAUSE_PKT_TIME"   ,       0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64, 161},
    {"GMX0_TX001_PAUSE_PKT_TIME"   ,       0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64, 161},
    {"GMX0_TX002_PAUSE_PKT_TIME"   ,       0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64, 161},
    {"GMX0_TX003_PAUSE_PKT_TIME"   ,       0x1180008001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64, 161},
    {"GMX0_TX000_PAUSE_TOGO"       ,       0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64, 162},
    {"GMX0_TX001_PAUSE_TOGO"       ,       0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64, 162},
    {"GMX0_TX002_PAUSE_TOGO"       ,       0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64, 162},
    {"GMX0_TX003_PAUSE_TOGO"       ,       0x1180008001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64, 162},
    {"GMX0_TX000_PAUSE_ZERO"       ,       0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64, 163},
    {"GMX0_TX001_PAUSE_ZERO"       ,       0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64, 163},
    {"GMX0_TX002_PAUSE_ZERO"       ,       0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64, 163},
    {"GMX0_TX003_PAUSE_ZERO"       ,       0x1180008001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64, 163},
    {"GMX0_TX000_SGMII_CTL"        ,       0x1180008000300ull,  CVMX_CSR_DB_TYPE_RSL,   64, 164},
    {"GMX0_TX001_SGMII_CTL"        ,       0x1180008000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64, 164},
    {"GMX0_TX002_SGMII_CTL"        ,       0x1180008001300ull,  CVMX_CSR_DB_TYPE_RSL,   64, 164},
    {"GMX0_TX003_SGMII_CTL"        ,       0x1180008001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64, 164},
    {"GMX0_TX000_SLOT"             ,       0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX0_TX001_SLOT"             ,       0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX0_TX002_SLOT"             ,       0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX0_TX003_SLOT"             ,       0x1180008001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64, 165},
    {"GMX0_TX000_SOFT_PAUSE"       ,       0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX0_TX001_SOFT_PAUSE"       ,       0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX0_TX002_SOFT_PAUSE"       ,       0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX0_TX003_SOFT_PAUSE"       ,       0x1180008001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64, 166},
    {"GMX0_TX000_STAT0"            ,       0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX0_TX001_STAT0"            ,       0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX0_TX002_STAT0"            ,       0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX0_TX003_STAT0"            ,       0x1180008001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64, 167},
    {"GMX0_TX000_STAT1"            ,       0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX0_TX001_STAT1"            ,       0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX0_TX002_STAT1"            ,       0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX0_TX003_STAT1"            ,       0x1180008001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64, 168},
    {"GMX0_TX000_STAT2"            ,       0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX0_TX001_STAT2"            ,       0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX0_TX002_STAT2"            ,       0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX0_TX003_STAT2"            ,       0x1180008001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64, 169},
    {"GMX0_TX000_STAT3"            ,       0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX0_TX001_STAT3"            ,       0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX0_TX002_STAT3"            ,       0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX0_TX003_STAT3"            ,       0x1180008001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64, 170},
    {"GMX0_TX000_STAT4"            ,       0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX0_TX001_STAT4"            ,       0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX0_TX002_STAT4"            ,       0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX0_TX003_STAT4"            ,       0x1180008001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 171},
    {"GMX0_TX000_STAT5"            ,       0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX0_TX001_STAT5"            ,       0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX0_TX002_STAT5"            ,       0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX0_TX003_STAT5"            ,       0x1180008001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 172},
    {"GMX0_TX000_STAT6"            ,       0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX0_TX001_STAT6"            ,       0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX0_TX002_STAT6"            ,       0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX0_TX003_STAT6"            ,       0x1180008001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 173},
    {"GMX0_TX000_STAT7"            ,       0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX0_TX001_STAT7"            ,       0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX0_TX002_STAT7"            ,       0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX0_TX003_STAT7"            ,       0x1180008001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 174},
    {"GMX0_TX000_STAT8"            ,       0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX0_TX001_STAT8"            ,       0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX0_TX002_STAT8"            ,       0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX0_TX003_STAT8"            ,       0x1180008001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 175},
    {"GMX0_TX000_STAT9"            ,       0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 176},
    {"GMX0_TX001_STAT9"            ,       0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 176},
    {"GMX0_TX002_STAT9"            ,       0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 176},
    {"GMX0_TX003_STAT9"            ,       0x1180008001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 176},
    {"GMX0_TX000_STATS_CTL"        ,       0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64, 177},
    {"GMX0_TX001_STATS_CTL"        ,       0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64, 177},
    {"GMX0_TX002_STATS_CTL"        ,       0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64, 177},
    {"GMX0_TX003_STATS_CTL"        ,       0x1180008001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64, 177},
    {"GMX0_TX000_THRESH"           ,       0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64, 178},
    {"GMX0_TX001_THRESH"           ,       0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64, 178},
    {"GMX0_TX002_THRESH"           ,       0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64, 178},
    {"GMX0_TX003_THRESH"           ,       0x1180008001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64, 178},
    {"GMX0_TX_BP"                  ,       0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 179},
    {"GMX0_TX_COL_ATTEMPT"         ,       0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64, 180},
    {"GMX0_TX_CORRUPT"             ,       0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 181},
    {"GMX0_TX_HG2_REG1"            ,       0x1180008000558ull,  CVMX_CSR_DB_TYPE_RSL,   64, 182},
    {"GMX0_TX_HG2_REG2"            ,       0x1180008000560ull,  CVMX_CSR_DB_TYPE_RSL,   64, 183},
    {"GMX0_TX_IFG"                 ,       0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64, 184},
    {"GMX0_TX_INT_EN"              ,       0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64, 185},
    {"GMX0_TX_INT_REG"             ,       0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64, 186},
    {"GMX0_TX_JAM"                 ,       0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64, 187},
    {"GMX0_TX_LFSR"                ,       0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 188},
    {"GMX0_TX_OVR_BP"              ,       0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 189},
    {"GMX0_TX_PAUSE_PKT_DMAC"      ,       0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64, 190},
    {"GMX0_TX_PAUSE_PKT_TYPE"      ,       0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64, 191},
    {"GMX0_TX_PRTS"                ,       0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64, 192},
    {"GMX0_TX_XAUI_CTL"            ,       0x1180008000528ull,  CVMX_CSR_DB_TYPE_RSL,   64, 193},
    {"GMX0_XAUI_EXT_LOOPBACK"      ,       0x1180008000540ull,  CVMX_CSR_DB_TYPE_RSL,   64, 194},
#endif
    {NULL,0,0,0,0}
};



int do_sdump (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    uint64_t data; 
    int i;

    printf("SGMII STATS\n");

    i = 0;

    if (argv[1][0] == 'g' || argv[1][0] == 'G' )
    {

        if (argv[1][1] == 'v')
        {
            while (gmx_all_regs_56xx[i].name != NULL)
            {
                data = cvmx_read_csr(CVMX_ADD_IO_SEG(gmx_all_regs_56xx[i].address));
                printf("%s:0x%08x%08x\n", gmx_all_regs_56xx[i].name,data >> 32, data);
                i++;
            }
        }
        else
        {
            while (gmx_regs_56xx[i].name != NULL)
            {
                data = cvmx_read_csr(CVMX_ADD_IO_SEG(gmx_regs_56xx[i].address));
                printf("%s:0x%08x%08x\n", gmx_regs_56xx[i].name,data >> 32, data);
                i++;
            }
        }

    }
    else
    {
        while (pcs_regs_56xx[i].name != NULL)
        {
            data = cvmx_read_csr(CVMX_ADD_IO_SEG(pcs_regs_56xx[i].address));
            printf("%s:0x%08x%08x\n", pcs_regs_56xx[i].name,data >> 32, data);
            i++;
        }               
    }

#ifdef CONFIG_OCTEON_5651x
        get_phy_status(BOARD_10G_PHY0_MDIO_ADDR, MDIO_BUS_0);
        get_phy_status(BOARD_10G_PHY0_MDIO_ADDR, MDIO_BUS_1);
#endif

    return 0;
}

U_BOOT_CMD(
          sdump,  2,  1,  do_sdump,
          "sdump <g> or <p>    - dump GMX or PCS status reg's \n",
          );

    #include "cvmx-pcie.h"

typedef struct 
{
    char *reg_name;
    //uint64_t (*reg_func_ptr)(void);
    uint64_t addr;
} PCIE_REG_TYPE;

static PCIE_REG_TYPE pcie_regs[] = 
{
    {"CVMX_PCIEEP_CFG000",0x0000000000000000},
    {"CVMX_PCIEEP_CFG001",0x0000000000000004},
    {"CVMX_PCIEEP_CFG002",0x0000000000000008},
    {"CVMX_PCIEEP_CFG003",0x000000000000000C},
    {"CVMX_PCIEEP_CFG004",0x0000000000000010},
    {"CVMX_PCIEEP_CFG005",0x0000000000000014},
    {"CVMX_PCIEEP_CFG006",0x0000000000000018},
    {"CVMX_PCIEEP_CFG007",0x000000000000001C},
    {"CVMX_PCIEEP_CFG008",0x0000000000000020},
    {"CVMX_PCIEEP_CFG009",0x0000000000000024},
    {"CVMX_PCIEEP_CFG010",0x0000000000000028},
    {"CVMX_PCIEEP_CFG011",0x000000000000002C},
    {"CVMX_PCIEEP_CFG012",0x0000000000000030},
    {"CVMX_PCIEEP_CFG013",0x0000000000000034},
    {"CVMX_PCIEEP_CFG015",0x000000000000003C},
    {"CVMX_PCIEEP_CFG016",0x0000000000000040},
    {"CVMX_PCIEEP_CFG017",0x0000000000000044},
    {"CVMX_PCIEEP_CFG020",0x0000000000000050},
    {"CVMX_PCIEEP_CFG021",0x0000000000000054},
    {"CVMX_PCIEEP_CFG022",0x0000000000000058},
    {"CVMX_PCIEEP_CFG023",0x000000000000005C},
    {"CVMX_PCIEEP_CFG028",0x0000000000000070},
    {"CVMX_PCIEEP_CFG029",0x0000000000000074},
    {"CVMX_PCIEEP_CFG030",0x0000000000000078},
    {"CVMX_PCIEEP_CFG031",0x000000000000007C},
    {"CVMX_PCIEEP_CFG032",0x0000000000000080},
    {"CVMX_PCIEEP_CFG033",0x0000000000000084},
    {"CVMX_PCIEEP_CFG034",0x0000000000000088},
    {"CVMX_PCIEEP_CFG037",0x0000000000000094},
    {"CVMX_PCIEEP_CFG038",0x0000000000000098},
    {"CVMX_PCIEEP_CFG039",0x000000000000009C},
    {"CVMX_PCIEEP_CFG040",0x00000000000000A0},
    {"CVMX_PCIEEP_CFG041",0x00000000000000A4},
    {"CVMX_PCIEEP_CFG042",0x00000000000000A8},
    {"CVMX_PCIEEP_CFG064",0x0000000000000100},
    {"CVMX_PCIEEP_CFG065",0x0000000000000104},
    {"CVMX_PCIEEP_CFG066",0x0000000000000108},
    {"CVMX_PCIEEP_CFG067",0x000000000000010C},
    {"CVMX_PCIEEP_CFG068",0x0000000000000110},
    {"CVMX_PCIEEP_CFG069",0x0000000000000114},
    {"CVMX_PCIEEP_CFG070",0x0000000000000118},
    {"CVMX_PCIEEP_CFG071",0x000000000000011C},
    {"CVMX_PCIEEP_CFG072",0x0000000000000120},
    {"CVMX_PCIEEP_CFG073",0x0000000000000124},
    {"CVMX_PCIEEP_CFG074",0x0000000000000128},
    {"CVMX_PCIEEP_CFG448",0x0000000000000700},
    {"CVMX_PCIEEP_CFG449",0x0000000000000704},
    {"CVMX_PCIEEP_CFG450",0x0000000000000708},
    {"CVMX_PCIEEP_CFG451",0x000000000000070C},
    {"CVMX_PCIEEP_CFG452",0x0000000000000710},
    {"CVMX_PCIEEP_CFG453",0x0000000000000714},
    {"CVMX_PCIEEP_CFG454",0x0000000000000718},
    {"CVMX_PCIEEP_CFG455",0x000000000000071C},
    {"CVMX_PCIEEP_CFG456",0x0000000000000720},
    {"CVMX_PCIEEP_CFG458",0x0000000000000728},
    {"CVMX_PCIEEP_CFG459",0x000000000000072C},
    {"CVMX_PCIEEP_CFG460",0x0000000000000730},
    {"CVMX_PCIEEP_CFG461",0x0000000000000734},
    {"CVMX_PCIEEP_CFG462",0x0000000000000738},
    {"CVMX_PCIEEP_CFG463",0x000000000000073C},
    {"CVMX_PCIEEP_CFG466",0x0000000000000748},
    {"CVMX_PCIEEP_CFG467",0x000000000000074C},
    {"CVMX_PCIEEP_CFG468",0x0000000000000750},
    {"CVMX_PCIEEP_CFG490",0x00000000000007A8},
    {"CVMX_PCIEEP_CFG491",0x00000000000007AC},
    {"CVMX_PCIEEP_CFG492",0x00000000000007B0},
    {"CVMX_PCIEEP_CFG516",0x0000000000000810},
    {"CVMX_PCIEEP_CFG517",0x0000000000000814},
    {"CVMX_PCIEEP_CFG004_MASK",0x0000000080000010},
    {"CVMX_PCIEEP_CFG005_MASK",0x0000000080000014},
    {"CVMX_PCIEEP_CFG006_MASK",0x0000000080000018},
    {"CVMX_PCIEEP_CFG007_MASK",0x000000008000001C},
    {"CVMX_PCIEEP_CFG008_MASK",0x0000000080000020},
    {"CVMX_PCIEEP_CFG009_MASK",0x0000000080000024},
    {"CVMX_PCIEEP_CFG012_MASK",0x0000000080000030},
    {NULL, 0x00},
    {"PESC0_CTL_STATUS",        0x00011800C8000000ull},
    {"PESC0_DBG_INFO",          0x00011800C8000008ull},
    {"PESC0_BIST_STATUS",       0x00011800C8000018ull},
    {"PESC0_DIAG_STATUS",       0x00011800C8000020ull},
    {"PESC0_CFG_WR",            0x00011800C8000028ull},
    {"PESC0_CFG_RD",            0x00011800C8000030ull},
    {"PESC0_TLP_CREDITS",       0x00011800C8000038ull},
    {"PESC0_P2P_BAR000_START",  0x00011800C8000040ull},
    {"PESC0_P2P_BAR000_END",    0x00011800C8000048ull},
    {"PESC0_P2P_BAR001_START",  0x00011800C8000050ull},
    {"PESC0_P2P_BAR001_END",    0x00011800C8000058ull},
    {"PESC0_P2P_BAR002_START",  0x00011800C8000060ull},
    {"PESC0_P2P_BAR002_END",    0x00011800C8000068ull},
    {"PESC0_P2P_BAR003_START",  0x00011800C8000070ull},
    {"PESC0_P2P_BAR003_END",    0x00011800C8000078ull},
    {"PESC0_P2N_BAR0_START",    0x00011800C8000080ull},
    {"PESC0_P2N_BAR1_START",    0x00011800C8000088ull},
    {"PESC0_P2N_BAR2_START",    0x00011800C8000090ull},
    {"PESC0_CPL_LUT_VALID",     0x00011800C8000098ull},
    {"PESC0_DBG_INFO_EN",       0x00011800C80000A0ull},
    {"PESC0_CTL_STATUS2",       0x00011800C8000400ull},
    {"PESC0_BIST_STATUS2",      0x00011800C8000418ull},
    {"NPEI_DBG_DATA",           0x00011F0000008510ull},
    {"NPEI_CTL_STATUS",         0x00011F0000008570ull},
    {"NPEI_BIST_STATUS",        0x00011F0000008580ull},
    {"NPEI_DATA_OUT_CNT",       0x00011F00000085F0ull},
    {"NPEI_STATE1",             0x00011F0000008620ull},
    {"NPEI_STATE2",             0x00011F0000008630ull},
    {"NPEI_STATE3",             0x00011F0000008640ull},
    {"NPEI_SCRATCH_1",          0x00011F0000008270ull},
    {NULL, 0x00},
};

int do_reg_pcie (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    uint32_t val;
    uint32_t addr;

    if (argv[1][0] == 'w')//write
    {
        val = cvmx_pcie_cfgx_read(0, CVMX_PCIEEPX_CFG001(0));
        printf("PCI-e reg read:0x%08x\n", val);

        addr = simple_strtoul(argv[2], NULL, 10);
        val = simple_strtoul(argv[3], NULL, 10);
        cvmx_pcie_cfgx_write(0, addr, val);
        printf("PCI-e reg wrote:0x%08x\n", val);
    }
    else if (argv[1][0] == 'r')//read
    {
        addr = simple_strtoul(argv[2], NULL, 10);
        val = cvmx_pcie_cfgx_read(0,addr);
        printf("%x:	0x%08x\n",addr, val);
    }
    else if (argv[1][0] == 'd')//read
    {
        int i = 0;

        while (pcie_regs[i].reg_name != NULL)
        {
            val = cvmx_pcie_cfgx_read(0, pcie_regs[i].addr);
            printf("%s:0x%08x\n", pcie_regs[i].reg_name, val);
            i++;
        }

        i++;
        while (pcie_regs[i].reg_name != NULL)
        {
            val = cvmx_read_csr(CVMX_ADD_IO_SEG(pcie_regs[i].addr));
            printf("%s:0x%08x\n", pcie_regs[i].reg_name, val);
            i++;
        }
    }

    return 0;
}
U_BOOT_CMD(
          pcie,   4,  1,  do_reg_pcie,
          "pcie     - pcie <flag> <addr>; i.e. pcie r 0x04 (reads from pci-e cfg reg 001) flags - r(read), w(write), d(dump)\n",
          );

typedef struct 
{
    char *reg_name;
    uint16_t reg_addr;
    uint8_t  dev_type;
} AMCC_REG_TYPE;

#if defined(CONFIG_OCTEON_DYNAMIC_BOARD_DETECTION)
static AMCC_REG_TYPE amcc_regs[] = 
{
    /* print out XAUi registers */
    {"3.d7fd",                0xd7fd, AMCC_DEV_ADDR_PCS},
    {"3.0021",                0x0021, AMCC_DEV_ADDR_PCS},
    {"1.c001",      0xC001, AMCC_DEV_ADDR_PMA_PMD},
    {"4.0018",          0x0018, AMCC_DEV_ADDR_XGXS},
    {"AMCC_XGXS_VENDOR_SPECIFIC_1_REG",         0xC000, AMCC_DEV_ADDR_XGXS},
    {"AMCC_XGXS_PHY_XS_XAUI_LANE_0_ERR_CNT",    0xC030, AMCC_DEV_ADDR_XGXS},
    {"AMCC_XGXS_PHY_XS_XAUI_LANE_1_ERR_CNT",    0xC031, AMCC_DEV_ADDR_XGXS},
    {"AMCC_XGXS_PHY_XS_XAUI_LANE_2_ERR_CNT",    0xC032, AMCC_DEV_ADDR_XGXS},
    {"AMCC_XGXS_PHY_XS_XAUI_LANE_3_ERR_CNT",    0xC033, AMCC_DEV_ADDR_XGXS},
    {"1.9003",          0x9003, AMCC_DEV_ADDR_PMA_PMD},
    {"1.9004",          0x9004, AMCC_DEV_ADDR_PMA_PMD},
    {"1.000A",          0x000A, AMCC_DEV_ADDR_PMA_PMD},
    {"1.D002",          0xD002, AMCC_DEV_ADDR_PMA_PMD},
    {"1.D003",          0xD003, AMCC_DEV_ADDR_PMA_PMD},

    
    {NULL, 0x00, 0x00},
};
#endif /*CONFIG_OCTEON_DYNAMIC_BOARD_DETECTION*/

#if defined(CONFIG_OCTEON_DYNAMIC_BOARD_DETECTION)

extern void phyRegRead (uint8_t addr, uint16_t reg, uint16_t *val, uint8_t dev_type);
extern void phyRegWrite(uint8_t addr, uint16_t reg, uint16_t mask, uint16_t newVal, int wait, uint8_t dev_type);

int do_reg_amcc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
    uint16_t data;
    int rc;
    uint16_t reg;
    uint16_t mdio_addr;
    uint16_t logic_block;
    uint16_t val;

    rc = 0;

    if (IS_10G_PHY_PRESENT)
    {
        /* just do the test dump and get out */
        if (argv[1][0] == 'd')
        {
            int i = 0;
            while (amcc_regs[i].reg_name != NULL)
            {
                phyRegRead(BOARD_10G_PHY0_MDIO_ADDR, amcc_regs[i].reg_addr, &data, amcc_regs[i].dev_type);
                printf("PHY0:%d.%04x:0x%04x\n",amcc_regs[i].dev_type , amcc_regs[i].reg_addr, data);
                phyRegRead(BOARD_10G_PHY1_MDIO_ADDR, amcc_regs[i].reg_addr, &data, amcc_regs[i].dev_type);
                printf("PHY1:%d.%04x:0x%04x\n",amcc_regs[i].dev_type , amcc_regs[i].reg_addr, data);
                i++;
            }
            return rc;
        }

        //              0      1             2                             3                      4            5
        // "amcc     - amcc [r or w] [phy number - 0 or 1] [PMA(1), WIS(2), PCS(3), XGXS(4)] [register] [value - write only]\n",
        mdio_addr = simple_strtoul(argv[2], NULL, 10);
        logic_block = simple_strtoul(argv[3], NULL, 10);
        reg = simple_strtoul(argv[4], NULL, 10);

        phyRegRead(mdio_addr, reg, &data, logic_block);
        printf("READ: %s 0x%04x:0x%04x\n", 
                   (logic_block == 1) ? "PMA/PMD" : (logic_block == 2) ? "WIS" : (logic_block == 3) ? "PCS" : "XGXS", 
                   reg,  
                   data);

        if (argv[1][0] == 'w')//write
        {
            val = simple_strtoul(argv[5], NULL, 10);

            phyRegWrite(mdio_addr, reg, 0x0000, val, 0, logic_block);
        }
        
    }
    else
    {
        rc =1;
        printf("AMCC 10G phy is not supported on this board\n");
    }

    return rc;
}
U_BOOT_CMD(
          amcc,   6,  1,  do_reg_amcc,
          "amcc     - amcc [r or w] [phy number - 0 or 1] [PMA(0), WIS(2), PCS(3), XGXS(4)] [register] [value - write only]\n",
          );
#endif /*CONFIG_OCTEON_DYNAMIC_BOARD_DETECTION*/

#endif	/* CFG_CMD_NET */
